Software APIs
dt_gpio.h
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1// Copyright lowRISC contributors (OpenTitan project).
2// Licensed under the Apache License, Version 2.0, see LICENSE for details.
3// SPDX-License-Identifier: Apache-2.0
4//
5// Device table API auto-generated by `dtgen`
6
7#ifndef OPENTITAN_DT_GPIO_H_
8#define OPENTITAN_DT_GPIO_H_
9
10/**
11 * @file
12 * @brief Device Tables (DT) for IP gpio and top earlgrey.
13 *
14 * This file contains the type definitions and global functions of the gpio.
15 */
16
17#include "dt_api.h"
18#include <stdint.h>
19
20
21
22
23
24/**
25 * List of instances.
26 */
27typedef enum dt_gpio {
28 kDtGpio = 0, /**< gpio */
29 kDtGpioFirst = 0, /**< \internal First instance */
30 kDtGpioCount = 1, /**< \internal Number of instances */
31} dt_gpio_t;
32
33/**
34 * List of register blocks.
35 *
36 * Register blocks are guaranteed to start at 0 and to be consecutively numbered.
37 */
38typedef enum dt_gpio_reg_block {
39 kDtGpioRegBlockCore = 0, /**< */
40 kDtGpioRegBlockCount = 1, /**< \internal Number of register blocks */
41} dt_gpio_reg_block_t;
42
43/** Primary register block (associated with the "primary" set of registers that control the IP). */
44static const dt_gpio_reg_block_t kDtGpioRegBlockPrimary = kDtGpioRegBlockCore;
45
46/**
47 * List of IRQs.
48 *
49 * IRQs are guaranteed to be numbered consecutively from 0.
50 */
51typedef enum dt_gpio_irq {
52 kDtGpioIrqGpio0 = 0, /**< raised if any of GPIO pin detects configured interrupt mode */
53 kDtGpioIrqGpio1 = 1, /**< raised if any of GPIO pin detects configured interrupt mode */
54 kDtGpioIrqGpio2 = 2, /**< raised if any of GPIO pin detects configured interrupt mode */
55 kDtGpioIrqGpio3 = 3, /**< raised if any of GPIO pin detects configured interrupt mode */
56 kDtGpioIrqGpio4 = 4, /**< raised if any of GPIO pin detects configured interrupt mode */
57 kDtGpioIrqGpio5 = 5, /**< raised if any of GPIO pin detects configured interrupt mode */
58 kDtGpioIrqGpio6 = 6, /**< raised if any of GPIO pin detects configured interrupt mode */
59 kDtGpioIrqGpio7 = 7, /**< raised if any of GPIO pin detects configured interrupt mode */
60 kDtGpioIrqGpio8 = 8, /**< raised if any of GPIO pin detects configured interrupt mode */
61 kDtGpioIrqGpio9 = 9, /**< raised if any of GPIO pin detects configured interrupt mode */
62 kDtGpioIrqGpio10 = 10, /**< raised if any of GPIO pin detects configured interrupt mode */
63 kDtGpioIrqGpio11 = 11, /**< raised if any of GPIO pin detects configured interrupt mode */
64 kDtGpioIrqGpio12 = 12, /**< raised if any of GPIO pin detects configured interrupt mode */
65 kDtGpioIrqGpio13 = 13, /**< raised if any of GPIO pin detects configured interrupt mode */
66 kDtGpioIrqGpio14 = 14, /**< raised if any of GPIO pin detects configured interrupt mode */
67 kDtGpioIrqGpio15 = 15, /**< raised if any of GPIO pin detects configured interrupt mode */
68 kDtGpioIrqGpio16 = 16, /**< raised if any of GPIO pin detects configured interrupt mode */
69 kDtGpioIrqGpio17 = 17, /**< raised if any of GPIO pin detects configured interrupt mode */
70 kDtGpioIrqGpio18 = 18, /**< raised if any of GPIO pin detects configured interrupt mode */
71 kDtGpioIrqGpio19 = 19, /**< raised if any of GPIO pin detects configured interrupt mode */
72 kDtGpioIrqGpio20 = 20, /**< raised if any of GPIO pin detects configured interrupt mode */
73 kDtGpioIrqGpio21 = 21, /**< raised if any of GPIO pin detects configured interrupt mode */
74 kDtGpioIrqGpio22 = 22, /**< raised if any of GPIO pin detects configured interrupt mode */
75 kDtGpioIrqGpio23 = 23, /**< raised if any of GPIO pin detects configured interrupt mode */
76 kDtGpioIrqGpio24 = 24, /**< raised if any of GPIO pin detects configured interrupt mode */
77 kDtGpioIrqGpio25 = 25, /**< raised if any of GPIO pin detects configured interrupt mode */
78 kDtGpioIrqGpio26 = 26, /**< raised if any of GPIO pin detects configured interrupt mode */
79 kDtGpioIrqGpio27 = 27, /**< raised if any of GPIO pin detects configured interrupt mode */
80 kDtGpioIrqGpio28 = 28, /**< raised if any of GPIO pin detects configured interrupt mode */
81 kDtGpioIrqGpio29 = 29, /**< raised if any of GPIO pin detects configured interrupt mode */
82 kDtGpioIrqGpio30 = 30, /**< raised if any of GPIO pin detects configured interrupt mode */
83 kDtGpioIrqGpio31 = 31, /**< raised if any of GPIO pin detects configured interrupt mode */
84 kDtGpioIrqCount = 32, /**< \internal Number of IRQs */
85} dt_gpio_irq_t;
86
87/**
88 * List of Alerts.
89 *
90 * Alerts are guaranteed to be numbered consecutively from 0.
91 */
92typedef enum dt_gpio_alert {
93 kDtGpioAlertFatalFault = 0, /**< This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected. */
94 kDtGpioAlertCount = 1, /**< \internal Number of Alerts */
95} dt_gpio_alert_t;
96
97/**
98 * List of clock ports.
99 *
100 * Clock ports are guaranteed to be numbered consecutively from 0.
101 */
102typedef enum dt_gpio_clock {
103 kDtGpioClockClk = 0, /**< Clock port clk_i */
104 kDtGpioClockCount = 1, /**< \internal Number of clock ports */
105} dt_gpio_clock_t;
106
107/**
108 * List of reset ports.
109 *
110 * Reset ports are guaranteed to be numbered consecutively from 0.
111 */
112typedef enum dt_gpio_reset {
113 kDtGpioResetRst = 0, /**< Reset port rst_ni */
114 kDtGpioResetCount = 1, /**< \internal Number of reset ports */
115} dt_gpio_reset_t;
116
117/**
118 * List of peripheral I/O.
119 *
120 * Peripheral I/O are guaranteed to be numbered consecutively from 0.
121 */
122typedef enum dt_gpio_periph_io {
123 kDtGpioPeriphIoGpio0 = 0, /**< */
124 kDtGpioPeriphIoGpio1 = 1, /**< */
125 kDtGpioPeriphIoGpio2 = 2, /**< */
126 kDtGpioPeriphIoGpio3 = 3, /**< */
127 kDtGpioPeriphIoGpio4 = 4, /**< */
128 kDtGpioPeriphIoGpio5 = 5, /**< */
129 kDtGpioPeriphIoGpio6 = 6, /**< */
130 kDtGpioPeriphIoGpio7 = 7, /**< */
131 kDtGpioPeriphIoGpio8 = 8, /**< */
132 kDtGpioPeriphIoGpio9 = 9, /**< */
133 kDtGpioPeriphIoGpio10 = 10, /**< */
134 kDtGpioPeriphIoGpio11 = 11, /**< */
135 kDtGpioPeriphIoGpio12 = 12, /**< */
136 kDtGpioPeriphIoGpio13 = 13, /**< */
137 kDtGpioPeriphIoGpio14 = 14, /**< */
138 kDtGpioPeriphIoGpio15 = 15, /**< */
139 kDtGpioPeriphIoGpio16 = 16, /**< */
140 kDtGpioPeriphIoGpio17 = 17, /**< */
141 kDtGpioPeriphIoGpio18 = 18, /**< */
142 kDtGpioPeriphIoGpio19 = 19, /**< */
143 kDtGpioPeriphIoGpio20 = 20, /**< */
144 kDtGpioPeriphIoGpio21 = 21, /**< */
145 kDtGpioPeriphIoGpio22 = 22, /**< */
146 kDtGpioPeriphIoGpio23 = 23, /**< */
147 kDtGpioPeriphIoGpio24 = 24, /**< */
148 kDtGpioPeriphIoGpio25 = 25, /**< */
149 kDtGpioPeriphIoGpio26 = 26, /**< */
150 kDtGpioPeriphIoGpio27 = 27, /**< */
151 kDtGpioPeriphIoGpio28 = 28, /**< */
152 kDtGpioPeriphIoGpio29 = 29, /**< */
153 kDtGpioPeriphIoGpio30 = 30, /**< */
154 kDtGpioPeriphIoGpio31 = 31, /**< */
155 kDtGpioPeriphIoCount = 32, /**< \internal Number of peripheral I/O */
156} dt_gpio_periph_io_t;
157
158/**
159 * List of supported hardware features.
160 */
161#define OPENTITAN_GPIO_HAS_IN_INTR_CTRL 1
162#define OPENTITAN_GPIO_HAS_IN_FILTER 1
163#define OPENTITAN_GPIO_HAS_OUT_MASK 1
164
165
166
167/**
168 * Get the gpio instance from an instance ID
169 *
170 * For example, `dt_uart_from_instance_id(kDtInstanceIdUart3) == kDtUart3`.
171 *
172 * @param inst_id Instance ID.
173 * @return A gpio instance.
174 *
175 * **Note:** This function only makes sense if the instance ID has device type gpio,
176 * otherwise the returned value is unspecified.
177 */
178dt_gpio_t dt_gpio_from_instance_id(dt_instance_id_t inst_id);
179
180/**
181 * Get the instance ID of an instance.
182 *
183 * @param dt Instance of gpio.
184 * @return The instance ID of that instance.
185 */
186dt_instance_id_t dt_gpio_instance_id(dt_gpio_t dt);
187
188/**
189 * Get the register base address of an instance.
190 *
191 * @param dt Instance of gpio.
192 * @param reg_block The register block requested.
193 * @return The register base address of the requested block.
194 */
195uint32_t dt_gpio_reg_block(
196 dt_gpio_t dt,
197 dt_gpio_reg_block_t reg_block);
198
199/**
200 * Get the primary register base address of an instance.
201 *
202 * This is just a convenience function, equivalent to
203 * `dt_gpio_reg_block(dt, kDtGpioRegBlockCore)`
204 *
205 * @param dt Instance of gpio.
206 * @return The register base address of the primary register block.
207 */
208static inline uint32_t dt_gpio_primary_reg_block(
209 dt_gpio_t dt) {
210 return dt_gpio_reg_block(dt, kDtGpioRegBlockCore);
211}
212
213/**
214 * Get the PLIC ID of a gpio IRQ for a given instance.
215 *
216 * If the instance is not connected to the PLIC, this function
217 * will return `kDtPlicIrqIdNone`.
218 *
219 * @param dt Instance of gpio.
220 * @param irq A gpio IRQ.
221 * @return The PLIC ID of the IRQ of this instance.
222 */
223dt_plic_irq_id_t dt_gpio_irq_to_plic_id(
224 dt_gpio_t dt,
225 dt_gpio_irq_t irq);
226
227/**
228 * Convert a global IRQ ID to a local gpio IRQ type.
229 *
230 * @param dt Instance of gpio.
231 * @param irq A PLIC ID that belongs to this instance.
232 * @return The gpio IRQ, or `kDtGpioIrqCount`.
233 *
234 * **Note:** This function assumes that the PLIC ID belongs to the instance
235 * of gpio passed in parameter. In other words, it must be the case that
236 * `dt_gpio_instance_id(dt) == dt_plic_id_to_instance_id(irq)`. Otherwise, this function
237 * will return `kDtGpioIrqCount`.
238 */
239dt_gpio_irq_t dt_gpio_irq_from_plic_id(
240 dt_gpio_t dt,
241 dt_plic_irq_id_t irq);
242
243
244/**
245 * Get the alert ID of a gpio alert for a given instance.
246 *
247 * **Note:** This function only makes sense if the instance is connected to the Alert Handler. For any
248 * instances where the instance is not connected, the return value is unspecified.
249 *
250 * @param dt Instance of gpio.
251 * @param alert A gpio alert.
252 * @return The Alert Handler alert ID of the alert of this instance.
253 */
254dt_alert_id_t dt_gpio_alert_to_alert_id(
255 dt_gpio_t dt,
256 dt_gpio_alert_t alert);
257
258/**
259 * Convert a global alert ID to a local gpio alert type.
260 *
261 * @param dt Instance of gpio.
262 * @param alert A global alert ID that belongs to this instance.
263 * @return The gpio alert, or `kDtGpioAlertCount`.
264 *
265 * **Note:** This function assumes that the global alert ID belongs to the
266 * instance of gpio passed in parameter. In other words, it must be the case
267 * that `dt_gpio_instance_id(dt) == dt_alert_id_to_instance_id(alert)`. Otherwise,
268 * this function will return `kDtGpioAlertCount`.
269 */
270dt_gpio_alert_t dt_gpio_alert_from_alert_id(
271 dt_gpio_t dt,
272 dt_alert_id_t alert);
273
274
275/**
276 * Get the peripheral I/O description of an instance.
277 *
278 * @param dt Instance of gpio.
279 * @param sig Requested peripheral I/O.
280 * @return Description of the requested peripheral I/O for this instance.
281 */
282dt_periph_io_t dt_gpio_periph_io(
283 dt_gpio_t dt,
284 dt_gpio_periph_io_t sig);
285
286/**
287 * Get the clock signal connected to a clock port of an instance.
288 *
289 * @param dt Instance of gpio.
290 * @param clk Clock port.
291 * @return Clock signal.
292 */
293dt_clock_t dt_gpio_clock(
294 dt_gpio_t dt,
295 dt_gpio_clock_t clk);
296
297/**
298 * Get the reset signal connected to a reset port of an instance.
299 *
300 * @param dt Instance of gpio.
301 * @param rst Reset port.
302 * @return Reset signal.
303 */
304dt_reset_t dt_gpio_reset(
305 dt_gpio_t dt,
306 dt_gpio_reset_t rst);
307
308
309
310/**
311 * Get the number of input period counters.
312 *
313 * @param dt Instance of gpio.
314 * @return number of input period counters.
315 */
316uint8_t dt_gpio_input_period_counter_count(dt_gpio_t dt);
317
318
319
320#endif // OPENTITAN_DT_GPIO_H_