Software APIs
dt_gpio.h
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1// Copyright lowRISC contributors (OpenTitan project).
2// Licensed under the Apache License, Version 2.0, see LICENSE for details.
3// SPDX-License-Identifier: Apache-2.0
4//
5// Device table API auto-generated by `dtgen`
6
7#ifndef OPENTITAN_DT_GPIO_H_
8#define OPENTITAN_DT_GPIO_H_
9
10#ifdef __cplusplus
11extern "C" {
12#endif // __cplusplus
13
14/**
15 * @file
16 * @brief Device Tables (DT) for IP gpio and top earlgrey.
17 *
18 * This file contains the type definitions and global functions of the gpio.
19 */
20
21#include "dt_api.h"
22#include <stdint.h>
23
24
25
26
27
28/**
29 * List of instances.
30 */
31typedef enum dt_gpio {
32 kDtGpio = 0, /**< gpio */
33 kDtGpioFirst = 0, /**< \internal First instance */
34 kDtGpioCount = 1, /**< \internal Number of instances */
35} dt_gpio_t;
36
37/**
38 * List of register blocks.
39 *
40 * Register blocks are guaranteed to start at 0 and to be consecutively numbered.
41 */
42typedef enum dt_gpio_reg_block {
43 kDtGpioRegBlockCore = 0, /**< */
44 kDtGpioRegBlockCount = 1, /**< \internal Number of register blocks */
45} dt_gpio_reg_block_t;
46
47/** Primary register block (associated with the "primary" set of registers that control the IP). */
48static const dt_gpio_reg_block_t kDtGpioRegBlockPrimary = kDtGpioRegBlockCore;
49
50/**
51 * List of IRQs.
52 *
53 * IRQs are guaranteed to be numbered consecutively from 0.
54 */
55typedef enum dt_gpio_irq {
56 kDtGpioIrqGpio0 = 0, /**< raised if any of GPIO pin detects configured interrupt mode */
57 kDtGpioIrqGpio1 = 1, /**< raised if any of GPIO pin detects configured interrupt mode */
58 kDtGpioIrqGpio2 = 2, /**< raised if any of GPIO pin detects configured interrupt mode */
59 kDtGpioIrqGpio3 = 3, /**< raised if any of GPIO pin detects configured interrupt mode */
60 kDtGpioIrqGpio4 = 4, /**< raised if any of GPIO pin detects configured interrupt mode */
61 kDtGpioIrqGpio5 = 5, /**< raised if any of GPIO pin detects configured interrupt mode */
62 kDtGpioIrqGpio6 = 6, /**< raised if any of GPIO pin detects configured interrupt mode */
63 kDtGpioIrqGpio7 = 7, /**< raised if any of GPIO pin detects configured interrupt mode */
64 kDtGpioIrqGpio8 = 8, /**< raised if any of GPIO pin detects configured interrupt mode */
65 kDtGpioIrqGpio9 = 9, /**< raised if any of GPIO pin detects configured interrupt mode */
66 kDtGpioIrqGpio10 = 10, /**< raised if any of GPIO pin detects configured interrupt mode */
67 kDtGpioIrqGpio11 = 11, /**< raised if any of GPIO pin detects configured interrupt mode */
68 kDtGpioIrqGpio12 = 12, /**< raised if any of GPIO pin detects configured interrupt mode */
69 kDtGpioIrqGpio13 = 13, /**< raised if any of GPIO pin detects configured interrupt mode */
70 kDtGpioIrqGpio14 = 14, /**< raised if any of GPIO pin detects configured interrupt mode */
71 kDtGpioIrqGpio15 = 15, /**< raised if any of GPIO pin detects configured interrupt mode */
72 kDtGpioIrqGpio16 = 16, /**< raised if any of GPIO pin detects configured interrupt mode */
73 kDtGpioIrqGpio17 = 17, /**< raised if any of GPIO pin detects configured interrupt mode */
74 kDtGpioIrqGpio18 = 18, /**< raised if any of GPIO pin detects configured interrupt mode */
75 kDtGpioIrqGpio19 = 19, /**< raised if any of GPIO pin detects configured interrupt mode */
76 kDtGpioIrqGpio20 = 20, /**< raised if any of GPIO pin detects configured interrupt mode */
77 kDtGpioIrqGpio21 = 21, /**< raised if any of GPIO pin detects configured interrupt mode */
78 kDtGpioIrqGpio22 = 22, /**< raised if any of GPIO pin detects configured interrupt mode */
79 kDtGpioIrqGpio23 = 23, /**< raised if any of GPIO pin detects configured interrupt mode */
80 kDtGpioIrqGpio24 = 24, /**< raised if any of GPIO pin detects configured interrupt mode */
81 kDtGpioIrqGpio25 = 25, /**< raised if any of GPIO pin detects configured interrupt mode */
82 kDtGpioIrqGpio26 = 26, /**< raised if any of GPIO pin detects configured interrupt mode */
83 kDtGpioIrqGpio27 = 27, /**< raised if any of GPIO pin detects configured interrupt mode */
84 kDtGpioIrqGpio28 = 28, /**< raised if any of GPIO pin detects configured interrupt mode */
85 kDtGpioIrqGpio29 = 29, /**< raised if any of GPIO pin detects configured interrupt mode */
86 kDtGpioIrqGpio30 = 30, /**< raised if any of GPIO pin detects configured interrupt mode */
87 kDtGpioIrqGpio31 = 31, /**< raised if any of GPIO pin detects configured interrupt mode */
88 kDtGpioIrqCount = 32, /**< \internal Number of IRQs */
89} dt_gpio_irq_t;
90
91/**
92 * List of Alerts.
93 *
94 * Alerts are guaranteed to be numbered consecutively from 0.
95 */
96typedef enum dt_gpio_alert {
97 kDtGpioAlertFatalFault = 0, /**< This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected. */
98 kDtGpioAlertCount = 1, /**< \internal Number of Alerts */
99} dt_gpio_alert_t;
100
101/**
102 * List of clock ports.
103 *
104 * Clock ports are guaranteed to be numbered consecutively from 0.
105 */
106typedef enum dt_gpio_clock {
107 kDtGpioClockClk = 0, /**< Clock port clk_i */
108 kDtGpioClockCount = 1, /**< \internal Number of clock ports */
109} dt_gpio_clock_t;
110
111/**
112 * List of reset ports.
113 *
114 * Reset ports are guaranteed to be numbered consecutively from 0.
115 */
116typedef enum dt_gpio_reset {
117 kDtGpioResetRst = 0, /**< Reset port rst_ni */
118 kDtGpioResetCount = 1, /**< \internal Number of reset ports */
119} dt_gpio_reset_t;
120
121/**
122 * List of peripheral I/O.
123 *
124 * Peripheral I/O are guaranteed to be numbered consecutively from 0.
125 */
126typedef enum dt_gpio_periph_io {
127 kDtGpioPeriphIoGpio0 = 0, /**< */
128 kDtGpioPeriphIoGpio1 = 1, /**< */
129 kDtGpioPeriphIoGpio2 = 2, /**< */
130 kDtGpioPeriphIoGpio3 = 3, /**< */
131 kDtGpioPeriphIoGpio4 = 4, /**< */
132 kDtGpioPeriphIoGpio5 = 5, /**< */
133 kDtGpioPeriphIoGpio6 = 6, /**< */
134 kDtGpioPeriphIoGpio7 = 7, /**< */
135 kDtGpioPeriphIoGpio8 = 8, /**< */
136 kDtGpioPeriphIoGpio9 = 9, /**< */
137 kDtGpioPeriphIoGpio10 = 10, /**< */
138 kDtGpioPeriphIoGpio11 = 11, /**< */
139 kDtGpioPeriphIoGpio12 = 12, /**< */
140 kDtGpioPeriphIoGpio13 = 13, /**< */
141 kDtGpioPeriphIoGpio14 = 14, /**< */
142 kDtGpioPeriphIoGpio15 = 15, /**< */
143 kDtGpioPeriphIoGpio16 = 16, /**< */
144 kDtGpioPeriphIoGpio17 = 17, /**< */
145 kDtGpioPeriphIoGpio18 = 18, /**< */
146 kDtGpioPeriphIoGpio19 = 19, /**< */
147 kDtGpioPeriphIoGpio20 = 20, /**< */
148 kDtGpioPeriphIoGpio21 = 21, /**< */
149 kDtGpioPeriphIoGpio22 = 22, /**< */
150 kDtGpioPeriphIoGpio23 = 23, /**< */
151 kDtGpioPeriphIoGpio24 = 24, /**< */
152 kDtGpioPeriphIoGpio25 = 25, /**< */
153 kDtGpioPeriphIoGpio26 = 26, /**< */
154 kDtGpioPeriphIoGpio27 = 27, /**< */
155 kDtGpioPeriphIoGpio28 = 28, /**< */
156 kDtGpioPeriphIoGpio29 = 29, /**< */
157 kDtGpioPeriphIoGpio30 = 30, /**< */
158 kDtGpioPeriphIoGpio31 = 31, /**< */
159 kDtGpioPeriphIoCount = 32, /**< \internal Number of peripheral I/O */
160} dt_gpio_periph_io_t;
161
162/**
163 * List of supported hardware features.
164 */
165#define OPENTITAN_GPIO_HAS_IN_INTR_CTRL 1
166#define OPENTITAN_GPIO_HAS_IN_FILTER 1
167#define OPENTITAN_GPIO_HAS_OUT_MASK 1
168
169
170
171/**
172 * Get the gpio instance from an instance ID
173 *
174 * For example, `dt_uart_from_instance_id(kDtInstanceIdUart3) == kDtUart3`.
175 *
176 * @param inst_id Instance ID.
177 * @return A gpio instance.
178 *
179 * **Note:** This function only makes sense if the instance ID has device type gpio,
180 * otherwise the returned value is unspecified.
181 */
182dt_gpio_t dt_gpio_from_instance_id(dt_instance_id_t inst_id);
183
184/**
185 * Get the instance ID of an instance.
186 *
187 * @param dt Instance of gpio.
188 * @return The instance ID of that instance.
189 */
190dt_instance_id_t dt_gpio_instance_id(dt_gpio_t dt);
191
192/**
193 * Get the register base address of an instance.
194 *
195 * @param dt Instance of gpio.
196 * @param reg_block The register block requested.
197 * @return The register base address of the requested block.
198 */
199uint32_t dt_gpio_reg_block(
200 dt_gpio_t dt,
201 dt_gpio_reg_block_t reg_block);
202
203/**
204 * Get the primary register base address of an instance.
205 *
206 * This is just a convenience function, equivalent to
207 * `dt_gpio_reg_block(dt, kDtGpioRegBlockCore)`
208 *
209 * @param dt Instance of gpio.
210 * @return The register base address of the primary register block.
211 */
212static inline uint32_t dt_gpio_primary_reg_block(
213 dt_gpio_t dt) {
214 return dt_gpio_reg_block(dt, kDtGpioRegBlockCore);
215}
216
217/**
218 * Get the PLIC ID of a gpio IRQ for a given instance.
219 *
220 * If the instance is not connected to the PLIC, this function
221 * will return `kDtPlicIrqIdNone`.
222 *
223 * @param dt Instance of gpio.
224 * @param irq A gpio IRQ.
225 * @return The PLIC ID of the IRQ of this instance.
226 */
227dt_plic_irq_id_t dt_gpio_irq_to_plic_id(
228 dt_gpio_t dt,
229 dt_gpio_irq_t irq);
230
231/**
232 * Convert a global IRQ ID to a local gpio IRQ type.
233 *
234 * @param dt Instance of gpio.
235 * @param irq A PLIC ID that belongs to this instance.
236 * @return The gpio IRQ, or `kDtGpioIrqCount`.
237 *
238 * **Note:** This function assumes that the PLIC ID belongs to the instance
239 * of gpio passed in parameter. In other words, it must be the case that
240 * `dt_gpio_instance_id(dt) == dt_plic_id_to_instance_id(irq)`. Otherwise, this function
241 * will return `kDtGpioIrqCount`.
242 */
243dt_gpio_irq_t dt_gpio_irq_from_plic_id(
244 dt_gpio_t dt,
245 dt_plic_irq_id_t irq);
246
247
248/**
249 * Get the alert ID of a gpio alert for a given instance.
250 *
251 * **Note:** This function only makes sense if the instance is connected to the Alert Handler. For any
252 * instances where the instance is not connected, the return value is unspecified.
253 *
254 * @param dt Instance of gpio.
255 * @param alert A gpio alert.
256 * @return The Alert Handler alert ID of the alert of this instance.
257 */
258dt_alert_id_t dt_gpio_alert_to_alert_id(
259 dt_gpio_t dt,
260 dt_gpio_alert_t alert);
261
262/**
263 * Convert a global alert ID to a local gpio alert type.
264 *
265 * @param dt Instance of gpio.
266 * @param alert A global alert ID that belongs to this instance.
267 * @return The gpio alert, or `kDtGpioAlertCount`.
268 *
269 * **Note:** This function assumes that the global alert ID belongs to the
270 * instance of gpio passed in parameter. In other words, it must be the case
271 * that `dt_gpio_instance_id(dt) == dt_alert_id_to_instance_id(alert)`. Otherwise,
272 * this function will return `kDtGpioAlertCount`.
273 */
274dt_gpio_alert_t dt_gpio_alert_from_alert_id(
275 dt_gpio_t dt,
276 dt_alert_id_t alert);
277
278
279/**
280 * Get the peripheral I/O description of an instance.
281 *
282 * @param dt Instance of gpio.
283 * @param sig Requested peripheral I/O.
284 * @return Description of the requested peripheral I/O for this instance.
285 */
286dt_periph_io_t dt_gpio_periph_io(
287 dt_gpio_t dt,
288 dt_gpio_periph_io_t sig);
289
290/**
291 * Get the clock signal connected to a clock port of an instance.
292 *
293 * @param dt Instance of gpio.
294 * @param clk Clock port.
295 * @return Clock signal.
296 */
297dt_clock_t dt_gpio_clock(
298 dt_gpio_t dt,
299 dt_gpio_clock_t clk);
300
301/**
302 * Get the reset signal connected to a reset port of an instance.
303 *
304 * @param dt Instance of gpio.
305 * @param rst Reset port.
306 * @return Reset signal.
307 */
308dt_reset_t dt_gpio_reset(
309 dt_gpio_t dt,
310 dt_gpio_reset_t rst);
311
312
313
314/**
315 * Get the number of input period counters.
316 *
317 * @param dt Instance of gpio.
318 * @return number of input period counters.
319 */
320uint8_t dt_gpio_input_period_counter_count(dt_gpio_t dt);
321
322
323
324#ifdef __cplusplus
325} // extern "C"
326#endif // __cplusplus
327
328#endif // OPENTITAN_DT_GPIO_H_