dt_clkmgr.h

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// Copyright lowRISC contributors (OpenTitan project).
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// Device table API auto-generated by `dtgen`
 
#ifndef OPENTITAN_DT_CLKMGR_H_
#define OPENTITAN_DT_CLKMGR_H_
 
#ifdef __cplusplus
extern "C" {
#endif  // __cplusplus
 
/**
 * @file
 * @brief Device Tables (DT) for IP clkmgr and top earlgrey.
 *
 * This file contains the type definitions and global functions of the clkmgr.
 */
 
#include "hw/top/dt/dt_api.h"
#include <stdint.h>
 
 
#include "sw/device/lib/base/bitfield.h"
 
 
/**
 * List of instances.
 */
typedef enum dt_clkmgr {
  kDtClkmgrAon = 0, /**< clkmgr_aon */
  kDtClkmgrFirst = 0, /**< \internal First instance */
  kDtClkmgrCount = 1, /**< \internal Number of instances */
} dt_clkmgr_t;
 
/**
 * List of register blocks.
 *
 * Register blocks are guaranteed to start at 0 and to be consecutively numbered.
 */
typedef enum dt_clkmgr_reg_block {
  kDtClkmgrRegBlockCore = 0, /**<  */
  kDtClkmgrRegBlockCount = 1, /**< \internal Number of register blocks */
} dt_clkmgr_reg_block_t;
 
/** Primary register block (associated with the "primary" set of registers that control the IP). */
static const dt_clkmgr_reg_block_t kDtClkmgrRegBlockPrimary = kDtClkmgrRegBlockCore;
 
/**
 * List of memories.
 *
 * Memories are guaranteed to start at 0 and to be consecutively numbered.
 */
typedef enum dt_clkmgr_memory {
  kDtClkmgrMemoryCount = 0, /**< \internal Number of memories */
} dt_clkmgr_memory_t;
 
/**
 * List of Alerts.
 *
 * Alerts are guaranteed to be numbered consecutively from 0.
 */
typedef enum dt_clkmgr_alert {
  kDtClkmgrAlertRecovFault = 0, /**< This recoverable alert is triggered when there are measurement errors. */
  kDtClkmgrAlertFatalFault = 1, /**< This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected. */
  kDtClkmgrAlertCount = 2, /**< \internal Number of Alerts */
} dt_clkmgr_alert_t;
 
/**
 * List of clock ports.
 *
 * Clock ports are guaranteed to be numbered consecutively from 0.
 */
typedef enum dt_clkmgr_clock {
  kDtClkmgrClockClk = 0, /**< Clock port clk_i */
  kDtClkmgrClockMain = 1, /**< Clock port clk_main_i */
  kDtClkmgrClockIo = 2, /**< Clock port clk_io_i */
  kDtClkmgrClockUsb = 3, /**< Clock port clk_usb_i */
  kDtClkmgrClockAon = 4, /**< Clock port clk_aon_i */
  kDtClkmgrClockCount = 5, /**< \internal Number of clock ports */
} dt_clkmgr_clock_t;
 
/**
 * List of reset ports.
 *
 * Reset ports are guaranteed to be numbered consecutively from 0.
 */
typedef enum dt_clkmgr_reset {
  kDtClkmgrResetRst = 0, /**< Reset port rst_ni */
  kDtClkmgrResetRoot = 1, /**< Reset port rst_root_ni */
  kDtClkmgrResetMain = 2, /**< Reset port rst_main_ni */
  kDtClkmgrResetIo = 3, /**< Reset port rst_io_ni */
  kDtClkmgrResetUsb = 4, /**< Reset port rst_usb_ni */
  kDtClkmgrResetAon = 5, /**< Reset port rst_aon_ni */
  kDtClkmgrResetIoDiv2 = 6, /**< Reset port rst_io_div2_ni */
  kDtClkmgrResetIoDiv4 = 7, /**< Reset port rst_io_div4_ni */
  kDtClkmgrResetRootMain = 8, /**< Reset port rst_root_main_ni */
  kDtClkmgrResetRootIo = 9, /**< Reset port rst_root_io_ni */
  kDtClkmgrResetRootIoDiv2 = 10, /**< Reset port rst_root_io_div2_ni */
  kDtClkmgrResetRootIoDiv4 = 11, /**< Reset port rst_root_io_div4_ni */
  kDtClkmgrResetRootUsb = 12, /**< Reset port rst_root_usb_ni */
  kDtClkmgrResetCount = 13, /**< \internal Number of reset ports */
} dt_clkmgr_reset_t;
 
/**
 * List of supported hardware features.
 */
#define OPENTITAN_CLKMGR_HAS_ENABLE_IO_DIV4 1
#define OPENTITAN_CLKMGR_HAS_ENABLE_IO_DIV2 1
#define OPENTITAN_CLKMGR_HAS_ENABLE_IO 1
#define OPENTITAN_CLKMGR_HAS_ENABLE_USB 1
#define OPENTITAN_CLKMGR_HAS_HINT_AES 1
#define OPENTITAN_CLKMGR_HAS_HINT_HMAC 1
#define OPENTITAN_CLKMGR_HAS_HINT_KMAC 1
#define OPENTITAN_CLKMGR_HAS_HINT_OTBN 1
#define OPENTITAN_CLKMGR_HAS_MEAS_CTRL_REGWEN 1
#define OPENTITAN_CLKMGR_HAS_MEAS_CTRL_IO 1
#define OPENTITAN_CLKMGR_HAS_MEAS_CTRL_IO_DIV2 1
#define OPENTITAN_CLKMGR_HAS_MEAS_CTRL_IO_DIV4 1
#define OPENTITAN_CLKMGR_HAS_MEAS_CTRL_MAIN 1
#define OPENTITAN_CLKMGR_HAS_MEAS_CTRL_USB 1
#define OPENTITAN_CLKMGR_HAS_MEAS_CTRL_RECOV_ERR 1
#define OPENTITAN_CLKMGR_HAS_LC_EXTCLK_SPEED 1
#define OPENTITAN_CLKMGR_HAS_SW_EXTCLK_REGWEN 1
#define OPENTITAN_CLKMGR_HAS_SW_EXTCLK_HIGH_SPEED 1
#define OPENTITAN_CLKMGR_HAS_SW_EXTCLK_LOW_SPEED 1
#define OPENTITAN_CLKMGR_HAS_JITTER_REGWEN 1
#define OPENTITAN_CLKMGR_HAS_JITTER_ENABLE 1
#define OPENTITAN_CLKMGR_HAS_ALERT_HANDLER_CLOCK_STATUS 1
 
 
 
/**
 * Get the clkmgr instance from an instance ID
 *
 * For example, `dt_uart_from_instance_id(kDtInstanceIdUart3) == kDtUart3`.
 *
 * @param inst_id Instance ID.
 * @return A clkmgr instance.
 *
 * **Note:** This function only makes sense if the instance ID has device type clkmgr,
 * otherwise the returned value is unspecified.
 */
dt_clkmgr_t dt_clkmgr_from_instance_id(dt_instance_id_t inst_id);
 
/**
 * Get the instance ID of an instance.
 *
 * @param dt Instance of clkmgr.
 * @return The instance ID of that instance.
 */
dt_instance_id_t dt_clkmgr_instance_id(dt_clkmgr_t dt);
 
/**
 * Get the register base address of an instance.
 *
 * @param dt Instance of clkmgr.
 * @param reg_block The register block requested.
 * @return The register base address of the requested block.
 */
uint32_t dt_clkmgr_reg_block(
    dt_clkmgr_t dt,
    dt_clkmgr_reg_block_t reg_block);
 
/**
 * Get the primary register base address of an instance.
 *
 * This is just a convenience function, equivalent to
 * `dt_clkmgr_reg_block(dt, kDtClkmgrRegBlockCore)`
 *
 * @param dt Instance of clkmgr.
 * @return The register base address of the primary register block.
 */
static inline uint32_t dt_clkmgr_primary_reg_block(
    dt_clkmgr_t dt) {
  return dt_clkmgr_reg_block(dt, kDtClkmgrRegBlockCore);
}
 
/**
 * Get the base address of a memory.
 *
 * @param dt Instance of clkmgr.
 * @param mem The memory requested.
 * @return The base address of the requested memory.
 */
uint32_t dt_clkmgr_memory_base(
    dt_clkmgr_t dt,
    dt_clkmgr_memory_t mem);
 
/**
 * Get the size of a memory.
 *
 * @param dt Instance of clkmgr.
 * @param mem The memory requested.
 * @return The size of the requested memory.
 */
uint32_t dt_clkmgr_memory_size(
    dt_clkmgr_t dt,
    dt_clkmgr_memory_t mem);
 
 
/**
 * Get the alert ID of a clkmgr alert for a given instance.
 *
 * **Note:** This function only makes sense if the instance is connected to the Alert Handler. For any
 * instances where the instance is not connected, the return value is unspecified.
 *
 * @param dt Instance of clkmgr.
 * @param alert A clkmgr alert.
 * @return The Alert Handler alert ID of the alert of this instance.
 */
dt_alert_id_t dt_clkmgr_alert_to_alert_id(
    dt_clkmgr_t dt,
    dt_clkmgr_alert_t alert);
 
/**
 * Convert a global alert ID to a local clkmgr alert type.
 *
 * @param dt Instance of clkmgr.
 * @param alert A global alert ID that belongs to this instance.
 * @return The clkmgr alert, or `kDtClkmgrAlertCount`.
 *
 * **Note:** This function assumes that the global alert ID belongs to the
 * instance of clkmgr passed in parameter. In other words, it must be the case
 * that `dt_clkmgr_instance_id(dt) == dt_alert_id_to_instance_id(alert)`. Otherwise,
 * this function will return `kDtClkmgrAlertCount`.
 */
dt_clkmgr_alert_t dt_clkmgr_alert_from_alert_id(
    dt_clkmgr_t dt,
    dt_alert_id_t alert);
 
 
 
/**
 * Get the clock signal connected to a clock port of an instance.
 *
 * @param dt Instance of clkmgr.
 * @param clk Clock port.
 * @return Clock signal.
 */
dt_clock_t dt_clkmgr_clock(
    dt_clkmgr_t dt,
    dt_clkmgr_clock_t clk);
 
/**
 * Get the reset signal connected to a reset port of an instance.
 *
 * @param dt Instance of clkmgr.
 * @param rst Reset port.
 * @return Reset signal.
 */
dt_reset_t dt_clkmgr_reset(
    dt_clkmgr_t dt,
    dt_clkmgr_reset_t rst);
 
 
 
/**
 * Get the number of software gateable clocks.
 *
 * @param dt Instance of clkmgr.
 * @return Number of gateable clocks.
 */
size_t dt_clkmgr_gateable_clock_count(dt_clkmgr_t dt);
 
/**
 * Get the instance ID of a gateable clock.
 *
 * The clocks are ordered as they appear in the registers.
 *
 * @param dt Instance of clkmgr.
 * @param idx Index of the gateable clock, between 0 and `dt_clkmgr_sw_clock_count(dt)-1`.
 * @return Instance ID of the device whose clock is gateable.
 */
dt_instance_id_t dt_clkmgr_gateable_clock(dt_clkmgr_t dt, size_t idx);
 
/**
 * Get the number of software hintable clocks.
 *
 * @param dt Instance of clkmgr.
 * @return Number of hintable clocks.
 */
size_t dt_clkmgr_hintable_clock_count(dt_clkmgr_t dt);
 
/**
 * Get the instance ID of a hintable clock.
 *
 * The clocks sources are ordered as they appear in the registers.
 *
 * @param dt Instance of clkmgr.
 * @param idx Index of the hintable clock, between 0 and `dt_clkmgr_hint_clock_count(dt)-1`.
 * @return Instance ID of the device whose clock is hintable.
 */
dt_instance_id_t dt_clkmgr_hintable_clock(dt_clkmgr_t dt, size_t idx);
 
/**
 * Description of a measurable clock.
 *
 */
typedef struct dt_clkmgr_measurable_clk {
  dt_clock_t clock; /**< Clock */
  uint32_t meas_ctrl_en_off; /**< MEAS_CTRL_EN register offset */
  bitfield_field32_t meas_ctrl_en_en_field; /**< MEAS_CTRL_EN_EN bitfield */
  uint32_t meas_ctrl_shadowed_off; /**< CTRL_SHADOWED register offset */
  bitfield_field32_t meas_ctrl_shadowed_lo_field; /**< CTRL_SHADOWED_LO bitfield */
  bitfield_field32_t meas_ctrl_shadowed_hi_field; /**< CTRL_SHADOWED_HI bitfield */
} dt_clkmgr_measurable_clk_t;
 
 
/**
 * Get the number of measurable clocks.
 *
 * @param dt Instance of clkmgr.
 * @return Number of measurable clocks.
 */
size_t dt_clkmgr_measurable_clock_count(dt_clkmgr_t dt);
 
/**
 * Get the description of a measurable clock.
 *
 * @param dt Instance of clkmgr.
 * @param idx Index of the measurable clock, between 0 and
 *            `dt_clkmgr_measurable_clock_count(dt)-1`.
 * @return Description of the measurable clock.
 */
dt_clkmgr_measurable_clk_t dt_clkmgr_measurable_clock(dt_clkmgr_t dt, size_t idx);
 
 
 
#ifdef __cplusplus
}  // extern "C"
#endif  // __cplusplus
 
#endif  // OPENTITAN_DT_CLKMGR_H_