Software APIs
dt_clkmgr.h
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1// Copyright lowRISC contributors (OpenTitan project).
2// Licensed under the Apache License, Version 2.0, see LICENSE for details.
3// SPDX-License-Identifier: Apache-2.0
4//
5// Device table API auto-generated by `dtgen`
6
7#ifndef OPENTITAN_DT_CLKMGR_H_
8#define OPENTITAN_DT_CLKMGR_H_
9
10#ifdef __cplusplus
11extern "C" {
12#endif // __cplusplus
13
14/**
15 * @file
16 * @brief Device Tables (DT) for IP clkmgr and top earlgrey.
17 *
18 * This file contains the type definitions and global functions of the clkmgr.
19 */
20
21#include "dt_api.h"
22#include <stdint.h>
23
24
26
27
28/**
29 * List of instances.
30 */
31typedef enum dt_clkmgr {
32 kDtClkmgrAon = 0, /**< clkmgr_aon */
33 kDtClkmgrFirst = 0, /**< \internal First instance */
34 kDtClkmgrCount = 1, /**< \internal Number of instances */
36
37/**
38 * List of register blocks.
39 *
40 * Register blocks are guaranteed to start at 0 and to be consecutively numbered.
41 */
42typedef enum dt_clkmgr_reg_block {
43 kDtClkmgrRegBlockCore = 0, /**< */
44 kDtClkmgrRegBlockCount = 1, /**< \internal Number of register blocks */
46
47/** Primary register block (associated with the "primary" set of registers that control the IP). */
48static const dt_clkmgr_reg_block_t kDtClkmgrRegBlockPrimary = kDtClkmgrRegBlockCore;
49
50/**
51 * List of Alerts.
52 *
53 * Alerts are guaranteed to be numbered consecutively from 0.
54 */
55typedef enum dt_clkmgr_alert {
56 kDtClkmgrAlertRecovFault = 0, /**< This recoverable alert is triggered when there are measurement errors. */
57 kDtClkmgrAlertFatalFault = 1, /**< This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected. */
58 kDtClkmgrAlertCount = 2, /**< \internal Number of Alerts */
60
61/**
62 * List of clock ports.
63 *
64 * Clock ports are guaranteed to be numbered consecutively from 0.
65 */
66typedef enum dt_clkmgr_clock {
67 kDtClkmgrClockClk = 0, /**< Clock port clk_i */
68 kDtClkmgrClockMain = 1, /**< Clock port clk_main_i */
69 kDtClkmgrClockIo = 2, /**< Clock port clk_io_i */
70 kDtClkmgrClockUsb = 3, /**< Clock port clk_usb_i */
71 kDtClkmgrClockAon = 4, /**< Clock port clk_aon_i */
72 kDtClkmgrClockCount = 5, /**< \internal Number of clock ports */
74
75/**
76 * List of reset ports.
77 *
78 * Reset ports are guaranteed to be numbered consecutively from 0.
79 */
80typedef enum dt_clkmgr_reset {
81 kDtClkmgrResetRst = 0, /**< Reset port rst_ni */
82 kDtClkmgrResetRoot = 1, /**< Reset port rst_root_ni */
83 kDtClkmgrResetMain = 2, /**< Reset port rst_main_ni */
84 kDtClkmgrResetIo = 3, /**< Reset port rst_io_ni */
85 kDtClkmgrResetUsb = 4, /**< Reset port rst_usb_ni */
86 kDtClkmgrResetAon = 5, /**< Reset port rst_aon_ni */
87 kDtClkmgrResetIoDiv2 = 6, /**< Reset port rst_io_div2_ni */
88 kDtClkmgrResetIoDiv4 = 7, /**< Reset port rst_io_div4_ni */
89 kDtClkmgrResetRootMain = 8, /**< Reset port rst_root_main_ni */
90 kDtClkmgrResetRootIo = 9, /**< Reset port rst_root_io_ni */
91 kDtClkmgrResetRootIoDiv2 = 10, /**< Reset port rst_root_io_div2_ni */
92 kDtClkmgrResetRootIoDiv4 = 11, /**< Reset port rst_root_io_div4_ni */
93 kDtClkmgrResetRootUsb = 12, /**< Reset port rst_root_usb_ni */
94 kDtClkmgrResetCount = 13, /**< \internal Number of reset ports */
96
97/**
98 * List of supported hardware features.
99 */
100#define OPENTITAN_CLKMGR_HAS_ENABLE_IO_DIV4 1
101#define OPENTITAN_CLKMGR_HAS_ENABLE_IO_DIV2 1
102#define OPENTITAN_CLKMGR_HAS_ENABLE_IO 1
103#define OPENTITAN_CLKMGR_HAS_ENABLE_USB 1
104#define OPENTITAN_CLKMGR_HAS_HINT_AES 1
105#define OPENTITAN_CLKMGR_HAS_HINT_HMAC 1
106#define OPENTITAN_CLKMGR_HAS_HINT_KMAC 1
107#define OPENTITAN_CLKMGR_HAS_HINT_OTBN 1
108#define OPENTITAN_CLKMGR_HAS_MEAS_CTRL_REGWEN 1
109#define OPENTITAN_CLKMGR_HAS_MEAS_CTRL_IO 1
110#define OPENTITAN_CLKMGR_HAS_MEAS_CTRL_IO_DIV2 1
111#define OPENTITAN_CLKMGR_HAS_MEAS_CTRL_IO_DIV4 1
112#define OPENTITAN_CLKMGR_HAS_MEAS_CTRL_MAIN 1
113#define OPENTITAN_CLKMGR_HAS_MEAS_CTRL_USB 1
114#define OPENTITAN_CLKMGR_HAS_MEAS_CTRL_RECOV_ERR 1
115#define OPENTITAN_CLKMGR_HAS_LC_EXTCLK_SPEED 1
116#define OPENTITAN_CLKMGR_HAS_SW_EXTCLK_REGWEN 1
117#define OPENTITAN_CLKMGR_HAS_SW_EXTCLK_HIGH_SPEED 1
118#define OPENTITAN_CLKMGR_HAS_SW_EXTCLK_LOW_SPEED 1
119#define OPENTITAN_CLKMGR_HAS_JITTER_REGWEN 1
120#define OPENTITAN_CLKMGR_HAS_JITTER_ENABLE 1
121#define OPENTITAN_CLKMGR_HAS_ALERT_HANDLER_CLOCK_STATUS 1
122
123
124
125/**
126 * Get the clkmgr instance from an instance ID
127 *
128 * For example, `dt_uart_from_instance_id(kDtInstanceIdUart3) == kDtUart3`.
129 *
130 * @param inst_id Instance ID.
131 * @return A clkmgr instance.
132 *
133 * **Note:** This function only makes sense if the instance ID has device type clkmgr,
134 * otherwise the returned value is unspecified.
135 */
137
138/**
139 * Get the instance ID of an instance.
140 *
141 * @param dt Instance of clkmgr.
142 * @return The instance ID of that instance.
143 */
145
146/**
147 * Get the register base address of an instance.
148 *
149 * @param dt Instance of clkmgr.
150 * @param reg_block The register block requested.
151 * @return The register base address of the requested block.
152 */
153uint32_t dt_clkmgr_reg_block(
154 dt_clkmgr_t dt,
155 dt_clkmgr_reg_block_t reg_block);
156
157/**
158 * Get the primary register base address of an instance.
159 *
160 * This is just a convenience function, equivalent to
161 * `dt_clkmgr_reg_block(dt, kDtClkmgrRegBlockCore)`
162 *
163 * @param dt Instance of clkmgr.
164 * @return The register base address of the primary register block.
165 */
166static inline uint32_t dt_clkmgr_primary_reg_block(
167 dt_clkmgr_t dt) {
168 return dt_clkmgr_reg_block(dt, kDtClkmgrRegBlockCore);
169}
170
171
172/**
173 * Get the alert ID of a clkmgr alert for a given instance.
174 *
175 * **Note:** This function only makes sense if the instance is connected to the Alert Handler. For any
176 * instances where the instance is not connected, the return value is unspecified.
177 *
178 * @param dt Instance of clkmgr.
179 * @param alert A clkmgr alert.
180 * @return The Alert Handler alert ID of the alert of this instance.
181 */
183 dt_clkmgr_t dt,
184 dt_clkmgr_alert_t alert);
185
186/**
187 * Convert a global alert ID to a local clkmgr alert type.
188 *
189 * @param dt Instance of clkmgr.
190 * @param alert A global alert ID that belongs to this instance.
191 * @return The clkmgr alert, or `kDtClkmgrAlertCount`.
192 *
193 * **Note:** This function assumes that the global alert ID belongs to the
194 * instance of clkmgr passed in parameter. In other words, it must be the case
195 * that `dt_clkmgr_instance_id(dt) == dt_alert_id_to_instance_id(alert)`. Otherwise,
196 * this function will return `kDtClkmgrAlertCount`.
197 */
199 dt_clkmgr_t dt,
200 dt_alert_id_t alert);
201
202
203
204/**
205 * Get the clock signal connected to a clock port of an instance.
206 *
207 * @param dt Instance of clkmgr.
208 * @param clk Clock port.
209 * @return Clock signal.
210 */
212 dt_clkmgr_t dt,
214
215/**
216 * Get the reset signal connected to a reset port of an instance.
217 *
218 * @param dt Instance of clkmgr.
219 * @param rst Reset port.
220 * @return Reset signal.
221 */
223 dt_clkmgr_t dt,
225
226
227
228/**
229 * Get the number of software gateable clocks.
230 *
231 * @param dt Instance of clkmgr.
232 * @return Number of gateable clocks.
233 */
235
236/**
237 * Get the instance ID of a gateable clock.
238 *
239 * The clocks are ordered as they appear in the registers.
240 *
241 * @param dt Instance of clkmgr.
242 * @param idx Index of the gateable clock, between 0 and `dt_clkmgr_sw_clock_count(dt)-1`.
243 * @return Instance ID of the device whose clock is gateable.
244 */
246
247/**
248 * Get the number of software hintable clocks.
249 *
250 * @param dt Instance of clkmgr.
251 * @return Number of hintable clocks.
252 */
254
255/**
256 * Get the instance ID of a hintable clock.
257 *
258 * The clocks sources are ordered as they appear in the registers.
259 *
260 * @param dt Instance of clkmgr.
261 * @param idx Index of the hintable clock, between 0 and `dt_clkmgr_hint_clock_count(dt)-1`.
262 * @return Instance ID of the device whose clock is hintable.
263 */
265
266/**
267 * Description of a measurable clock.
268 *
269 */
271 dt_clock_t clock; /**< Clock */
272 uint32_t meas_ctrl_en_off; /**< MEAS_CTRL_EN register offset */
273 bitfield_field32_t meas_ctrl_en_en_field; /**< MEAS_CTRL_EN_EN bitfield */
274 uint32_t meas_ctrl_shadowed_off; /**< CTRL_SHADOWED register offset */
275 bitfield_field32_t meas_ctrl_shadowed_lo_field; /**< CTRL_SHADOWED_LO bitfield */
276 bitfield_field32_t meas_ctrl_shadowed_hi_field; /**< CTRL_SHADOWED_HI bitfield */
278
279
280/**
281 * Get the number of measurable clocks.
282 *
283 * @param dt Instance of clkmgr.
284 * @return Number of measurable clocks.
285 */
287
288/**
289 * Get the description of a measurable clock.
290 *
291 * @param dt Instance of clkmgr.
292 * @param idx Index of the measurable clock, between 0 and
293 * `dt_clkmgr_measurable_clock_count(dt)-1`.
294 * @return Description of the measurable clock.
295 */
297
298
299
300#ifdef __cplusplus
301} // extern "C"
302#endif // __cplusplus
303
304#endif // OPENTITAN_DT_CLKMGR_H_