csrng_regs.h

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/**
 * @file
 * @brief Generated register defines for csrng
 */
 
// Copyright information found in source file:
// Copyright lowRISC contributors (OpenTitan project).
 
// Licensing information found in source file:
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
 
#ifndef _CSRNG_REG_DEFS_
#define _CSRNG_REG_DEFS_
 
#ifdef __cplusplus
extern "C" {
#endif
// Number of application interfaces
#define CSRNG_PARAM_NUM_APPS 3
 
// Number of alerts
#define CSRNG_PARAM_NUM_ALERTS 2
 
// Register width
#define CSRNG_PARAM_REG_WIDTH 32
 
// Common Interrupt Offsets
#define CSRNG_INTR_COMMON_CS_CMD_REQ_DONE_BIT 0
#define CSRNG_INTR_COMMON_CS_ENTROPY_REQ_BIT 1
#define CSRNG_INTR_COMMON_CS_HW_INST_EXC_BIT 2
#define CSRNG_INTR_COMMON_CS_FATAL_ERR_BIT 3
 
// Interrupt State Register
#define CSRNG_INTR_STATE_REG_OFFSET 0x0
#define CSRNG_INTR_STATE_REG_RESVAL 0x0u
#define CSRNG_INTR_STATE_CS_CMD_REQ_DONE_BIT 0
#define CSRNG_INTR_STATE_CS_ENTROPY_REQ_BIT 1
#define CSRNG_INTR_STATE_CS_HW_INST_EXC_BIT 2
#define CSRNG_INTR_STATE_CS_FATAL_ERR_BIT 3
 
// Interrupt Enable Register
#define CSRNG_INTR_ENABLE_REG_OFFSET 0x4
#define CSRNG_INTR_ENABLE_REG_RESVAL 0x0u
#define CSRNG_INTR_ENABLE_CS_CMD_REQ_DONE_BIT 0
#define CSRNG_INTR_ENABLE_CS_ENTROPY_REQ_BIT 1
#define CSRNG_INTR_ENABLE_CS_HW_INST_EXC_BIT 2
#define CSRNG_INTR_ENABLE_CS_FATAL_ERR_BIT 3
 
// Interrupt Test Register
#define CSRNG_INTR_TEST_REG_OFFSET 0x8
#define CSRNG_INTR_TEST_REG_RESVAL 0x0u
#define CSRNG_INTR_TEST_CS_CMD_REQ_DONE_BIT 0
#define CSRNG_INTR_TEST_CS_ENTROPY_REQ_BIT 1
#define CSRNG_INTR_TEST_CS_HW_INST_EXC_BIT 2
#define CSRNG_INTR_TEST_CS_FATAL_ERR_BIT 3
 
// Alert Test Register
#define CSRNG_ALERT_TEST_REG_OFFSET 0xc
#define CSRNG_ALERT_TEST_REG_RESVAL 0x0u
#define CSRNG_ALERT_TEST_RECOV_ALERT_BIT 0
#define CSRNG_ALERT_TEST_FATAL_ALERT_BIT 1
 
// Register write enable for all control registers
#define CSRNG_REGWEN_REG_OFFSET 0x10
#define CSRNG_REGWEN_REG_RESVAL 0x1u
#define CSRNG_REGWEN_REGWEN_BIT 0
 
// Control register
#define CSRNG_CTRL_REG_OFFSET 0x14
#define CSRNG_CTRL_REG_RESVAL 0x9999u
#define CSRNG_CTRL_ENABLE_MASK 0xfu
#define CSRNG_CTRL_ENABLE_OFFSET 0
#define CSRNG_CTRL_ENABLE_FIELD \
  ((bitfield_field32_t) { .mask = CSRNG_CTRL_ENABLE_MASK, .index = CSRNG_CTRL_ENABLE_OFFSET })
#define CSRNG_CTRL_SW_APP_ENABLE_MASK 0xfu
#define CSRNG_CTRL_SW_APP_ENABLE_OFFSET 4
#define CSRNG_CTRL_SW_APP_ENABLE_FIELD \
  ((bitfield_field32_t) { .mask = CSRNG_CTRL_SW_APP_ENABLE_MASK, .index = CSRNG_CTRL_SW_APP_ENABLE_OFFSET })
#define CSRNG_CTRL_READ_INT_STATE_MASK 0xfu
#define CSRNG_CTRL_READ_INT_STATE_OFFSET 8
#define CSRNG_CTRL_READ_INT_STATE_FIELD \
  ((bitfield_field32_t) { .mask = CSRNG_CTRL_READ_INT_STATE_MASK, .index = CSRNG_CTRL_READ_INT_STATE_OFFSET })
#define CSRNG_CTRL_FIPS_FORCE_ENABLE_MASK 0xfu
#define CSRNG_CTRL_FIPS_FORCE_ENABLE_OFFSET 12
#define CSRNG_CTRL_FIPS_FORCE_ENABLE_FIELD \
  ((bitfield_field32_t) { .mask = CSRNG_CTRL_FIPS_FORCE_ENABLE_MASK, .index = CSRNG_CTRL_FIPS_FORCE_ENABLE_OFFSET })
 
// Command request register
#define CSRNG_CMD_REQ_REG_OFFSET 0x18
#define CSRNG_CMD_REQ_REG_RESVAL 0x0u
 
// CSRNG maximum number of generate requests allowed between reseeds register
#define CSRNG_RESEED_INTERVAL_REG_OFFSET 0x1c
#define CSRNG_RESEED_INTERVAL_REG_RESVAL 0xffffffffu
 
// Reseed counter.
#define CSRNG_RESEED_COUNTER_RESEED_COUNTER_FIELD_WIDTH 32
#define CSRNG_RESEED_COUNTER_MULTIREG_COUNT 3
 
// Reseed counter.
#define CSRNG_RESEED_COUNTER_0_REG_OFFSET 0x20
#define CSRNG_RESEED_COUNTER_0_REG_RESVAL 0x0u
 
// Reseed counter.
#define CSRNG_RESEED_COUNTER_1_REG_OFFSET 0x24
#define CSRNG_RESEED_COUNTER_1_REG_RESVAL 0x0u
 
// Reseed counter.
#define CSRNG_RESEED_COUNTER_2_REG_OFFSET 0x28
#define CSRNG_RESEED_COUNTER_2_REG_RESVAL 0x0u
 
// Application interface command status register
#define CSRNG_SW_CMD_STS_REG_OFFSET 0x2c
#define CSRNG_SW_CMD_STS_REG_RESVAL 0x0u
#define CSRNG_SW_CMD_STS_CMD_RDY_BIT 1
#define CSRNG_SW_CMD_STS_CMD_ACK_BIT 2
#define CSRNG_SW_CMD_STS_CMD_STS_MASK 0x7u
#define CSRNG_SW_CMD_STS_CMD_STS_OFFSET 3
#define CSRNG_SW_CMD_STS_CMD_STS_FIELD \
  ((bitfield_field32_t) { .mask = CSRNG_SW_CMD_STS_CMD_STS_MASK, .index = CSRNG_SW_CMD_STS_CMD_STS_OFFSET })
#define CSRNG_SW_CMD_STS_CMD_STS_VALUE_SUCCESS 0x0
#define CSRNG_SW_CMD_STS_CMD_STS_VALUE_INVALID_ACMD 0x1
#define CSRNG_SW_CMD_STS_CMD_STS_VALUE_INVALID_GEN_CMD 0x2
#define CSRNG_SW_CMD_STS_CMD_STS_VALUE_INVALID_CMD_SEQ 0x3
#define CSRNG_SW_CMD_STS_CMD_STS_VALUE_RESEED_CNT_EXCEEDED 0x4
 
// Generate bits returned valid register
#define CSRNG_GENBITS_VLD_REG_OFFSET 0x30
#define CSRNG_GENBITS_VLD_REG_RESVAL 0x0u
#define CSRNG_GENBITS_VLD_GENBITS_VLD_BIT 0
#define CSRNG_GENBITS_VLD_GENBITS_FIPS_BIT 1
 
// Generate bits returned register
#define CSRNG_GENBITS_REG_OFFSET 0x34
#define CSRNG_GENBITS_REG_RESVAL 0x0u
 
// Internal state read enable register
#define CSRNG_INT_STATE_READ_ENABLE_REG_OFFSET 0x38
#define CSRNG_INT_STATE_READ_ENABLE_REG_RESVAL 0x7u
#define CSRNG_INT_STATE_READ_ENABLE_INT_STATE_READ_ENABLE_MASK 0x7u
#define CSRNG_INT_STATE_READ_ENABLE_INT_STATE_READ_ENABLE_OFFSET 0
#define CSRNG_INT_STATE_READ_ENABLE_INT_STATE_READ_ENABLE_FIELD \
  ((bitfield_field32_t) { .mask = CSRNG_INT_STATE_READ_ENABLE_INT_STATE_READ_ENABLE_MASK, .index = CSRNG_INT_STATE_READ_ENABLE_INT_STATE_READ_ENABLE_OFFSET })
 
// Internal state read enable REGWEN register
#define CSRNG_INT_STATE_READ_ENABLE_REGWEN_REG_OFFSET 0x3c
#define CSRNG_INT_STATE_READ_ENABLE_REGWEN_REG_RESVAL 0x1u
#define CSRNG_INT_STATE_READ_ENABLE_REGWEN_INT_STATE_READ_ENABLE_REGWEN_BIT 0
 
// Internal state number register
#define CSRNG_INT_STATE_NUM_REG_OFFSET 0x40
#define CSRNG_INT_STATE_NUM_REG_RESVAL 0x0u
#define CSRNG_INT_STATE_NUM_INT_STATE_NUM_MASK 0xfu
#define CSRNG_INT_STATE_NUM_INT_STATE_NUM_OFFSET 0
#define CSRNG_INT_STATE_NUM_INT_STATE_NUM_FIELD \
  ((bitfield_field32_t) { .mask = CSRNG_INT_STATE_NUM_INT_STATE_NUM_MASK, .index = CSRNG_INT_STATE_NUM_INT_STATE_NUM_OFFSET })
 
// Internal state read access register
#define CSRNG_INT_STATE_VAL_REG_OFFSET 0x44
#define CSRNG_INT_STATE_VAL_REG_RESVAL 0x0u
 
// FIPS/CC compliance flag forcing register
#define CSRNG_FIPS_FORCE_REG_OFFSET 0x48
#define CSRNG_FIPS_FORCE_REG_RESVAL 0x0u
#define CSRNG_FIPS_FORCE_FIPS_FORCE_MASK 0x7u
#define CSRNG_FIPS_FORCE_FIPS_FORCE_OFFSET 0
#define CSRNG_FIPS_FORCE_FIPS_FORCE_FIELD \
  ((bitfield_field32_t) { .mask = CSRNG_FIPS_FORCE_FIPS_FORCE_MASK, .index = CSRNG_FIPS_FORCE_FIPS_FORCE_OFFSET })
 
// Hardware instance exception status register
#define CSRNG_HW_EXC_STS_REG_OFFSET 0x4c
#define CSRNG_HW_EXC_STS_REG_RESVAL 0x0u
#define CSRNG_HW_EXC_STS_HW_EXC_STS_MASK 0xffffu
#define CSRNG_HW_EXC_STS_HW_EXC_STS_OFFSET 0
#define CSRNG_HW_EXC_STS_HW_EXC_STS_FIELD \
  ((bitfield_field32_t) { .mask = CSRNG_HW_EXC_STS_HW_EXC_STS_MASK, .index = CSRNG_HW_EXC_STS_HW_EXC_STS_OFFSET })
 
// Recoverable alert status register
#define CSRNG_RECOV_ALERT_STS_REG_OFFSET 0x50
#define CSRNG_RECOV_ALERT_STS_REG_RESVAL 0x0u
#define CSRNG_RECOV_ALERT_STS_ENABLE_FIELD_ALERT_BIT 0
#define CSRNG_RECOV_ALERT_STS_SW_APP_ENABLE_FIELD_ALERT_BIT 1
#define CSRNG_RECOV_ALERT_STS_READ_INT_STATE_FIELD_ALERT_BIT 2
#define CSRNG_RECOV_ALERT_STS_FIPS_FORCE_ENABLE_FIELD_ALERT_BIT 3
#define CSRNG_RECOV_ALERT_STS_ACMD_FLAG0_FIELD_ALERT_BIT 4
#define CSRNG_RECOV_ALERT_STS_CS_BUS_CMP_ALERT_BIT 12
#define CSRNG_RECOV_ALERT_STS_CMD_STAGE_INVALID_ACMD_ALERT_BIT 13
#define CSRNG_RECOV_ALERT_STS_CMD_STAGE_INVALID_CMD_SEQ_ALERT_BIT 14
#define CSRNG_RECOV_ALERT_STS_CMD_STAGE_RESEED_CNT_ALERT_BIT 15
 
// Hardware detection of error conditions status register
#define CSRNG_ERR_CODE_REG_OFFSET 0x54
#define CSRNG_ERR_CODE_REG_RESVAL 0x0u
#define CSRNG_ERR_CODE_SFIFO_CMD_ERR_BIT 0
#define CSRNG_ERR_CODE_SFIFO_GENBITS_ERR_BIT 1
#define CSRNG_ERR_CODE_SFIFO_CMDREQ_ERR_BIT 2
#define CSRNG_ERR_CODE_SFIFO_RCSTAGE_ERR_BIT 3
#define CSRNG_ERR_CODE_SFIFO_KEYVRC_ERR_BIT 4
#define CSRNG_ERR_CODE_SFIFO_UPDREQ_ERR_BIT 5
#define CSRNG_ERR_CODE_SFIFO_BENCREQ_ERR_BIT 6
#define CSRNG_ERR_CODE_SFIFO_BENCACK_ERR_BIT 7
#define CSRNG_ERR_CODE_SFIFO_PDATA_ERR_BIT 8
#define CSRNG_ERR_CODE_SFIFO_FINAL_ERR_BIT 9
#define CSRNG_ERR_CODE_SFIFO_GBENCACK_ERR_BIT 10
#define CSRNG_ERR_CODE_SFIFO_GRCSTAGE_ERR_BIT 11
#define CSRNG_ERR_CODE_SFIFO_GGENREQ_ERR_BIT 12
#define CSRNG_ERR_CODE_SFIFO_GADSTAGE_ERR_BIT 13
#define CSRNG_ERR_CODE_SFIFO_GGENBITS_ERR_BIT 14
#define CSRNG_ERR_CODE_SFIFO_BLKENC_ERR_BIT 15
#define CSRNG_ERR_CODE_CMD_STAGE_SM_ERR_BIT 20
#define CSRNG_ERR_CODE_MAIN_SM_ERR_BIT 21
#define CSRNG_ERR_CODE_DRBG_GEN_SM_ERR_BIT 22
#define CSRNG_ERR_CODE_DRBG_UPDBE_SM_ERR_BIT 23
#define CSRNG_ERR_CODE_DRBG_UPDOB_SM_ERR_BIT 24
#define CSRNG_ERR_CODE_AES_CIPHER_SM_ERR_BIT 25
#define CSRNG_ERR_CODE_CMD_GEN_CNT_ERR_BIT 26
#define CSRNG_ERR_CODE_FIFO_WRITE_ERR_BIT 28
#define CSRNG_ERR_CODE_FIFO_READ_ERR_BIT 29
#define CSRNG_ERR_CODE_FIFO_STATE_ERR_BIT 30
 
// Test error conditions register
#define CSRNG_ERR_CODE_TEST_REG_OFFSET 0x58
#define CSRNG_ERR_CODE_TEST_REG_RESVAL 0x0u
#define CSRNG_ERR_CODE_TEST_ERR_CODE_TEST_MASK 0x1fu
#define CSRNG_ERR_CODE_TEST_ERR_CODE_TEST_OFFSET 0
#define CSRNG_ERR_CODE_TEST_ERR_CODE_TEST_FIELD \
  ((bitfield_field32_t) { .mask = CSRNG_ERR_CODE_TEST_ERR_CODE_TEST_MASK, .index = CSRNG_ERR_CODE_TEST_ERR_CODE_TEST_OFFSET })
 
// Main state machine state debug register
#define CSRNG_MAIN_SM_STATE_REG_OFFSET 0x5c
#define CSRNG_MAIN_SM_STATE_REG_RESVAL 0x4eu
#define CSRNG_MAIN_SM_STATE_MAIN_SM_STATE_MASK 0xffu
#define CSRNG_MAIN_SM_STATE_MAIN_SM_STATE_OFFSET 0
#define CSRNG_MAIN_SM_STATE_MAIN_SM_STATE_FIELD \
  ((bitfield_field32_t) { .mask = CSRNG_MAIN_SM_STATE_MAIN_SM_STATE_MASK, .index = CSRNG_MAIN_SM_STATE_MAIN_SM_STATE_OFFSET })
 
#ifdef __cplusplus
}  // extern "C"
#endif
#endif  // _CSRNG_REG_DEFS_
// End generated register defines for csrng