alert_handler_regs.h

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/**
 * @file
 * @brief Generated register defines for alert_handler
 */
 
// Copyright information found in source file:
// Copyright lowRISC contributors (OpenTitan project).
 
// Licensing information found in source file:
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
 
#ifndef _ALERT_HANDLER_REG_DEFS_
#define _ALERT_HANDLER_REG_DEFS_
 
#ifdef __cplusplus
extern "C" {
#endif
// Number of alert channels.
#define ALERT_HANDLER_PARAM_N_ALERTS 66
 
// Number of LPGs.
#define ALERT_HANDLER_PARAM_N_LPG 24
 
// Width of LPG ID.
#define ALERT_HANDLER_PARAM_N_LPG_WIDTH 5
 
// Width of the escalation timer.
#define ALERT_HANDLER_PARAM_ESC_CNT_DW 32
 
// Width of the accumulation counter.
#define ALERT_HANDLER_PARAM_ACCU_CNT_DW 16
 
// Number of classes
#define ALERT_HANDLER_PARAM_N_CLASSES 4
 
// Number of escalation severities
#define ALERT_HANDLER_PARAM_N_ESC_SEV 4
 
// Number of escalation phases
#define ALERT_HANDLER_PARAM_N_PHASES 4
 
// Number of local alerts
#define ALERT_HANDLER_PARAM_N_LOC_ALERT 7
 
// Width of ping counter
#define ALERT_HANDLER_PARAM_PING_CNT_DW 16
 
// Width of phase ID
#define ALERT_HANDLER_PARAM_PHASE_DW 2
 
// Width of class ID
#define ALERT_HANDLER_PARAM_CLASS_DW 2
 
// Local alert ID for alert ping failure.
#define ALERT_HANDLER_PARAM_LOCAL_ALERT_ID_ALERT_PINGFAIL 0
 
// Local alert ID for escalation ping failure.
#define ALERT_HANDLER_PARAM_LOCAL_ALERT_ID_ESC_PINGFAIL 1
 
// Local alert ID for alert integrity failure.
#define ALERT_HANDLER_PARAM_LOCAL_ALERT_ID_ALERT_INTEGFAIL 2
 
// Local alert ID for escalation integrity failure.
#define ALERT_HANDLER_PARAM_LOCAL_ALERT_ID_ESC_INTEGFAIL 3
 
// Local alert ID for bus integrity failure.
#define ALERT_HANDLER_PARAM_LOCAL_ALERT_ID_BUS_INTEGFAIL 4
 
// Local alert ID for shadow register update error.
#define ALERT_HANDLER_PARAM_LOCAL_ALERT_ID_SHADOW_REG_UPDATE_ERROR 5
 
// Local alert ID for shadow register storage error.
#define ALERT_HANDLER_PARAM_LOCAL_ALERT_ID_SHADOW_REG_STORAGE_ERROR 6
 
// Last local alert ID.
#define ALERT_HANDLER_PARAM_LOCAL_ALERT_ID_LAST 6
 
// Register width
#define ALERT_HANDLER_PARAM_REG_WIDTH 32
 
// Common Interrupt Offsets
#define ALERT_HANDLER_INTR_COMMON_CLASSA_BIT 0
#define ALERT_HANDLER_INTR_COMMON_CLASSB_BIT 1
#define ALERT_HANDLER_INTR_COMMON_CLASSC_BIT 2
#define ALERT_HANDLER_INTR_COMMON_CLASSD_BIT 3
 
// Interrupt State Register
#define ALERT_HANDLER_INTR_STATE_REG_OFFSET 0x0
#define ALERT_HANDLER_INTR_STATE_REG_RESVAL 0x0u
#define ALERT_HANDLER_INTR_STATE_CLASSA_BIT 0
#define ALERT_HANDLER_INTR_STATE_CLASSB_BIT 1
#define ALERT_HANDLER_INTR_STATE_CLASSC_BIT 2
#define ALERT_HANDLER_INTR_STATE_CLASSD_BIT 3
 
// Interrupt Enable Register
#define ALERT_HANDLER_INTR_ENABLE_REG_OFFSET 0x4
#define ALERT_HANDLER_INTR_ENABLE_REG_RESVAL 0x0u
#define ALERT_HANDLER_INTR_ENABLE_CLASSA_BIT 0
#define ALERT_HANDLER_INTR_ENABLE_CLASSB_BIT 1
#define ALERT_HANDLER_INTR_ENABLE_CLASSC_BIT 2
#define ALERT_HANDLER_INTR_ENABLE_CLASSD_BIT 3
 
// Interrupt Test Register
#define ALERT_HANDLER_INTR_TEST_REG_OFFSET 0x8
#define ALERT_HANDLER_INTR_TEST_REG_RESVAL 0x0u
#define ALERT_HANDLER_INTR_TEST_CLASSA_BIT 0
#define ALERT_HANDLER_INTR_TEST_CLASSB_BIT 1
#define ALERT_HANDLER_INTR_TEST_CLASSC_BIT 2
#define ALERT_HANDLER_INTR_TEST_CLASSD_BIT 3
 
// Register write enable for !!PING_TIMEOUT_CYC_SHADOWED and
// !!PING_TIMER_EN_SHADOWED.
#define ALERT_HANDLER_PING_TIMER_REGWEN_REG_OFFSET 0xc
#define ALERT_HANDLER_PING_TIMER_REGWEN_REG_RESVAL 0x1u
#define ALERT_HANDLER_PING_TIMER_REGWEN_PING_TIMER_REGWEN_BIT 0
 
// Ping timeout cycle count.
#define ALERT_HANDLER_PING_TIMEOUT_CYC_SHADOWED_REG_OFFSET 0x10
#define ALERT_HANDLER_PING_TIMEOUT_CYC_SHADOWED_REG_RESVAL 0x100u
#define ALERT_HANDLER_PING_TIMEOUT_CYC_SHADOWED_PING_TIMEOUT_CYC_SHADOWED_MASK \
  0xffffu
#define ALERT_HANDLER_PING_TIMEOUT_CYC_SHADOWED_PING_TIMEOUT_CYC_SHADOWED_OFFSET \
  0
#define ALERT_HANDLER_PING_TIMEOUT_CYC_SHADOWED_PING_TIMEOUT_CYC_SHADOWED_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_PING_TIMEOUT_CYC_SHADOWED_PING_TIMEOUT_CYC_SHADOWED_MASK, .index = ALERT_HANDLER_PING_TIMEOUT_CYC_SHADOWED_PING_TIMEOUT_CYC_SHADOWED_OFFSET })
 
// Ping timer enable.
#define ALERT_HANDLER_PING_TIMER_EN_SHADOWED_REG_OFFSET 0x14
#define ALERT_HANDLER_PING_TIMER_EN_SHADOWED_REG_RESVAL 0x0u
#define ALERT_HANDLER_PING_TIMER_EN_SHADOWED_PING_TIMER_EN_SHADOWED_BIT 0
 
// Register write enable for alert enable bits. (common parameters)
#define ALERT_HANDLER_ALERT_REGWEN_EN_FIELD_WIDTH 1
#define ALERT_HANDLER_ALERT_REGWEN_MULTIREG_COUNT 66
 
// Register write enable for alert enable bits.
#define ALERT_HANDLER_ALERT_REGWEN_0_REG_OFFSET 0x18
#define ALERT_HANDLER_ALERT_REGWEN_0_REG_RESVAL 0x1u
#define ALERT_HANDLER_ALERT_REGWEN_0_EN_0_BIT 0
 
// Register write enable for alert enable bits.
#define ALERT_HANDLER_ALERT_REGWEN_1_REG_OFFSET 0x1c
#define ALERT_HANDLER_ALERT_REGWEN_1_REG_RESVAL 0x1u
#define ALERT_HANDLER_ALERT_REGWEN_1_EN_1_BIT 0
 
// Register write enable for alert enable bits.
#define ALERT_HANDLER_ALERT_REGWEN_2_REG_OFFSET 0x20
#define ALERT_HANDLER_ALERT_REGWEN_2_REG_RESVAL 0x1u
#define ALERT_HANDLER_ALERT_REGWEN_2_EN_2_BIT 0
 
// Register write enable for alert enable bits.
#define ALERT_HANDLER_ALERT_REGWEN_3_REG_OFFSET 0x24
#define ALERT_HANDLER_ALERT_REGWEN_3_REG_RESVAL 0x1u
#define ALERT_HANDLER_ALERT_REGWEN_3_EN_3_BIT 0
 
// Register write enable for alert enable bits.
#define ALERT_HANDLER_ALERT_REGWEN_4_REG_OFFSET 0x28
#define ALERT_HANDLER_ALERT_REGWEN_4_REG_RESVAL 0x1u
#define ALERT_HANDLER_ALERT_REGWEN_4_EN_4_BIT 0
 
// Register write enable for alert enable bits.
#define ALERT_HANDLER_ALERT_REGWEN_5_REG_OFFSET 0x2c
#define ALERT_HANDLER_ALERT_REGWEN_5_REG_RESVAL 0x1u
#define ALERT_HANDLER_ALERT_REGWEN_5_EN_5_BIT 0
 
// Register write enable for alert enable bits.
#define ALERT_HANDLER_ALERT_REGWEN_6_REG_OFFSET 0x30
#define ALERT_HANDLER_ALERT_REGWEN_6_REG_RESVAL 0x1u
#define ALERT_HANDLER_ALERT_REGWEN_6_EN_6_BIT 0
 
// Register write enable for alert enable bits.
#define ALERT_HANDLER_ALERT_REGWEN_7_REG_OFFSET 0x34
#define ALERT_HANDLER_ALERT_REGWEN_7_REG_RESVAL 0x1u
#define ALERT_HANDLER_ALERT_REGWEN_7_EN_7_BIT 0
 
// Register write enable for alert enable bits.
#define ALERT_HANDLER_ALERT_REGWEN_8_REG_OFFSET 0x38
#define ALERT_HANDLER_ALERT_REGWEN_8_REG_RESVAL 0x1u
#define ALERT_HANDLER_ALERT_REGWEN_8_EN_8_BIT 0
 
// Register write enable for alert enable bits.
#define ALERT_HANDLER_ALERT_REGWEN_9_REG_OFFSET 0x3c
#define ALERT_HANDLER_ALERT_REGWEN_9_REG_RESVAL 0x1u
#define ALERT_HANDLER_ALERT_REGWEN_9_EN_9_BIT 0
 
// Register write enable for alert enable bits.
#define ALERT_HANDLER_ALERT_REGWEN_10_REG_OFFSET 0x40
#define ALERT_HANDLER_ALERT_REGWEN_10_REG_RESVAL 0x1u
#define ALERT_HANDLER_ALERT_REGWEN_10_EN_10_BIT 0
 
// Register write enable for alert enable bits.
#define ALERT_HANDLER_ALERT_REGWEN_11_REG_OFFSET 0x44
#define ALERT_HANDLER_ALERT_REGWEN_11_REG_RESVAL 0x1u
#define ALERT_HANDLER_ALERT_REGWEN_11_EN_11_BIT 0
 
// Register write enable for alert enable bits.
#define ALERT_HANDLER_ALERT_REGWEN_12_REG_OFFSET 0x48
#define ALERT_HANDLER_ALERT_REGWEN_12_REG_RESVAL 0x1u
#define ALERT_HANDLER_ALERT_REGWEN_12_EN_12_BIT 0
 
// Register write enable for alert enable bits.
#define ALERT_HANDLER_ALERT_REGWEN_13_REG_OFFSET 0x4c
#define ALERT_HANDLER_ALERT_REGWEN_13_REG_RESVAL 0x1u
#define ALERT_HANDLER_ALERT_REGWEN_13_EN_13_BIT 0
 
// Register write enable for alert enable bits.
#define ALERT_HANDLER_ALERT_REGWEN_14_REG_OFFSET 0x50
#define ALERT_HANDLER_ALERT_REGWEN_14_REG_RESVAL 0x1u
#define ALERT_HANDLER_ALERT_REGWEN_14_EN_14_BIT 0
 
// Register write enable for alert enable bits.
#define ALERT_HANDLER_ALERT_REGWEN_15_REG_OFFSET 0x54
#define ALERT_HANDLER_ALERT_REGWEN_15_REG_RESVAL 0x1u
#define ALERT_HANDLER_ALERT_REGWEN_15_EN_15_BIT 0
 
// Register write enable for alert enable bits.
#define ALERT_HANDLER_ALERT_REGWEN_16_REG_OFFSET 0x58
#define ALERT_HANDLER_ALERT_REGWEN_16_REG_RESVAL 0x1u
#define ALERT_HANDLER_ALERT_REGWEN_16_EN_16_BIT 0
 
// Register write enable for alert enable bits.
#define ALERT_HANDLER_ALERT_REGWEN_17_REG_OFFSET 0x5c
#define ALERT_HANDLER_ALERT_REGWEN_17_REG_RESVAL 0x1u
#define ALERT_HANDLER_ALERT_REGWEN_17_EN_17_BIT 0
 
// Register write enable for alert enable bits.
#define ALERT_HANDLER_ALERT_REGWEN_18_REG_OFFSET 0x60
#define ALERT_HANDLER_ALERT_REGWEN_18_REG_RESVAL 0x1u
#define ALERT_HANDLER_ALERT_REGWEN_18_EN_18_BIT 0
 
// Register write enable for alert enable bits.
#define ALERT_HANDLER_ALERT_REGWEN_19_REG_OFFSET 0x64
#define ALERT_HANDLER_ALERT_REGWEN_19_REG_RESVAL 0x1u
#define ALERT_HANDLER_ALERT_REGWEN_19_EN_19_BIT 0
 
// Register write enable for alert enable bits.
#define ALERT_HANDLER_ALERT_REGWEN_20_REG_OFFSET 0x68
#define ALERT_HANDLER_ALERT_REGWEN_20_REG_RESVAL 0x1u
#define ALERT_HANDLER_ALERT_REGWEN_20_EN_20_BIT 0
 
// Register write enable for alert enable bits.
#define ALERT_HANDLER_ALERT_REGWEN_21_REG_OFFSET 0x6c
#define ALERT_HANDLER_ALERT_REGWEN_21_REG_RESVAL 0x1u
#define ALERT_HANDLER_ALERT_REGWEN_21_EN_21_BIT 0
 
// Register write enable for alert enable bits.
#define ALERT_HANDLER_ALERT_REGWEN_22_REG_OFFSET 0x70
#define ALERT_HANDLER_ALERT_REGWEN_22_REG_RESVAL 0x1u
#define ALERT_HANDLER_ALERT_REGWEN_22_EN_22_BIT 0
 
// Register write enable for alert enable bits.
#define ALERT_HANDLER_ALERT_REGWEN_23_REG_OFFSET 0x74
#define ALERT_HANDLER_ALERT_REGWEN_23_REG_RESVAL 0x1u
#define ALERT_HANDLER_ALERT_REGWEN_23_EN_23_BIT 0
 
// Register write enable for alert enable bits.
#define ALERT_HANDLER_ALERT_REGWEN_24_REG_OFFSET 0x78
#define ALERT_HANDLER_ALERT_REGWEN_24_REG_RESVAL 0x1u
#define ALERT_HANDLER_ALERT_REGWEN_24_EN_24_BIT 0
 
// Register write enable for alert enable bits.
#define ALERT_HANDLER_ALERT_REGWEN_25_REG_OFFSET 0x7c
#define ALERT_HANDLER_ALERT_REGWEN_25_REG_RESVAL 0x1u
#define ALERT_HANDLER_ALERT_REGWEN_25_EN_25_BIT 0
 
// Register write enable for alert enable bits.
#define ALERT_HANDLER_ALERT_REGWEN_26_REG_OFFSET 0x80
#define ALERT_HANDLER_ALERT_REGWEN_26_REG_RESVAL 0x1u
#define ALERT_HANDLER_ALERT_REGWEN_26_EN_26_BIT 0
 
// Register write enable for alert enable bits.
#define ALERT_HANDLER_ALERT_REGWEN_27_REG_OFFSET 0x84
#define ALERT_HANDLER_ALERT_REGWEN_27_REG_RESVAL 0x1u
#define ALERT_HANDLER_ALERT_REGWEN_27_EN_27_BIT 0
 
// Register write enable for alert enable bits.
#define ALERT_HANDLER_ALERT_REGWEN_28_REG_OFFSET 0x88
#define ALERT_HANDLER_ALERT_REGWEN_28_REG_RESVAL 0x1u
#define ALERT_HANDLER_ALERT_REGWEN_28_EN_28_BIT 0
 
// Register write enable for alert enable bits.
#define ALERT_HANDLER_ALERT_REGWEN_29_REG_OFFSET 0x8c
#define ALERT_HANDLER_ALERT_REGWEN_29_REG_RESVAL 0x1u
#define ALERT_HANDLER_ALERT_REGWEN_29_EN_29_BIT 0
 
// Register write enable for alert enable bits.
#define ALERT_HANDLER_ALERT_REGWEN_30_REG_OFFSET 0x90
#define ALERT_HANDLER_ALERT_REGWEN_30_REG_RESVAL 0x1u
#define ALERT_HANDLER_ALERT_REGWEN_30_EN_30_BIT 0
 
// Register write enable for alert enable bits.
#define ALERT_HANDLER_ALERT_REGWEN_31_REG_OFFSET 0x94
#define ALERT_HANDLER_ALERT_REGWEN_31_REG_RESVAL 0x1u
#define ALERT_HANDLER_ALERT_REGWEN_31_EN_31_BIT 0
 
// Register write enable for alert enable bits.
#define ALERT_HANDLER_ALERT_REGWEN_32_REG_OFFSET 0x98
#define ALERT_HANDLER_ALERT_REGWEN_32_REG_RESVAL 0x1u
#define ALERT_HANDLER_ALERT_REGWEN_32_EN_32_BIT 0
 
// Register write enable for alert enable bits.
#define ALERT_HANDLER_ALERT_REGWEN_33_REG_OFFSET 0x9c
#define ALERT_HANDLER_ALERT_REGWEN_33_REG_RESVAL 0x1u
#define ALERT_HANDLER_ALERT_REGWEN_33_EN_33_BIT 0
 
// Register write enable for alert enable bits.
#define ALERT_HANDLER_ALERT_REGWEN_34_REG_OFFSET 0xa0
#define ALERT_HANDLER_ALERT_REGWEN_34_REG_RESVAL 0x1u
#define ALERT_HANDLER_ALERT_REGWEN_34_EN_34_BIT 0
 
// Register write enable for alert enable bits.
#define ALERT_HANDLER_ALERT_REGWEN_35_REG_OFFSET 0xa4
#define ALERT_HANDLER_ALERT_REGWEN_35_REG_RESVAL 0x1u
#define ALERT_HANDLER_ALERT_REGWEN_35_EN_35_BIT 0
 
// Register write enable for alert enable bits.
#define ALERT_HANDLER_ALERT_REGWEN_36_REG_OFFSET 0xa8
#define ALERT_HANDLER_ALERT_REGWEN_36_REG_RESVAL 0x1u
#define ALERT_HANDLER_ALERT_REGWEN_36_EN_36_BIT 0
 
// Register write enable for alert enable bits.
#define ALERT_HANDLER_ALERT_REGWEN_37_REG_OFFSET 0xac
#define ALERT_HANDLER_ALERT_REGWEN_37_REG_RESVAL 0x1u
#define ALERT_HANDLER_ALERT_REGWEN_37_EN_37_BIT 0
 
// Register write enable for alert enable bits.
#define ALERT_HANDLER_ALERT_REGWEN_38_REG_OFFSET 0xb0
#define ALERT_HANDLER_ALERT_REGWEN_38_REG_RESVAL 0x1u
#define ALERT_HANDLER_ALERT_REGWEN_38_EN_38_BIT 0
 
// Register write enable for alert enable bits.
#define ALERT_HANDLER_ALERT_REGWEN_39_REG_OFFSET 0xb4
#define ALERT_HANDLER_ALERT_REGWEN_39_REG_RESVAL 0x1u
#define ALERT_HANDLER_ALERT_REGWEN_39_EN_39_BIT 0
 
// Register write enable for alert enable bits.
#define ALERT_HANDLER_ALERT_REGWEN_40_REG_OFFSET 0xb8
#define ALERT_HANDLER_ALERT_REGWEN_40_REG_RESVAL 0x1u
#define ALERT_HANDLER_ALERT_REGWEN_40_EN_40_BIT 0
 
// Register write enable for alert enable bits.
#define ALERT_HANDLER_ALERT_REGWEN_41_REG_OFFSET 0xbc
#define ALERT_HANDLER_ALERT_REGWEN_41_REG_RESVAL 0x1u
#define ALERT_HANDLER_ALERT_REGWEN_41_EN_41_BIT 0
 
// Register write enable for alert enable bits.
#define ALERT_HANDLER_ALERT_REGWEN_42_REG_OFFSET 0xc0
#define ALERT_HANDLER_ALERT_REGWEN_42_REG_RESVAL 0x1u
#define ALERT_HANDLER_ALERT_REGWEN_42_EN_42_BIT 0
 
// Register write enable for alert enable bits.
#define ALERT_HANDLER_ALERT_REGWEN_43_REG_OFFSET 0xc4
#define ALERT_HANDLER_ALERT_REGWEN_43_REG_RESVAL 0x1u
#define ALERT_HANDLER_ALERT_REGWEN_43_EN_43_BIT 0
 
// Register write enable for alert enable bits.
#define ALERT_HANDLER_ALERT_REGWEN_44_REG_OFFSET 0xc8
#define ALERT_HANDLER_ALERT_REGWEN_44_REG_RESVAL 0x1u
#define ALERT_HANDLER_ALERT_REGWEN_44_EN_44_BIT 0
 
// Register write enable for alert enable bits.
#define ALERT_HANDLER_ALERT_REGWEN_45_REG_OFFSET 0xcc
#define ALERT_HANDLER_ALERT_REGWEN_45_REG_RESVAL 0x1u
#define ALERT_HANDLER_ALERT_REGWEN_45_EN_45_BIT 0
 
// Register write enable for alert enable bits.
#define ALERT_HANDLER_ALERT_REGWEN_46_REG_OFFSET 0xd0
#define ALERT_HANDLER_ALERT_REGWEN_46_REG_RESVAL 0x1u
#define ALERT_HANDLER_ALERT_REGWEN_46_EN_46_BIT 0
 
// Register write enable for alert enable bits.
#define ALERT_HANDLER_ALERT_REGWEN_47_REG_OFFSET 0xd4
#define ALERT_HANDLER_ALERT_REGWEN_47_REG_RESVAL 0x1u
#define ALERT_HANDLER_ALERT_REGWEN_47_EN_47_BIT 0
 
// Register write enable for alert enable bits.
#define ALERT_HANDLER_ALERT_REGWEN_48_REG_OFFSET 0xd8
#define ALERT_HANDLER_ALERT_REGWEN_48_REG_RESVAL 0x1u
#define ALERT_HANDLER_ALERT_REGWEN_48_EN_48_BIT 0
 
// Register write enable for alert enable bits.
#define ALERT_HANDLER_ALERT_REGWEN_49_REG_OFFSET 0xdc
#define ALERT_HANDLER_ALERT_REGWEN_49_REG_RESVAL 0x1u
#define ALERT_HANDLER_ALERT_REGWEN_49_EN_49_BIT 0
 
// Register write enable for alert enable bits.
#define ALERT_HANDLER_ALERT_REGWEN_50_REG_OFFSET 0xe0
#define ALERT_HANDLER_ALERT_REGWEN_50_REG_RESVAL 0x1u
#define ALERT_HANDLER_ALERT_REGWEN_50_EN_50_BIT 0
 
// Register write enable for alert enable bits.
#define ALERT_HANDLER_ALERT_REGWEN_51_REG_OFFSET 0xe4
#define ALERT_HANDLER_ALERT_REGWEN_51_REG_RESVAL 0x1u
#define ALERT_HANDLER_ALERT_REGWEN_51_EN_51_BIT 0
 
// Register write enable for alert enable bits.
#define ALERT_HANDLER_ALERT_REGWEN_52_REG_OFFSET 0xe8
#define ALERT_HANDLER_ALERT_REGWEN_52_REG_RESVAL 0x1u
#define ALERT_HANDLER_ALERT_REGWEN_52_EN_52_BIT 0
 
// Register write enable for alert enable bits.
#define ALERT_HANDLER_ALERT_REGWEN_53_REG_OFFSET 0xec
#define ALERT_HANDLER_ALERT_REGWEN_53_REG_RESVAL 0x1u
#define ALERT_HANDLER_ALERT_REGWEN_53_EN_53_BIT 0
 
// Register write enable for alert enable bits.
#define ALERT_HANDLER_ALERT_REGWEN_54_REG_OFFSET 0xf0
#define ALERT_HANDLER_ALERT_REGWEN_54_REG_RESVAL 0x1u
#define ALERT_HANDLER_ALERT_REGWEN_54_EN_54_BIT 0
 
// Register write enable for alert enable bits.
#define ALERT_HANDLER_ALERT_REGWEN_55_REG_OFFSET 0xf4
#define ALERT_HANDLER_ALERT_REGWEN_55_REG_RESVAL 0x1u
#define ALERT_HANDLER_ALERT_REGWEN_55_EN_55_BIT 0
 
// Register write enable for alert enable bits.
#define ALERT_HANDLER_ALERT_REGWEN_56_REG_OFFSET 0xf8
#define ALERT_HANDLER_ALERT_REGWEN_56_REG_RESVAL 0x1u
#define ALERT_HANDLER_ALERT_REGWEN_56_EN_56_BIT 0
 
// Register write enable for alert enable bits.
#define ALERT_HANDLER_ALERT_REGWEN_57_REG_OFFSET 0xfc
#define ALERT_HANDLER_ALERT_REGWEN_57_REG_RESVAL 0x1u
#define ALERT_HANDLER_ALERT_REGWEN_57_EN_57_BIT 0
 
// Register write enable for alert enable bits.
#define ALERT_HANDLER_ALERT_REGWEN_58_REG_OFFSET 0x100
#define ALERT_HANDLER_ALERT_REGWEN_58_REG_RESVAL 0x1u
#define ALERT_HANDLER_ALERT_REGWEN_58_EN_58_BIT 0
 
// Register write enable for alert enable bits.
#define ALERT_HANDLER_ALERT_REGWEN_59_REG_OFFSET 0x104
#define ALERT_HANDLER_ALERT_REGWEN_59_REG_RESVAL 0x1u
#define ALERT_HANDLER_ALERT_REGWEN_59_EN_59_BIT 0
 
// Register write enable for alert enable bits.
#define ALERT_HANDLER_ALERT_REGWEN_60_REG_OFFSET 0x108
#define ALERT_HANDLER_ALERT_REGWEN_60_REG_RESVAL 0x1u
#define ALERT_HANDLER_ALERT_REGWEN_60_EN_60_BIT 0
 
// Register write enable for alert enable bits.
#define ALERT_HANDLER_ALERT_REGWEN_61_REG_OFFSET 0x10c
#define ALERT_HANDLER_ALERT_REGWEN_61_REG_RESVAL 0x1u
#define ALERT_HANDLER_ALERT_REGWEN_61_EN_61_BIT 0
 
// Register write enable for alert enable bits.
#define ALERT_HANDLER_ALERT_REGWEN_62_REG_OFFSET 0x110
#define ALERT_HANDLER_ALERT_REGWEN_62_REG_RESVAL 0x1u
#define ALERT_HANDLER_ALERT_REGWEN_62_EN_62_BIT 0
 
// Register write enable for alert enable bits.
#define ALERT_HANDLER_ALERT_REGWEN_63_REG_OFFSET 0x114
#define ALERT_HANDLER_ALERT_REGWEN_63_REG_RESVAL 0x1u
#define ALERT_HANDLER_ALERT_REGWEN_63_EN_63_BIT 0
 
// Register write enable for alert enable bits.
#define ALERT_HANDLER_ALERT_REGWEN_64_REG_OFFSET 0x118
#define ALERT_HANDLER_ALERT_REGWEN_64_REG_RESVAL 0x1u
#define ALERT_HANDLER_ALERT_REGWEN_64_EN_64_BIT 0
 
// Register write enable for alert enable bits.
#define ALERT_HANDLER_ALERT_REGWEN_65_REG_OFFSET 0x11c
#define ALERT_HANDLER_ALERT_REGWEN_65_REG_RESVAL 0x1u
#define ALERT_HANDLER_ALERT_REGWEN_65_EN_65_BIT 0
 
// Enable register for alerts. (common parameters)
#define ALERT_HANDLER_ALERT_EN_SHADOWED_EN_A_FIELD_WIDTH 1
#define ALERT_HANDLER_ALERT_EN_SHADOWED_MULTIREG_COUNT 66
 
// Enable register for alerts.
#define ALERT_HANDLER_ALERT_EN_SHADOWED_0_REG_OFFSET 0x120
#define ALERT_HANDLER_ALERT_EN_SHADOWED_0_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_EN_SHADOWED_0_EN_A_0_BIT 0
 
// Enable register for alerts.
#define ALERT_HANDLER_ALERT_EN_SHADOWED_1_REG_OFFSET 0x124
#define ALERT_HANDLER_ALERT_EN_SHADOWED_1_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_EN_SHADOWED_1_EN_A_1_BIT 0
 
// Enable register for alerts.
#define ALERT_HANDLER_ALERT_EN_SHADOWED_2_REG_OFFSET 0x128
#define ALERT_HANDLER_ALERT_EN_SHADOWED_2_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_EN_SHADOWED_2_EN_A_2_BIT 0
 
// Enable register for alerts.
#define ALERT_HANDLER_ALERT_EN_SHADOWED_3_REG_OFFSET 0x12c
#define ALERT_HANDLER_ALERT_EN_SHADOWED_3_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_EN_SHADOWED_3_EN_A_3_BIT 0
 
// Enable register for alerts.
#define ALERT_HANDLER_ALERT_EN_SHADOWED_4_REG_OFFSET 0x130
#define ALERT_HANDLER_ALERT_EN_SHADOWED_4_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_EN_SHADOWED_4_EN_A_4_BIT 0
 
// Enable register for alerts.
#define ALERT_HANDLER_ALERT_EN_SHADOWED_5_REG_OFFSET 0x134
#define ALERT_HANDLER_ALERT_EN_SHADOWED_5_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_EN_SHADOWED_5_EN_A_5_BIT 0
 
// Enable register for alerts.
#define ALERT_HANDLER_ALERT_EN_SHADOWED_6_REG_OFFSET 0x138
#define ALERT_HANDLER_ALERT_EN_SHADOWED_6_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_EN_SHADOWED_6_EN_A_6_BIT 0
 
// Enable register for alerts.
#define ALERT_HANDLER_ALERT_EN_SHADOWED_7_REG_OFFSET 0x13c
#define ALERT_HANDLER_ALERT_EN_SHADOWED_7_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_EN_SHADOWED_7_EN_A_7_BIT 0
 
// Enable register for alerts.
#define ALERT_HANDLER_ALERT_EN_SHADOWED_8_REG_OFFSET 0x140
#define ALERT_HANDLER_ALERT_EN_SHADOWED_8_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_EN_SHADOWED_8_EN_A_8_BIT 0
 
// Enable register for alerts.
#define ALERT_HANDLER_ALERT_EN_SHADOWED_9_REG_OFFSET 0x144
#define ALERT_HANDLER_ALERT_EN_SHADOWED_9_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_EN_SHADOWED_9_EN_A_9_BIT 0
 
// Enable register for alerts.
#define ALERT_HANDLER_ALERT_EN_SHADOWED_10_REG_OFFSET 0x148
#define ALERT_HANDLER_ALERT_EN_SHADOWED_10_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_EN_SHADOWED_10_EN_A_10_BIT 0
 
// Enable register for alerts.
#define ALERT_HANDLER_ALERT_EN_SHADOWED_11_REG_OFFSET 0x14c
#define ALERT_HANDLER_ALERT_EN_SHADOWED_11_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_EN_SHADOWED_11_EN_A_11_BIT 0
 
// Enable register for alerts.
#define ALERT_HANDLER_ALERT_EN_SHADOWED_12_REG_OFFSET 0x150
#define ALERT_HANDLER_ALERT_EN_SHADOWED_12_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_EN_SHADOWED_12_EN_A_12_BIT 0
 
// Enable register for alerts.
#define ALERT_HANDLER_ALERT_EN_SHADOWED_13_REG_OFFSET 0x154
#define ALERT_HANDLER_ALERT_EN_SHADOWED_13_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_EN_SHADOWED_13_EN_A_13_BIT 0
 
// Enable register for alerts.
#define ALERT_HANDLER_ALERT_EN_SHADOWED_14_REG_OFFSET 0x158
#define ALERT_HANDLER_ALERT_EN_SHADOWED_14_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_EN_SHADOWED_14_EN_A_14_BIT 0
 
// Enable register for alerts.
#define ALERT_HANDLER_ALERT_EN_SHADOWED_15_REG_OFFSET 0x15c
#define ALERT_HANDLER_ALERT_EN_SHADOWED_15_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_EN_SHADOWED_15_EN_A_15_BIT 0
 
// Enable register for alerts.
#define ALERT_HANDLER_ALERT_EN_SHADOWED_16_REG_OFFSET 0x160
#define ALERT_HANDLER_ALERT_EN_SHADOWED_16_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_EN_SHADOWED_16_EN_A_16_BIT 0
 
// Enable register for alerts.
#define ALERT_HANDLER_ALERT_EN_SHADOWED_17_REG_OFFSET 0x164
#define ALERT_HANDLER_ALERT_EN_SHADOWED_17_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_EN_SHADOWED_17_EN_A_17_BIT 0
 
// Enable register for alerts.
#define ALERT_HANDLER_ALERT_EN_SHADOWED_18_REG_OFFSET 0x168
#define ALERT_HANDLER_ALERT_EN_SHADOWED_18_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_EN_SHADOWED_18_EN_A_18_BIT 0
 
// Enable register for alerts.
#define ALERT_HANDLER_ALERT_EN_SHADOWED_19_REG_OFFSET 0x16c
#define ALERT_HANDLER_ALERT_EN_SHADOWED_19_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_EN_SHADOWED_19_EN_A_19_BIT 0
 
// Enable register for alerts.
#define ALERT_HANDLER_ALERT_EN_SHADOWED_20_REG_OFFSET 0x170
#define ALERT_HANDLER_ALERT_EN_SHADOWED_20_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_EN_SHADOWED_20_EN_A_20_BIT 0
 
// Enable register for alerts.
#define ALERT_HANDLER_ALERT_EN_SHADOWED_21_REG_OFFSET 0x174
#define ALERT_HANDLER_ALERT_EN_SHADOWED_21_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_EN_SHADOWED_21_EN_A_21_BIT 0
 
// Enable register for alerts.
#define ALERT_HANDLER_ALERT_EN_SHADOWED_22_REG_OFFSET 0x178
#define ALERT_HANDLER_ALERT_EN_SHADOWED_22_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_EN_SHADOWED_22_EN_A_22_BIT 0
 
// Enable register for alerts.
#define ALERT_HANDLER_ALERT_EN_SHADOWED_23_REG_OFFSET 0x17c
#define ALERT_HANDLER_ALERT_EN_SHADOWED_23_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_EN_SHADOWED_23_EN_A_23_BIT 0
 
// Enable register for alerts.
#define ALERT_HANDLER_ALERT_EN_SHADOWED_24_REG_OFFSET 0x180
#define ALERT_HANDLER_ALERT_EN_SHADOWED_24_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_EN_SHADOWED_24_EN_A_24_BIT 0
 
// Enable register for alerts.
#define ALERT_HANDLER_ALERT_EN_SHADOWED_25_REG_OFFSET 0x184
#define ALERT_HANDLER_ALERT_EN_SHADOWED_25_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_EN_SHADOWED_25_EN_A_25_BIT 0
 
// Enable register for alerts.
#define ALERT_HANDLER_ALERT_EN_SHADOWED_26_REG_OFFSET 0x188
#define ALERT_HANDLER_ALERT_EN_SHADOWED_26_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_EN_SHADOWED_26_EN_A_26_BIT 0
 
// Enable register for alerts.
#define ALERT_HANDLER_ALERT_EN_SHADOWED_27_REG_OFFSET 0x18c
#define ALERT_HANDLER_ALERT_EN_SHADOWED_27_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_EN_SHADOWED_27_EN_A_27_BIT 0
 
// Enable register for alerts.
#define ALERT_HANDLER_ALERT_EN_SHADOWED_28_REG_OFFSET 0x190
#define ALERT_HANDLER_ALERT_EN_SHADOWED_28_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_EN_SHADOWED_28_EN_A_28_BIT 0
 
// Enable register for alerts.
#define ALERT_HANDLER_ALERT_EN_SHADOWED_29_REG_OFFSET 0x194
#define ALERT_HANDLER_ALERT_EN_SHADOWED_29_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_EN_SHADOWED_29_EN_A_29_BIT 0
 
// Enable register for alerts.
#define ALERT_HANDLER_ALERT_EN_SHADOWED_30_REG_OFFSET 0x198
#define ALERT_HANDLER_ALERT_EN_SHADOWED_30_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_EN_SHADOWED_30_EN_A_30_BIT 0
 
// Enable register for alerts.
#define ALERT_HANDLER_ALERT_EN_SHADOWED_31_REG_OFFSET 0x19c
#define ALERT_HANDLER_ALERT_EN_SHADOWED_31_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_EN_SHADOWED_31_EN_A_31_BIT 0
 
// Enable register for alerts.
#define ALERT_HANDLER_ALERT_EN_SHADOWED_32_REG_OFFSET 0x1a0
#define ALERT_HANDLER_ALERT_EN_SHADOWED_32_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_EN_SHADOWED_32_EN_A_32_BIT 0
 
// Enable register for alerts.
#define ALERT_HANDLER_ALERT_EN_SHADOWED_33_REG_OFFSET 0x1a4
#define ALERT_HANDLER_ALERT_EN_SHADOWED_33_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_EN_SHADOWED_33_EN_A_33_BIT 0
 
// Enable register for alerts.
#define ALERT_HANDLER_ALERT_EN_SHADOWED_34_REG_OFFSET 0x1a8
#define ALERT_HANDLER_ALERT_EN_SHADOWED_34_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_EN_SHADOWED_34_EN_A_34_BIT 0
 
// Enable register for alerts.
#define ALERT_HANDLER_ALERT_EN_SHADOWED_35_REG_OFFSET 0x1ac
#define ALERT_HANDLER_ALERT_EN_SHADOWED_35_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_EN_SHADOWED_35_EN_A_35_BIT 0
 
// Enable register for alerts.
#define ALERT_HANDLER_ALERT_EN_SHADOWED_36_REG_OFFSET 0x1b0
#define ALERT_HANDLER_ALERT_EN_SHADOWED_36_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_EN_SHADOWED_36_EN_A_36_BIT 0
 
// Enable register for alerts.
#define ALERT_HANDLER_ALERT_EN_SHADOWED_37_REG_OFFSET 0x1b4
#define ALERT_HANDLER_ALERT_EN_SHADOWED_37_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_EN_SHADOWED_37_EN_A_37_BIT 0
 
// Enable register for alerts.
#define ALERT_HANDLER_ALERT_EN_SHADOWED_38_REG_OFFSET 0x1b8
#define ALERT_HANDLER_ALERT_EN_SHADOWED_38_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_EN_SHADOWED_38_EN_A_38_BIT 0
 
// Enable register for alerts.
#define ALERT_HANDLER_ALERT_EN_SHADOWED_39_REG_OFFSET 0x1bc
#define ALERT_HANDLER_ALERT_EN_SHADOWED_39_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_EN_SHADOWED_39_EN_A_39_BIT 0
 
// Enable register for alerts.
#define ALERT_HANDLER_ALERT_EN_SHADOWED_40_REG_OFFSET 0x1c0
#define ALERT_HANDLER_ALERT_EN_SHADOWED_40_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_EN_SHADOWED_40_EN_A_40_BIT 0
 
// Enable register for alerts.
#define ALERT_HANDLER_ALERT_EN_SHADOWED_41_REG_OFFSET 0x1c4
#define ALERT_HANDLER_ALERT_EN_SHADOWED_41_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_EN_SHADOWED_41_EN_A_41_BIT 0
 
// Enable register for alerts.
#define ALERT_HANDLER_ALERT_EN_SHADOWED_42_REG_OFFSET 0x1c8
#define ALERT_HANDLER_ALERT_EN_SHADOWED_42_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_EN_SHADOWED_42_EN_A_42_BIT 0
 
// Enable register for alerts.
#define ALERT_HANDLER_ALERT_EN_SHADOWED_43_REG_OFFSET 0x1cc
#define ALERT_HANDLER_ALERT_EN_SHADOWED_43_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_EN_SHADOWED_43_EN_A_43_BIT 0
 
// Enable register for alerts.
#define ALERT_HANDLER_ALERT_EN_SHADOWED_44_REG_OFFSET 0x1d0
#define ALERT_HANDLER_ALERT_EN_SHADOWED_44_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_EN_SHADOWED_44_EN_A_44_BIT 0
 
// Enable register for alerts.
#define ALERT_HANDLER_ALERT_EN_SHADOWED_45_REG_OFFSET 0x1d4
#define ALERT_HANDLER_ALERT_EN_SHADOWED_45_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_EN_SHADOWED_45_EN_A_45_BIT 0
 
// Enable register for alerts.
#define ALERT_HANDLER_ALERT_EN_SHADOWED_46_REG_OFFSET 0x1d8
#define ALERT_HANDLER_ALERT_EN_SHADOWED_46_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_EN_SHADOWED_46_EN_A_46_BIT 0
 
// Enable register for alerts.
#define ALERT_HANDLER_ALERT_EN_SHADOWED_47_REG_OFFSET 0x1dc
#define ALERT_HANDLER_ALERT_EN_SHADOWED_47_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_EN_SHADOWED_47_EN_A_47_BIT 0
 
// Enable register for alerts.
#define ALERT_HANDLER_ALERT_EN_SHADOWED_48_REG_OFFSET 0x1e0
#define ALERT_HANDLER_ALERT_EN_SHADOWED_48_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_EN_SHADOWED_48_EN_A_48_BIT 0
 
// Enable register for alerts.
#define ALERT_HANDLER_ALERT_EN_SHADOWED_49_REG_OFFSET 0x1e4
#define ALERT_HANDLER_ALERT_EN_SHADOWED_49_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_EN_SHADOWED_49_EN_A_49_BIT 0
 
// Enable register for alerts.
#define ALERT_HANDLER_ALERT_EN_SHADOWED_50_REG_OFFSET 0x1e8
#define ALERT_HANDLER_ALERT_EN_SHADOWED_50_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_EN_SHADOWED_50_EN_A_50_BIT 0
 
// Enable register for alerts.
#define ALERT_HANDLER_ALERT_EN_SHADOWED_51_REG_OFFSET 0x1ec
#define ALERT_HANDLER_ALERT_EN_SHADOWED_51_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_EN_SHADOWED_51_EN_A_51_BIT 0
 
// Enable register for alerts.
#define ALERT_HANDLER_ALERT_EN_SHADOWED_52_REG_OFFSET 0x1f0
#define ALERT_HANDLER_ALERT_EN_SHADOWED_52_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_EN_SHADOWED_52_EN_A_52_BIT 0
 
// Enable register for alerts.
#define ALERT_HANDLER_ALERT_EN_SHADOWED_53_REG_OFFSET 0x1f4
#define ALERT_HANDLER_ALERT_EN_SHADOWED_53_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_EN_SHADOWED_53_EN_A_53_BIT 0
 
// Enable register for alerts.
#define ALERT_HANDLER_ALERT_EN_SHADOWED_54_REG_OFFSET 0x1f8
#define ALERT_HANDLER_ALERT_EN_SHADOWED_54_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_EN_SHADOWED_54_EN_A_54_BIT 0
 
// Enable register for alerts.
#define ALERT_HANDLER_ALERT_EN_SHADOWED_55_REG_OFFSET 0x1fc
#define ALERT_HANDLER_ALERT_EN_SHADOWED_55_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_EN_SHADOWED_55_EN_A_55_BIT 0
 
// Enable register for alerts.
#define ALERT_HANDLER_ALERT_EN_SHADOWED_56_REG_OFFSET 0x200
#define ALERT_HANDLER_ALERT_EN_SHADOWED_56_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_EN_SHADOWED_56_EN_A_56_BIT 0
 
// Enable register for alerts.
#define ALERT_HANDLER_ALERT_EN_SHADOWED_57_REG_OFFSET 0x204
#define ALERT_HANDLER_ALERT_EN_SHADOWED_57_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_EN_SHADOWED_57_EN_A_57_BIT 0
 
// Enable register for alerts.
#define ALERT_HANDLER_ALERT_EN_SHADOWED_58_REG_OFFSET 0x208
#define ALERT_HANDLER_ALERT_EN_SHADOWED_58_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_EN_SHADOWED_58_EN_A_58_BIT 0
 
// Enable register for alerts.
#define ALERT_HANDLER_ALERT_EN_SHADOWED_59_REG_OFFSET 0x20c
#define ALERT_HANDLER_ALERT_EN_SHADOWED_59_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_EN_SHADOWED_59_EN_A_59_BIT 0
 
// Enable register for alerts.
#define ALERT_HANDLER_ALERT_EN_SHADOWED_60_REG_OFFSET 0x210
#define ALERT_HANDLER_ALERT_EN_SHADOWED_60_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_EN_SHADOWED_60_EN_A_60_BIT 0
 
// Enable register for alerts.
#define ALERT_HANDLER_ALERT_EN_SHADOWED_61_REG_OFFSET 0x214
#define ALERT_HANDLER_ALERT_EN_SHADOWED_61_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_EN_SHADOWED_61_EN_A_61_BIT 0
 
// Enable register for alerts.
#define ALERT_HANDLER_ALERT_EN_SHADOWED_62_REG_OFFSET 0x218
#define ALERT_HANDLER_ALERT_EN_SHADOWED_62_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_EN_SHADOWED_62_EN_A_62_BIT 0
 
// Enable register for alerts.
#define ALERT_HANDLER_ALERT_EN_SHADOWED_63_REG_OFFSET 0x21c
#define ALERT_HANDLER_ALERT_EN_SHADOWED_63_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_EN_SHADOWED_63_EN_A_63_BIT 0
 
// Enable register for alerts.
#define ALERT_HANDLER_ALERT_EN_SHADOWED_64_REG_OFFSET 0x220
#define ALERT_HANDLER_ALERT_EN_SHADOWED_64_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_EN_SHADOWED_64_EN_A_64_BIT 0
 
// Enable register for alerts.
#define ALERT_HANDLER_ALERT_EN_SHADOWED_65_REG_OFFSET 0x224
#define ALERT_HANDLER_ALERT_EN_SHADOWED_65_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_EN_SHADOWED_65_EN_A_65_BIT 0
 
// Class assignment of alerts. (common parameters)
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_CLASS_A_FIELD_WIDTH 2
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_MULTIREG_COUNT 66
 
// Class assignment of alerts.
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_REG_OFFSET 0x228
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_MASK 0x3u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_OFFSET 0
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_OFFSET })
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_VALUE_CLASSA 0x0
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_VALUE_CLASSB 0x1
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_VALUE_CLASSC 0x2
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_VALUE_CLASSD 0x3
 
// Class assignment of alerts.
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_REG_OFFSET 0x22c
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_CLASS_A_1_MASK 0x3u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_CLASS_A_1_OFFSET 0
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_CLASS_A_1_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_CLASS_A_1_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_CLASS_A_1_OFFSET })
 
// Class assignment of alerts.
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_REG_OFFSET 0x230
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_CLASS_A_2_MASK 0x3u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_CLASS_A_2_OFFSET 0
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_CLASS_A_2_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_CLASS_A_2_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_CLASS_A_2_OFFSET })
 
// Class assignment of alerts.
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_REG_OFFSET 0x234
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_CLASS_A_3_MASK 0x3u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_CLASS_A_3_OFFSET 0
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_CLASS_A_3_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_CLASS_A_3_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_CLASS_A_3_OFFSET })
 
// Class assignment of alerts.
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_REG_OFFSET 0x238
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_CLASS_A_4_MASK 0x3u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_CLASS_A_4_OFFSET 0
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_CLASS_A_4_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_CLASS_A_4_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_CLASS_A_4_OFFSET })
 
// Class assignment of alerts.
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_REG_OFFSET 0x23c
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_CLASS_A_5_MASK 0x3u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_CLASS_A_5_OFFSET 0
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_CLASS_A_5_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_CLASS_A_5_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_CLASS_A_5_OFFSET })
 
// Class assignment of alerts.
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_REG_OFFSET 0x240
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_CLASS_A_6_MASK 0x3u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_CLASS_A_6_OFFSET 0
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_CLASS_A_6_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_CLASS_A_6_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_CLASS_A_6_OFFSET })
 
// Class assignment of alerts.
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_REG_OFFSET 0x244
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_CLASS_A_7_MASK 0x3u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_CLASS_A_7_OFFSET 0
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_CLASS_A_7_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_CLASS_A_7_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_CLASS_A_7_OFFSET })
 
// Class assignment of alerts.
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_REG_OFFSET 0x248
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_CLASS_A_8_MASK 0x3u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_CLASS_A_8_OFFSET 0
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_CLASS_A_8_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_CLASS_A_8_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_CLASS_A_8_OFFSET })
 
// Class assignment of alerts.
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_REG_OFFSET 0x24c
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_CLASS_A_9_MASK 0x3u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_CLASS_A_9_OFFSET 0
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_CLASS_A_9_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_CLASS_A_9_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_CLASS_A_9_OFFSET })
 
// Class assignment of alerts.
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_REG_OFFSET 0x250
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_CLASS_A_10_MASK 0x3u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_CLASS_A_10_OFFSET 0
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_CLASS_A_10_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_CLASS_A_10_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_CLASS_A_10_OFFSET })
 
// Class assignment of alerts.
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_REG_OFFSET 0x254
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_CLASS_A_11_MASK 0x3u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_CLASS_A_11_OFFSET 0
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_CLASS_A_11_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_CLASS_A_11_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_CLASS_A_11_OFFSET })
 
// Class assignment of alerts.
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_REG_OFFSET 0x258
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_CLASS_A_12_MASK 0x3u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_CLASS_A_12_OFFSET 0
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_CLASS_A_12_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_CLASS_A_12_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_CLASS_A_12_OFFSET })
 
// Class assignment of alerts.
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_REG_OFFSET 0x25c
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_CLASS_A_13_MASK 0x3u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_CLASS_A_13_OFFSET 0
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_CLASS_A_13_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_CLASS_A_13_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_CLASS_A_13_OFFSET })
 
// Class assignment of alerts.
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_REG_OFFSET 0x260
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_CLASS_A_14_MASK 0x3u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_CLASS_A_14_OFFSET 0
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_CLASS_A_14_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_CLASS_A_14_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_CLASS_A_14_OFFSET })
 
// Class assignment of alerts.
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_REG_OFFSET 0x264
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_CLASS_A_15_MASK 0x3u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_CLASS_A_15_OFFSET 0
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_CLASS_A_15_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_CLASS_A_15_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_CLASS_A_15_OFFSET })
 
// Class assignment of alerts.
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_REG_OFFSET 0x268
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_CLASS_A_16_MASK 0x3u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_CLASS_A_16_OFFSET 0
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_CLASS_A_16_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_CLASS_A_16_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_CLASS_A_16_OFFSET })
 
// Class assignment of alerts.
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_REG_OFFSET 0x26c
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_CLASS_A_17_MASK 0x3u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_CLASS_A_17_OFFSET 0
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_CLASS_A_17_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_CLASS_A_17_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_CLASS_A_17_OFFSET })
 
// Class assignment of alerts.
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_REG_OFFSET 0x270
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_CLASS_A_18_MASK 0x3u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_CLASS_A_18_OFFSET 0
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_CLASS_A_18_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_CLASS_A_18_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_CLASS_A_18_OFFSET })
 
// Class assignment of alerts.
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_REG_OFFSET 0x274
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_CLASS_A_19_MASK 0x3u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_CLASS_A_19_OFFSET 0
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_CLASS_A_19_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_CLASS_A_19_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_CLASS_A_19_OFFSET })
 
// Class assignment of alerts.
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_REG_OFFSET 0x278
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_CLASS_A_20_MASK 0x3u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_CLASS_A_20_OFFSET 0
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_CLASS_A_20_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_CLASS_A_20_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_CLASS_A_20_OFFSET })
 
// Class assignment of alerts.
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_REG_OFFSET 0x27c
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_CLASS_A_21_MASK 0x3u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_CLASS_A_21_OFFSET 0
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_CLASS_A_21_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_CLASS_A_21_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_CLASS_A_21_OFFSET })
 
// Class assignment of alerts.
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_REG_OFFSET 0x280
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_CLASS_A_22_MASK 0x3u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_CLASS_A_22_OFFSET 0
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_CLASS_A_22_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_CLASS_A_22_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_CLASS_A_22_OFFSET })
 
// Class assignment of alerts.
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_REG_OFFSET 0x284
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_CLASS_A_23_MASK 0x3u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_CLASS_A_23_OFFSET 0
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_CLASS_A_23_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_CLASS_A_23_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_CLASS_A_23_OFFSET })
 
// Class assignment of alerts.
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_REG_OFFSET 0x288
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_CLASS_A_24_MASK 0x3u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_CLASS_A_24_OFFSET 0
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_CLASS_A_24_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_CLASS_A_24_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_CLASS_A_24_OFFSET })
 
// Class assignment of alerts.
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_REG_OFFSET 0x28c
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_CLASS_A_25_MASK 0x3u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_CLASS_A_25_OFFSET 0
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_CLASS_A_25_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_CLASS_A_25_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_CLASS_A_25_OFFSET })
 
// Class assignment of alerts.
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_REG_OFFSET 0x290
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_CLASS_A_26_MASK 0x3u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_CLASS_A_26_OFFSET 0
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_CLASS_A_26_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_CLASS_A_26_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_CLASS_A_26_OFFSET })
 
// Class assignment of alerts.
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_REG_OFFSET 0x294
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_CLASS_A_27_MASK 0x3u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_CLASS_A_27_OFFSET 0
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_CLASS_A_27_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_CLASS_A_27_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_CLASS_A_27_OFFSET })
 
// Class assignment of alerts.
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_REG_OFFSET 0x298
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_CLASS_A_28_MASK 0x3u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_CLASS_A_28_OFFSET 0
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_CLASS_A_28_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_CLASS_A_28_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_CLASS_A_28_OFFSET })
 
// Class assignment of alerts.
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_REG_OFFSET 0x29c
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_CLASS_A_29_MASK 0x3u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_CLASS_A_29_OFFSET 0
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_CLASS_A_29_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_CLASS_A_29_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_CLASS_A_29_OFFSET })
 
// Class assignment of alerts.
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_REG_OFFSET 0x2a0
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_CLASS_A_30_MASK 0x3u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_CLASS_A_30_OFFSET 0
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_CLASS_A_30_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_CLASS_A_30_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_CLASS_A_30_OFFSET })
 
// Class assignment of alerts.
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_REG_OFFSET 0x2a4
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_CLASS_A_31_MASK 0x3u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_CLASS_A_31_OFFSET 0
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_CLASS_A_31_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_CLASS_A_31_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_CLASS_A_31_OFFSET })
 
// Class assignment of alerts.
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_REG_OFFSET 0x2a8
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_CLASS_A_32_MASK 0x3u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_CLASS_A_32_OFFSET 0
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_CLASS_A_32_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_CLASS_A_32_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_CLASS_A_32_OFFSET })
 
// Class assignment of alerts.
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_REG_OFFSET 0x2ac
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_CLASS_A_33_MASK 0x3u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_CLASS_A_33_OFFSET 0
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_CLASS_A_33_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_CLASS_A_33_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_CLASS_A_33_OFFSET })
 
// Class assignment of alerts.
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_REG_OFFSET 0x2b0
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_CLASS_A_34_MASK 0x3u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_CLASS_A_34_OFFSET 0
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_CLASS_A_34_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_CLASS_A_34_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_CLASS_A_34_OFFSET })
 
// Class assignment of alerts.
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_REG_OFFSET 0x2b4
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_CLASS_A_35_MASK 0x3u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_CLASS_A_35_OFFSET 0
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_CLASS_A_35_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_CLASS_A_35_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_CLASS_A_35_OFFSET })
 
// Class assignment of alerts.
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_REG_OFFSET 0x2b8
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_CLASS_A_36_MASK 0x3u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_CLASS_A_36_OFFSET 0
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_CLASS_A_36_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_CLASS_A_36_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_CLASS_A_36_OFFSET })
 
// Class assignment of alerts.
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_REG_OFFSET 0x2bc
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_CLASS_A_37_MASK 0x3u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_CLASS_A_37_OFFSET 0
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_CLASS_A_37_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_CLASS_A_37_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_CLASS_A_37_OFFSET })
 
// Class assignment of alerts.
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_REG_OFFSET 0x2c0
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_CLASS_A_38_MASK 0x3u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_CLASS_A_38_OFFSET 0
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_CLASS_A_38_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_CLASS_A_38_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_CLASS_A_38_OFFSET })
 
// Class assignment of alerts.
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_REG_OFFSET 0x2c4
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_CLASS_A_39_MASK 0x3u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_CLASS_A_39_OFFSET 0
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_CLASS_A_39_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_CLASS_A_39_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_CLASS_A_39_OFFSET })
 
// Class assignment of alerts.
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_REG_OFFSET 0x2c8
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_CLASS_A_40_MASK 0x3u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_CLASS_A_40_OFFSET 0
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_CLASS_A_40_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_CLASS_A_40_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_CLASS_A_40_OFFSET })
 
// Class assignment of alerts.
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_REG_OFFSET 0x2cc
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_CLASS_A_41_MASK 0x3u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_CLASS_A_41_OFFSET 0
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_CLASS_A_41_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_CLASS_A_41_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_CLASS_A_41_OFFSET })
 
// Class assignment of alerts.
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_REG_OFFSET 0x2d0
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_CLASS_A_42_MASK 0x3u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_CLASS_A_42_OFFSET 0
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_CLASS_A_42_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_CLASS_A_42_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_CLASS_A_42_OFFSET })
 
// Class assignment of alerts.
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_REG_OFFSET 0x2d4
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_CLASS_A_43_MASK 0x3u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_CLASS_A_43_OFFSET 0
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_CLASS_A_43_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_CLASS_A_43_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_CLASS_A_43_OFFSET })
 
// Class assignment of alerts.
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_REG_OFFSET 0x2d8
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_CLASS_A_44_MASK 0x3u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_CLASS_A_44_OFFSET 0
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_CLASS_A_44_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_CLASS_A_44_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_CLASS_A_44_OFFSET })
 
// Class assignment of alerts.
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_REG_OFFSET 0x2dc
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_CLASS_A_45_MASK 0x3u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_CLASS_A_45_OFFSET 0
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_CLASS_A_45_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_CLASS_A_45_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_CLASS_A_45_OFFSET })
 
// Class assignment of alerts.
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_REG_OFFSET 0x2e0
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_CLASS_A_46_MASK 0x3u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_CLASS_A_46_OFFSET 0
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_CLASS_A_46_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_CLASS_A_46_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_CLASS_A_46_OFFSET })
 
// Class assignment of alerts.
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_REG_OFFSET 0x2e4
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_CLASS_A_47_MASK 0x3u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_CLASS_A_47_OFFSET 0
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_CLASS_A_47_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_CLASS_A_47_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_CLASS_A_47_OFFSET })
 
// Class assignment of alerts.
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_REG_OFFSET 0x2e8
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_CLASS_A_48_MASK 0x3u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_CLASS_A_48_OFFSET 0
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_CLASS_A_48_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_CLASS_A_48_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_CLASS_A_48_OFFSET })
 
// Class assignment of alerts.
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_REG_OFFSET 0x2ec
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_CLASS_A_49_MASK 0x3u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_CLASS_A_49_OFFSET 0
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_CLASS_A_49_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_CLASS_A_49_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_CLASS_A_49_OFFSET })
 
// Class assignment of alerts.
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_REG_OFFSET 0x2f0
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_CLASS_A_50_MASK 0x3u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_CLASS_A_50_OFFSET 0
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_CLASS_A_50_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_CLASS_A_50_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_CLASS_A_50_OFFSET })
 
// Class assignment of alerts.
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_REG_OFFSET 0x2f4
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_CLASS_A_51_MASK 0x3u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_CLASS_A_51_OFFSET 0
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_CLASS_A_51_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_CLASS_A_51_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_CLASS_A_51_OFFSET })
 
// Class assignment of alerts.
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_REG_OFFSET 0x2f8
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_CLASS_A_52_MASK 0x3u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_CLASS_A_52_OFFSET 0
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_CLASS_A_52_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_CLASS_A_52_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_CLASS_A_52_OFFSET })
 
// Class assignment of alerts.
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_REG_OFFSET 0x2fc
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_CLASS_A_53_MASK 0x3u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_CLASS_A_53_OFFSET 0
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_CLASS_A_53_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_CLASS_A_53_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_CLASS_A_53_OFFSET })
 
// Class assignment of alerts.
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_REG_OFFSET 0x300
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_CLASS_A_54_MASK 0x3u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_CLASS_A_54_OFFSET 0
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_CLASS_A_54_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_CLASS_A_54_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_CLASS_A_54_OFFSET })
 
// Class assignment of alerts.
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_REG_OFFSET 0x304
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_CLASS_A_55_MASK 0x3u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_CLASS_A_55_OFFSET 0
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_CLASS_A_55_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_CLASS_A_55_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_CLASS_A_55_OFFSET })
 
// Class assignment of alerts.
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_REG_OFFSET 0x308
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_CLASS_A_56_MASK 0x3u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_CLASS_A_56_OFFSET 0
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_CLASS_A_56_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_CLASS_A_56_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_CLASS_A_56_OFFSET })
 
// Class assignment of alerts.
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_REG_OFFSET 0x30c
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_CLASS_A_57_MASK 0x3u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_CLASS_A_57_OFFSET 0
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_CLASS_A_57_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_CLASS_A_57_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_CLASS_A_57_OFFSET })
 
// Class assignment of alerts.
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_REG_OFFSET 0x310
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_CLASS_A_58_MASK 0x3u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_CLASS_A_58_OFFSET 0
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_CLASS_A_58_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_CLASS_A_58_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_CLASS_A_58_OFFSET })
 
// Class assignment of alerts.
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_REG_OFFSET 0x314
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_CLASS_A_59_MASK 0x3u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_CLASS_A_59_OFFSET 0
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_CLASS_A_59_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_CLASS_A_59_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_CLASS_A_59_OFFSET })
 
// Class assignment of alerts.
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_60_REG_OFFSET 0x318
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_60_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_60_CLASS_A_60_MASK 0x3u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_60_CLASS_A_60_OFFSET 0
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_60_CLASS_A_60_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_60_CLASS_A_60_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_60_CLASS_A_60_OFFSET })
 
// Class assignment of alerts.
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_61_REG_OFFSET 0x31c
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_61_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_61_CLASS_A_61_MASK 0x3u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_61_CLASS_A_61_OFFSET 0
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_61_CLASS_A_61_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_61_CLASS_A_61_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_61_CLASS_A_61_OFFSET })
 
// Class assignment of alerts.
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_62_REG_OFFSET 0x320
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_62_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_62_CLASS_A_62_MASK 0x3u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_62_CLASS_A_62_OFFSET 0
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_62_CLASS_A_62_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_62_CLASS_A_62_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_62_CLASS_A_62_OFFSET })
 
// Class assignment of alerts.
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_63_REG_OFFSET 0x324
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_63_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_63_CLASS_A_63_MASK 0x3u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_63_CLASS_A_63_OFFSET 0
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_63_CLASS_A_63_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_63_CLASS_A_63_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_63_CLASS_A_63_OFFSET })
 
// Class assignment of alerts.
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_64_REG_OFFSET 0x328
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_64_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_64_CLASS_A_64_MASK 0x3u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_64_CLASS_A_64_OFFSET 0
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_64_CLASS_A_64_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_64_CLASS_A_64_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_64_CLASS_A_64_OFFSET })
 
// Class assignment of alerts.
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_65_REG_OFFSET 0x32c
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_65_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_65_CLASS_A_65_MASK 0x3u
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_65_CLASS_A_65_OFFSET 0
#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_65_CLASS_A_65_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_65_CLASS_A_65_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_65_CLASS_A_65_OFFSET })
 
// Alert Cause Register (common parameters)
#define ALERT_HANDLER_ALERT_CAUSE_A_FIELD_WIDTH 1
#define ALERT_HANDLER_ALERT_CAUSE_MULTIREG_COUNT 66
 
// Alert Cause Register
#define ALERT_HANDLER_ALERT_CAUSE_0_REG_OFFSET 0x330
#define ALERT_HANDLER_ALERT_CAUSE_0_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CAUSE_0_A_0_BIT 0
 
// Alert Cause Register
#define ALERT_HANDLER_ALERT_CAUSE_1_REG_OFFSET 0x334
#define ALERT_HANDLER_ALERT_CAUSE_1_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CAUSE_1_A_1_BIT 0
 
// Alert Cause Register
#define ALERT_HANDLER_ALERT_CAUSE_2_REG_OFFSET 0x338
#define ALERT_HANDLER_ALERT_CAUSE_2_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CAUSE_2_A_2_BIT 0
 
// Alert Cause Register
#define ALERT_HANDLER_ALERT_CAUSE_3_REG_OFFSET 0x33c
#define ALERT_HANDLER_ALERT_CAUSE_3_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CAUSE_3_A_3_BIT 0
 
// Alert Cause Register
#define ALERT_HANDLER_ALERT_CAUSE_4_REG_OFFSET 0x340
#define ALERT_HANDLER_ALERT_CAUSE_4_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CAUSE_4_A_4_BIT 0
 
// Alert Cause Register
#define ALERT_HANDLER_ALERT_CAUSE_5_REG_OFFSET 0x344
#define ALERT_HANDLER_ALERT_CAUSE_5_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CAUSE_5_A_5_BIT 0
 
// Alert Cause Register
#define ALERT_HANDLER_ALERT_CAUSE_6_REG_OFFSET 0x348
#define ALERT_HANDLER_ALERT_CAUSE_6_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CAUSE_6_A_6_BIT 0
 
// Alert Cause Register
#define ALERT_HANDLER_ALERT_CAUSE_7_REG_OFFSET 0x34c
#define ALERT_HANDLER_ALERT_CAUSE_7_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CAUSE_7_A_7_BIT 0
 
// Alert Cause Register
#define ALERT_HANDLER_ALERT_CAUSE_8_REG_OFFSET 0x350
#define ALERT_HANDLER_ALERT_CAUSE_8_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CAUSE_8_A_8_BIT 0
 
// Alert Cause Register
#define ALERT_HANDLER_ALERT_CAUSE_9_REG_OFFSET 0x354
#define ALERT_HANDLER_ALERT_CAUSE_9_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CAUSE_9_A_9_BIT 0
 
// Alert Cause Register
#define ALERT_HANDLER_ALERT_CAUSE_10_REG_OFFSET 0x358
#define ALERT_HANDLER_ALERT_CAUSE_10_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CAUSE_10_A_10_BIT 0
 
// Alert Cause Register
#define ALERT_HANDLER_ALERT_CAUSE_11_REG_OFFSET 0x35c
#define ALERT_HANDLER_ALERT_CAUSE_11_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CAUSE_11_A_11_BIT 0
 
// Alert Cause Register
#define ALERT_HANDLER_ALERT_CAUSE_12_REG_OFFSET 0x360
#define ALERT_HANDLER_ALERT_CAUSE_12_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CAUSE_12_A_12_BIT 0
 
// Alert Cause Register
#define ALERT_HANDLER_ALERT_CAUSE_13_REG_OFFSET 0x364
#define ALERT_HANDLER_ALERT_CAUSE_13_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CAUSE_13_A_13_BIT 0
 
// Alert Cause Register
#define ALERT_HANDLER_ALERT_CAUSE_14_REG_OFFSET 0x368
#define ALERT_HANDLER_ALERT_CAUSE_14_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CAUSE_14_A_14_BIT 0
 
// Alert Cause Register
#define ALERT_HANDLER_ALERT_CAUSE_15_REG_OFFSET 0x36c
#define ALERT_HANDLER_ALERT_CAUSE_15_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CAUSE_15_A_15_BIT 0
 
// Alert Cause Register
#define ALERT_HANDLER_ALERT_CAUSE_16_REG_OFFSET 0x370
#define ALERT_HANDLER_ALERT_CAUSE_16_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CAUSE_16_A_16_BIT 0
 
// Alert Cause Register
#define ALERT_HANDLER_ALERT_CAUSE_17_REG_OFFSET 0x374
#define ALERT_HANDLER_ALERT_CAUSE_17_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CAUSE_17_A_17_BIT 0
 
// Alert Cause Register
#define ALERT_HANDLER_ALERT_CAUSE_18_REG_OFFSET 0x378
#define ALERT_HANDLER_ALERT_CAUSE_18_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CAUSE_18_A_18_BIT 0
 
// Alert Cause Register
#define ALERT_HANDLER_ALERT_CAUSE_19_REG_OFFSET 0x37c
#define ALERT_HANDLER_ALERT_CAUSE_19_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CAUSE_19_A_19_BIT 0
 
// Alert Cause Register
#define ALERT_HANDLER_ALERT_CAUSE_20_REG_OFFSET 0x380
#define ALERT_HANDLER_ALERT_CAUSE_20_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CAUSE_20_A_20_BIT 0
 
// Alert Cause Register
#define ALERT_HANDLER_ALERT_CAUSE_21_REG_OFFSET 0x384
#define ALERT_HANDLER_ALERT_CAUSE_21_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CAUSE_21_A_21_BIT 0
 
// Alert Cause Register
#define ALERT_HANDLER_ALERT_CAUSE_22_REG_OFFSET 0x388
#define ALERT_HANDLER_ALERT_CAUSE_22_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CAUSE_22_A_22_BIT 0
 
// Alert Cause Register
#define ALERT_HANDLER_ALERT_CAUSE_23_REG_OFFSET 0x38c
#define ALERT_HANDLER_ALERT_CAUSE_23_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CAUSE_23_A_23_BIT 0
 
// Alert Cause Register
#define ALERT_HANDLER_ALERT_CAUSE_24_REG_OFFSET 0x390
#define ALERT_HANDLER_ALERT_CAUSE_24_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CAUSE_24_A_24_BIT 0
 
// Alert Cause Register
#define ALERT_HANDLER_ALERT_CAUSE_25_REG_OFFSET 0x394
#define ALERT_HANDLER_ALERT_CAUSE_25_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CAUSE_25_A_25_BIT 0
 
// Alert Cause Register
#define ALERT_HANDLER_ALERT_CAUSE_26_REG_OFFSET 0x398
#define ALERT_HANDLER_ALERT_CAUSE_26_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CAUSE_26_A_26_BIT 0
 
// Alert Cause Register
#define ALERT_HANDLER_ALERT_CAUSE_27_REG_OFFSET 0x39c
#define ALERT_HANDLER_ALERT_CAUSE_27_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CAUSE_27_A_27_BIT 0
 
// Alert Cause Register
#define ALERT_HANDLER_ALERT_CAUSE_28_REG_OFFSET 0x3a0
#define ALERT_HANDLER_ALERT_CAUSE_28_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CAUSE_28_A_28_BIT 0
 
// Alert Cause Register
#define ALERT_HANDLER_ALERT_CAUSE_29_REG_OFFSET 0x3a4
#define ALERT_HANDLER_ALERT_CAUSE_29_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CAUSE_29_A_29_BIT 0
 
// Alert Cause Register
#define ALERT_HANDLER_ALERT_CAUSE_30_REG_OFFSET 0x3a8
#define ALERT_HANDLER_ALERT_CAUSE_30_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CAUSE_30_A_30_BIT 0
 
// Alert Cause Register
#define ALERT_HANDLER_ALERT_CAUSE_31_REG_OFFSET 0x3ac
#define ALERT_HANDLER_ALERT_CAUSE_31_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CAUSE_31_A_31_BIT 0
 
// Alert Cause Register
#define ALERT_HANDLER_ALERT_CAUSE_32_REG_OFFSET 0x3b0
#define ALERT_HANDLER_ALERT_CAUSE_32_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CAUSE_32_A_32_BIT 0
 
// Alert Cause Register
#define ALERT_HANDLER_ALERT_CAUSE_33_REG_OFFSET 0x3b4
#define ALERT_HANDLER_ALERT_CAUSE_33_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CAUSE_33_A_33_BIT 0
 
// Alert Cause Register
#define ALERT_HANDLER_ALERT_CAUSE_34_REG_OFFSET 0x3b8
#define ALERT_HANDLER_ALERT_CAUSE_34_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CAUSE_34_A_34_BIT 0
 
// Alert Cause Register
#define ALERT_HANDLER_ALERT_CAUSE_35_REG_OFFSET 0x3bc
#define ALERT_HANDLER_ALERT_CAUSE_35_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CAUSE_35_A_35_BIT 0
 
// Alert Cause Register
#define ALERT_HANDLER_ALERT_CAUSE_36_REG_OFFSET 0x3c0
#define ALERT_HANDLER_ALERT_CAUSE_36_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CAUSE_36_A_36_BIT 0
 
// Alert Cause Register
#define ALERT_HANDLER_ALERT_CAUSE_37_REG_OFFSET 0x3c4
#define ALERT_HANDLER_ALERT_CAUSE_37_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CAUSE_37_A_37_BIT 0
 
// Alert Cause Register
#define ALERT_HANDLER_ALERT_CAUSE_38_REG_OFFSET 0x3c8
#define ALERT_HANDLER_ALERT_CAUSE_38_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CAUSE_38_A_38_BIT 0
 
// Alert Cause Register
#define ALERT_HANDLER_ALERT_CAUSE_39_REG_OFFSET 0x3cc
#define ALERT_HANDLER_ALERT_CAUSE_39_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CAUSE_39_A_39_BIT 0
 
// Alert Cause Register
#define ALERT_HANDLER_ALERT_CAUSE_40_REG_OFFSET 0x3d0
#define ALERT_HANDLER_ALERT_CAUSE_40_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CAUSE_40_A_40_BIT 0
 
// Alert Cause Register
#define ALERT_HANDLER_ALERT_CAUSE_41_REG_OFFSET 0x3d4
#define ALERT_HANDLER_ALERT_CAUSE_41_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CAUSE_41_A_41_BIT 0
 
// Alert Cause Register
#define ALERT_HANDLER_ALERT_CAUSE_42_REG_OFFSET 0x3d8
#define ALERT_HANDLER_ALERT_CAUSE_42_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CAUSE_42_A_42_BIT 0
 
// Alert Cause Register
#define ALERT_HANDLER_ALERT_CAUSE_43_REG_OFFSET 0x3dc
#define ALERT_HANDLER_ALERT_CAUSE_43_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CAUSE_43_A_43_BIT 0
 
// Alert Cause Register
#define ALERT_HANDLER_ALERT_CAUSE_44_REG_OFFSET 0x3e0
#define ALERT_HANDLER_ALERT_CAUSE_44_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CAUSE_44_A_44_BIT 0
 
// Alert Cause Register
#define ALERT_HANDLER_ALERT_CAUSE_45_REG_OFFSET 0x3e4
#define ALERT_HANDLER_ALERT_CAUSE_45_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CAUSE_45_A_45_BIT 0
 
// Alert Cause Register
#define ALERT_HANDLER_ALERT_CAUSE_46_REG_OFFSET 0x3e8
#define ALERT_HANDLER_ALERT_CAUSE_46_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CAUSE_46_A_46_BIT 0
 
// Alert Cause Register
#define ALERT_HANDLER_ALERT_CAUSE_47_REG_OFFSET 0x3ec
#define ALERT_HANDLER_ALERT_CAUSE_47_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CAUSE_47_A_47_BIT 0
 
// Alert Cause Register
#define ALERT_HANDLER_ALERT_CAUSE_48_REG_OFFSET 0x3f0
#define ALERT_HANDLER_ALERT_CAUSE_48_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CAUSE_48_A_48_BIT 0
 
// Alert Cause Register
#define ALERT_HANDLER_ALERT_CAUSE_49_REG_OFFSET 0x3f4
#define ALERT_HANDLER_ALERT_CAUSE_49_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CAUSE_49_A_49_BIT 0
 
// Alert Cause Register
#define ALERT_HANDLER_ALERT_CAUSE_50_REG_OFFSET 0x3f8
#define ALERT_HANDLER_ALERT_CAUSE_50_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CAUSE_50_A_50_BIT 0
 
// Alert Cause Register
#define ALERT_HANDLER_ALERT_CAUSE_51_REG_OFFSET 0x3fc
#define ALERT_HANDLER_ALERT_CAUSE_51_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CAUSE_51_A_51_BIT 0
 
// Alert Cause Register
#define ALERT_HANDLER_ALERT_CAUSE_52_REG_OFFSET 0x400
#define ALERT_HANDLER_ALERT_CAUSE_52_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CAUSE_52_A_52_BIT 0
 
// Alert Cause Register
#define ALERT_HANDLER_ALERT_CAUSE_53_REG_OFFSET 0x404
#define ALERT_HANDLER_ALERT_CAUSE_53_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CAUSE_53_A_53_BIT 0
 
// Alert Cause Register
#define ALERT_HANDLER_ALERT_CAUSE_54_REG_OFFSET 0x408
#define ALERT_HANDLER_ALERT_CAUSE_54_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CAUSE_54_A_54_BIT 0
 
// Alert Cause Register
#define ALERT_HANDLER_ALERT_CAUSE_55_REG_OFFSET 0x40c
#define ALERT_HANDLER_ALERT_CAUSE_55_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CAUSE_55_A_55_BIT 0
 
// Alert Cause Register
#define ALERT_HANDLER_ALERT_CAUSE_56_REG_OFFSET 0x410
#define ALERT_HANDLER_ALERT_CAUSE_56_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CAUSE_56_A_56_BIT 0
 
// Alert Cause Register
#define ALERT_HANDLER_ALERT_CAUSE_57_REG_OFFSET 0x414
#define ALERT_HANDLER_ALERT_CAUSE_57_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CAUSE_57_A_57_BIT 0
 
// Alert Cause Register
#define ALERT_HANDLER_ALERT_CAUSE_58_REG_OFFSET 0x418
#define ALERT_HANDLER_ALERT_CAUSE_58_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CAUSE_58_A_58_BIT 0
 
// Alert Cause Register
#define ALERT_HANDLER_ALERT_CAUSE_59_REG_OFFSET 0x41c
#define ALERT_HANDLER_ALERT_CAUSE_59_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CAUSE_59_A_59_BIT 0
 
// Alert Cause Register
#define ALERT_HANDLER_ALERT_CAUSE_60_REG_OFFSET 0x420
#define ALERT_HANDLER_ALERT_CAUSE_60_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CAUSE_60_A_60_BIT 0
 
// Alert Cause Register
#define ALERT_HANDLER_ALERT_CAUSE_61_REG_OFFSET 0x424
#define ALERT_HANDLER_ALERT_CAUSE_61_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CAUSE_61_A_61_BIT 0
 
// Alert Cause Register
#define ALERT_HANDLER_ALERT_CAUSE_62_REG_OFFSET 0x428
#define ALERT_HANDLER_ALERT_CAUSE_62_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CAUSE_62_A_62_BIT 0
 
// Alert Cause Register
#define ALERT_HANDLER_ALERT_CAUSE_63_REG_OFFSET 0x42c
#define ALERT_HANDLER_ALERT_CAUSE_63_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CAUSE_63_A_63_BIT 0
 
// Alert Cause Register
#define ALERT_HANDLER_ALERT_CAUSE_64_REG_OFFSET 0x430
#define ALERT_HANDLER_ALERT_CAUSE_64_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CAUSE_64_A_64_BIT 0
 
// Alert Cause Register
#define ALERT_HANDLER_ALERT_CAUSE_65_REG_OFFSET 0x434
#define ALERT_HANDLER_ALERT_CAUSE_65_REG_RESVAL 0x0u
#define ALERT_HANDLER_ALERT_CAUSE_65_A_65_BIT 0
 
// Register write enable for alert enable bits. (common parameters)
#define ALERT_HANDLER_LOC_ALERT_REGWEN_EN_FIELD_WIDTH 1
#define ALERT_HANDLER_LOC_ALERT_REGWEN_MULTIREG_COUNT 7
 
// Register write enable for alert enable bits.
#define ALERT_HANDLER_LOC_ALERT_REGWEN_0_REG_OFFSET 0x438
#define ALERT_HANDLER_LOC_ALERT_REGWEN_0_REG_RESVAL 0x1u
#define ALERT_HANDLER_LOC_ALERT_REGWEN_0_EN_0_BIT 0
 
// Register write enable for alert enable bits.
#define ALERT_HANDLER_LOC_ALERT_REGWEN_1_REG_OFFSET 0x43c
#define ALERT_HANDLER_LOC_ALERT_REGWEN_1_REG_RESVAL 0x1u
#define ALERT_HANDLER_LOC_ALERT_REGWEN_1_EN_1_BIT 0
 
// Register write enable for alert enable bits.
#define ALERT_HANDLER_LOC_ALERT_REGWEN_2_REG_OFFSET 0x440
#define ALERT_HANDLER_LOC_ALERT_REGWEN_2_REG_RESVAL 0x1u
#define ALERT_HANDLER_LOC_ALERT_REGWEN_2_EN_2_BIT 0
 
// Register write enable for alert enable bits.
#define ALERT_HANDLER_LOC_ALERT_REGWEN_3_REG_OFFSET 0x444
#define ALERT_HANDLER_LOC_ALERT_REGWEN_3_REG_RESVAL 0x1u
#define ALERT_HANDLER_LOC_ALERT_REGWEN_3_EN_3_BIT 0
 
// Register write enable for alert enable bits.
#define ALERT_HANDLER_LOC_ALERT_REGWEN_4_REG_OFFSET 0x448
#define ALERT_HANDLER_LOC_ALERT_REGWEN_4_REG_RESVAL 0x1u
#define ALERT_HANDLER_LOC_ALERT_REGWEN_4_EN_4_BIT 0
 
// Register write enable for alert enable bits.
#define ALERT_HANDLER_LOC_ALERT_REGWEN_5_REG_OFFSET 0x44c
#define ALERT_HANDLER_LOC_ALERT_REGWEN_5_REG_RESVAL 0x1u
#define ALERT_HANDLER_LOC_ALERT_REGWEN_5_EN_5_BIT 0
 
// Register write enable for alert enable bits.
#define ALERT_HANDLER_LOC_ALERT_REGWEN_6_REG_OFFSET 0x450
#define ALERT_HANDLER_LOC_ALERT_REGWEN_6_REG_RESVAL 0x1u
#define ALERT_HANDLER_LOC_ALERT_REGWEN_6_EN_6_BIT 0
 
// Enable register for the local alerts
#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_EN_LA_FIELD_WIDTH 1
#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_MULTIREG_COUNT 7
 
// Enable register for the local alerts
#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0_REG_OFFSET 0x454
#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0_REG_RESVAL 0x0u
#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0_EN_LA_0_BIT 0
 
// Enable register for the local alerts
#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1_REG_OFFSET 0x458
#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1_REG_RESVAL 0x0u
#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1_EN_LA_1_BIT 0
 
// Enable register for the local alerts
#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2_REG_OFFSET 0x45c
#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2_REG_RESVAL 0x0u
#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2_EN_LA_2_BIT 0
 
// Enable register for the local alerts
#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3_REG_OFFSET 0x460
#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3_REG_RESVAL 0x0u
#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3_EN_LA_3_BIT 0
 
// Enable register for the local alerts
#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4_REG_OFFSET 0x464
#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4_REG_RESVAL 0x0u
#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4_EN_LA_4_BIT 0
 
// Enable register for the local alerts
#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5_REG_OFFSET 0x468
#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5_REG_RESVAL 0x0u
#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5_EN_LA_5_BIT 0
 
// Enable register for the local alerts
#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6_REG_OFFSET 0x46c
#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6_REG_RESVAL 0x0u
#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6_EN_LA_6_BIT 0
 
// Class assignment of the local alerts
#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_CLASS_LA_FIELD_WIDTH 2
#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_MULTIREG_COUNT 7
 
// Class assignment of the local alerts
#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_REG_OFFSET 0x470
#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_REG_RESVAL 0x0u
#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_MASK 0x3u
#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_OFFSET 0
#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_MASK, .index = ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_OFFSET })
#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_VALUE_CLASSA 0x0
#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_VALUE_CLASSB 0x1
#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_VALUE_CLASSC 0x2
#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_VALUE_CLASSD 0x3
 
// Class assignment of the local alerts
#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_REG_OFFSET 0x474
#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_REG_RESVAL 0x0u
#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_CLASS_LA_1_MASK 0x3u
#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_CLASS_LA_1_OFFSET 0
#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_CLASS_LA_1_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_CLASS_LA_1_MASK, .index = ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_CLASS_LA_1_OFFSET })
 
// Class assignment of the local alerts
#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_REG_OFFSET 0x478
#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_REG_RESVAL 0x0u
#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_CLASS_LA_2_MASK 0x3u
#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_CLASS_LA_2_OFFSET 0
#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_CLASS_LA_2_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_CLASS_LA_2_MASK, .index = ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_CLASS_LA_2_OFFSET })
 
// Class assignment of the local alerts
#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_REG_OFFSET 0x47c
#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_REG_RESVAL 0x0u
#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_CLASS_LA_3_MASK 0x3u
#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_CLASS_LA_3_OFFSET 0
#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_CLASS_LA_3_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_CLASS_LA_3_MASK, .index = ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_CLASS_LA_3_OFFSET })
 
// Class assignment of the local alerts
#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_REG_OFFSET 0x480
#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_REG_RESVAL 0x0u
#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_CLASS_LA_4_MASK 0x3u
#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_CLASS_LA_4_OFFSET 0
#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_CLASS_LA_4_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_CLASS_LA_4_MASK, .index = ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_CLASS_LA_4_OFFSET })
 
// Class assignment of the local alerts
#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_REG_OFFSET 0x484
#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_REG_RESVAL 0x0u
#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_CLASS_LA_5_MASK 0x3u
#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_CLASS_LA_5_OFFSET 0
#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_CLASS_LA_5_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_CLASS_LA_5_MASK, .index = ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_CLASS_LA_5_OFFSET })
 
// Class assignment of the local alerts
#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_REG_OFFSET 0x488
#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_REG_RESVAL 0x0u
#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_CLASS_LA_6_MASK 0x3u
#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_CLASS_LA_6_OFFSET 0
#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_CLASS_LA_6_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_CLASS_LA_6_MASK, .index = ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_CLASS_LA_6_OFFSET })
 
// Alert Cause Register for the local alerts
#define ALERT_HANDLER_LOC_ALERT_CAUSE_LA_FIELD_WIDTH 1
#define ALERT_HANDLER_LOC_ALERT_CAUSE_MULTIREG_COUNT 7
 
// Alert Cause Register for the local alerts
#define ALERT_HANDLER_LOC_ALERT_CAUSE_0_REG_OFFSET 0x48c
#define ALERT_HANDLER_LOC_ALERT_CAUSE_0_REG_RESVAL 0x0u
#define ALERT_HANDLER_LOC_ALERT_CAUSE_0_LA_0_BIT 0
 
// Alert Cause Register for the local alerts
#define ALERT_HANDLER_LOC_ALERT_CAUSE_1_REG_OFFSET 0x490
#define ALERT_HANDLER_LOC_ALERT_CAUSE_1_REG_RESVAL 0x0u
#define ALERT_HANDLER_LOC_ALERT_CAUSE_1_LA_1_BIT 0
 
// Alert Cause Register for the local alerts
#define ALERT_HANDLER_LOC_ALERT_CAUSE_2_REG_OFFSET 0x494
#define ALERT_HANDLER_LOC_ALERT_CAUSE_2_REG_RESVAL 0x0u
#define ALERT_HANDLER_LOC_ALERT_CAUSE_2_LA_2_BIT 0
 
// Alert Cause Register for the local alerts
#define ALERT_HANDLER_LOC_ALERT_CAUSE_3_REG_OFFSET 0x498
#define ALERT_HANDLER_LOC_ALERT_CAUSE_3_REG_RESVAL 0x0u
#define ALERT_HANDLER_LOC_ALERT_CAUSE_3_LA_3_BIT 0
 
// Alert Cause Register for the local alerts
#define ALERT_HANDLER_LOC_ALERT_CAUSE_4_REG_OFFSET 0x49c
#define ALERT_HANDLER_LOC_ALERT_CAUSE_4_REG_RESVAL 0x0u
#define ALERT_HANDLER_LOC_ALERT_CAUSE_4_LA_4_BIT 0
 
// Alert Cause Register for the local alerts
#define ALERT_HANDLER_LOC_ALERT_CAUSE_5_REG_OFFSET 0x4a0
#define ALERT_HANDLER_LOC_ALERT_CAUSE_5_REG_RESVAL 0x0u
#define ALERT_HANDLER_LOC_ALERT_CAUSE_5_LA_5_BIT 0
 
// Alert Cause Register for the local alerts
#define ALERT_HANDLER_LOC_ALERT_CAUSE_6_REG_OFFSET 0x4a4
#define ALERT_HANDLER_LOC_ALERT_CAUSE_6_REG_RESVAL 0x0u
#define ALERT_HANDLER_LOC_ALERT_CAUSE_6_LA_6_BIT 0
 
// Lock bit for Class A configuration.
#define ALERT_HANDLER_CLASSA_REGWEN_REG_OFFSET 0x4a8
#define ALERT_HANDLER_CLASSA_REGWEN_REG_RESVAL 0x1u
#define ALERT_HANDLER_CLASSA_REGWEN_CLASSA_REGWEN_BIT 0
 
// Escalation control register for alert Class A. Can not be modified if
// !!CLASSA_REGWEN is false.
#define ALERT_HANDLER_CLASSA_CTRL_SHADOWED_REG_OFFSET 0x4ac
#define ALERT_HANDLER_CLASSA_CTRL_SHADOWED_REG_RESVAL 0x393cu
#define ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_BIT 0
#define ALERT_HANDLER_CLASSA_CTRL_SHADOWED_LOCK_BIT 1
#define ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_E0_BIT 2
#define ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_E1_BIT 3
#define ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_E2_BIT 4
#define ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_E3_BIT 5
#define ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E0_MASK 0x3u
#define ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E0_OFFSET 6
#define ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E0_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E0_MASK, .index = ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E0_OFFSET })
#define ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E1_MASK 0x3u
#define ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E1_OFFSET 8
#define ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E1_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E1_MASK, .index = ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E1_OFFSET })
#define ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E2_MASK 0x3u
#define ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E2_OFFSET 10
#define ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E2_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E2_MASK, .index = ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E2_OFFSET })
#define ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E3_MASK 0x3u
#define ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E3_OFFSET 12
#define ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E3_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E3_MASK, .index = ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E3_OFFSET })
 
// Clear enable for escalation protocol of Class A alerts.
#define ALERT_HANDLER_CLASSA_CLR_REGWEN_REG_OFFSET 0x4b0
#define ALERT_HANDLER_CLASSA_CLR_REGWEN_REG_RESVAL 0x1u
#define ALERT_HANDLER_CLASSA_CLR_REGWEN_CLASSA_CLR_REGWEN_BIT 0
 
// Clear for escalation protocol of Class A.
#define ALERT_HANDLER_CLASSA_CLR_SHADOWED_REG_OFFSET 0x4b4
#define ALERT_HANDLER_CLASSA_CLR_SHADOWED_REG_RESVAL 0x0u
#define ALERT_HANDLER_CLASSA_CLR_SHADOWED_CLASSA_CLR_SHADOWED_BIT 0
 
// Current accumulation value for alert Class A. Software can clear this
// register
#define ALERT_HANDLER_CLASSA_ACCUM_CNT_REG_OFFSET 0x4b8
#define ALERT_HANDLER_CLASSA_ACCUM_CNT_REG_RESVAL 0x0u
#define ALERT_HANDLER_CLASSA_ACCUM_CNT_CLASSA_ACCUM_CNT_MASK 0xffffu
#define ALERT_HANDLER_CLASSA_ACCUM_CNT_CLASSA_ACCUM_CNT_OFFSET 0
#define ALERT_HANDLER_CLASSA_ACCUM_CNT_CLASSA_ACCUM_CNT_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSA_ACCUM_CNT_CLASSA_ACCUM_CNT_MASK, .index = ALERT_HANDLER_CLASSA_ACCUM_CNT_CLASSA_ACCUM_CNT_OFFSET })
 
// Accumulation threshold value for alert Class A.
#define ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_REG_OFFSET 0x4bc
#define ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_REG_RESVAL 0x0u
#define ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_CLASSA_ACCUM_THRESH_SHADOWED_MASK \
  0xffffu
#define ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_CLASSA_ACCUM_THRESH_SHADOWED_OFFSET \
  0
#define ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_CLASSA_ACCUM_THRESH_SHADOWED_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_CLASSA_ACCUM_THRESH_SHADOWED_MASK, .index = ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_CLASSA_ACCUM_THRESH_SHADOWED_OFFSET })
 
// Interrupt timeout in cycles.
#define ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED_REG_OFFSET 0x4c0
#define ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED_REG_RESVAL 0x0u
 
// Crashdump trigger configuration for Class A.
#define ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_REG_OFFSET 0x4c4
#define ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_REG_RESVAL 0x0u
#define ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_MASK \
  0x3u
#define ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_OFFSET \
  0
#define ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_MASK, .index = ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_OFFSET })
 
// Duration of escalation phase 0 for Class A.
#define ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED_REG_OFFSET 0x4c8
#define ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED_REG_RESVAL 0x0u
 
// Duration of escalation phase 1 for Class A.
#define ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED_REG_OFFSET 0x4cc
#define ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED_REG_RESVAL 0x0u
 
// Duration of escalation phase 2 for Class A.
#define ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED_REG_OFFSET 0x4d0
#define ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED_REG_RESVAL 0x0u
 
// Duration of escalation phase 3 for Class A.
#define ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED_REG_OFFSET 0x4d4
#define ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED_REG_RESVAL 0x0u
 
// Escalation counter in cycles for Class A.
#define ALERT_HANDLER_CLASSA_ESC_CNT_REG_OFFSET 0x4d8
#define ALERT_HANDLER_CLASSA_ESC_CNT_REG_RESVAL 0x0u
 
// Current escalation state of Class A. See also !!CLASSA_ESC_CNT.
#define ALERT_HANDLER_CLASSA_STATE_REG_OFFSET 0x4dc
#define ALERT_HANDLER_CLASSA_STATE_REG_RESVAL 0x0u
#define ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_MASK 0x7u
#define ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_OFFSET 0
#define ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_MASK, .index = ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_OFFSET })
#define ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_VALUE_IDLE 0x0
#define ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_VALUE_TIMEOUT 0x1
#define ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_VALUE_FSMERROR 0x2
#define ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_VALUE_TERMINAL 0x3
#define ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_VALUE_PHASE0 0x4
#define ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_VALUE_PHASE1 0x5
#define ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_VALUE_PHASE2 0x6
#define ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_VALUE_PHASE3 0x7
 
// Lock bit for Class B configuration.
#define ALERT_HANDLER_CLASSB_REGWEN_REG_OFFSET 0x4e0
#define ALERT_HANDLER_CLASSB_REGWEN_REG_RESVAL 0x1u
#define ALERT_HANDLER_CLASSB_REGWEN_CLASSB_REGWEN_BIT 0
 
// Escalation control register for alert Class B. Can not be modified if
// !!CLASSB_REGWEN is false.
#define ALERT_HANDLER_CLASSB_CTRL_SHADOWED_REG_OFFSET 0x4e4
#define ALERT_HANDLER_CLASSB_CTRL_SHADOWED_REG_RESVAL 0x393cu
#define ALERT_HANDLER_CLASSB_CTRL_SHADOWED_EN_BIT 0
#define ALERT_HANDLER_CLASSB_CTRL_SHADOWED_LOCK_BIT 1
#define ALERT_HANDLER_CLASSB_CTRL_SHADOWED_EN_E0_BIT 2
#define ALERT_HANDLER_CLASSB_CTRL_SHADOWED_EN_E1_BIT 3
#define ALERT_HANDLER_CLASSB_CTRL_SHADOWED_EN_E2_BIT 4
#define ALERT_HANDLER_CLASSB_CTRL_SHADOWED_EN_E3_BIT 5
#define ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E0_MASK 0x3u
#define ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E0_OFFSET 6
#define ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E0_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E0_MASK, .index = ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E0_OFFSET })
#define ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E1_MASK 0x3u
#define ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E1_OFFSET 8
#define ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E1_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E1_MASK, .index = ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E1_OFFSET })
#define ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E2_MASK 0x3u
#define ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E2_OFFSET 10
#define ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E2_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E2_MASK, .index = ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E2_OFFSET })
#define ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E3_MASK 0x3u
#define ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E3_OFFSET 12
#define ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E3_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E3_MASK, .index = ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E3_OFFSET })
 
// Clear enable for escalation protocol of Class B alerts.
#define ALERT_HANDLER_CLASSB_CLR_REGWEN_REG_OFFSET 0x4e8
#define ALERT_HANDLER_CLASSB_CLR_REGWEN_REG_RESVAL 0x1u
#define ALERT_HANDLER_CLASSB_CLR_REGWEN_CLASSB_CLR_REGWEN_BIT 0
 
// Clear for escalation protocol of Class B.
#define ALERT_HANDLER_CLASSB_CLR_SHADOWED_REG_OFFSET 0x4ec
#define ALERT_HANDLER_CLASSB_CLR_SHADOWED_REG_RESVAL 0x0u
#define ALERT_HANDLER_CLASSB_CLR_SHADOWED_CLASSB_CLR_SHADOWED_BIT 0
 
// Current accumulation value for alert Class B. Software can clear this
// register
#define ALERT_HANDLER_CLASSB_ACCUM_CNT_REG_OFFSET 0x4f0
#define ALERT_HANDLER_CLASSB_ACCUM_CNT_REG_RESVAL 0x0u
#define ALERT_HANDLER_CLASSB_ACCUM_CNT_CLASSB_ACCUM_CNT_MASK 0xffffu
#define ALERT_HANDLER_CLASSB_ACCUM_CNT_CLASSB_ACCUM_CNT_OFFSET 0
#define ALERT_HANDLER_CLASSB_ACCUM_CNT_CLASSB_ACCUM_CNT_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSB_ACCUM_CNT_CLASSB_ACCUM_CNT_MASK, .index = ALERT_HANDLER_CLASSB_ACCUM_CNT_CLASSB_ACCUM_CNT_OFFSET })
 
// Accumulation threshold value for alert Class B.
#define ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_REG_OFFSET 0x4f4
#define ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_REG_RESVAL 0x0u
#define ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_CLASSB_ACCUM_THRESH_SHADOWED_MASK \
  0xffffu
#define ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_CLASSB_ACCUM_THRESH_SHADOWED_OFFSET \
  0
#define ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_CLASSB_ACCUM_THRESH_SHADOWED_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_CLASSB_ACCUM_THRESH_SHADOWED_MASK, .index = ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_CLASSB_ACCUM_THRESH_SHADOWED_OFFSET })
 
// Interrupt timeout in cycles.
#define ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED_REG_OFFSET 0x4f8
#define ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED_REG_RESVAL 0x0u
 
// Crashdump trigger configuration for Class B.
#define ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_REG_OFFSET 0x4fc
#define ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_REG_RESVAL 0x0u
#define ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_MASK \
  0x3u
#define ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_OFFSET \
  0
#define ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_MASK, .index = ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_OFFSET })
 
// Duration of escalation phase 0 for Class B.
#define ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED_REG_OFFSET 0x500
#define ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED_REG_RESVAL 0x0u
 
// Duration of escalation phase 1 for Class B.
#define ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED_REG_OFFSET 0x504
#define ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED_REG_RESVAL 0x0u
 
// Duration of escalation phase 2 for Class B.
#define ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED_REG_OFFSET 0x508
#define ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED_REG_RESVAL 0x0u
 
// Duration of escalation phase 3 for Class B.
#define ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED_REG_OFFSET 0x50c
#define ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED_REG_RESVAL 0x0u
 
// Escalation counter in cycles for Class B.
#define ALERT_HANDLER_CLASSB_ESC_CNT_REG_OFFSET 0x510
#define ALERT_HANDLER_CLASSB_ESC_CNT_REG_RESVAL 0x0u
 
// Current escalation state of Class B. See also !!CLASSB_ESC_CNT.
#define ALERT_HANDLER_CLASSB_STATE_REG_OFFSET 0x514
#define ALERT_HANDLER_CLASSB_STATE_REG_RESVAL 0x0u
#define ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_MASK 0x7u
#define ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_OFFSET 0
#define ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_MASK, .index = ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_OFFSET })
#define ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_VALUE_IDLE 0x0
#define ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_VALUE_TIMEOUT 0x1
#define ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_VALUE_FSMERROR 0x2
#define ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_VALUE_TERMINAL 0x3
#define ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_VALUE_PHASE0 0x4
#define ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_VALUE_PHASE1 0x5
#define ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_VALUE_PHASE2 0x6
#define ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_VALUE_PHASE3 0x7
 
// Lock bit for Class C configuration.
#define ALERT_HANDLER_CLASSC_REGWEN_REG_OFFSET 0x518
#define ALERT_HANDLER_CLASSC_REGWEN_REG_RESVAL 0x1u
#define ALERT_HANDLER_CLASSC_REGWEN_CLASSC_REGWEN_BIT 0
 
// Escalation control register for alert Class C. Can not be modified if
// !!CLASSC_REGWEN is false.
#define ALERT_HANDLER_CLASSC_CTRL_SHADOWED_REG_OFFSET 0x51c
#define ALERT_HANDLER_CLASSC_CTRL_SHADOWED_REG_RESVAL 0x393cu
#define ALERT_HANDLER_CLASSC_CTRL_SHADOWED_EN_BIT 0
#define ALERT_HANDLER_CLASSC_CTRL_SHADOWED_LOCK_BIT 1
#define ALERT_HANDLER_CLASSC_CTRL_SHADOWED_EN_E0_BIT 2
#define ALERT_HANDLER_CLASSC_CTRL_SHADOWED_EN_E1_BIT 3
#define ALERT_HANDLER_CLASSC_CTRL_SHADOWED_EN_E2_BIT 4
#define ALERT_HANDLER_CLASSC_CTRL_SHADOWED_EN_E3_BIT 5
#define ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E0_MASK 0x3u
#define ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E0_OFFSET 6
#define ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E0_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E0_MASK, .index = ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E0_OFFSET })
#define ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E1_MASK 0x3u
#define ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E1_OFFSET 8
#define ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E1_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E1_MASK, .index = ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E1_OFFSET })
#define ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E2_MASK 0x3u
#define ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E2_OFFSET 10
#define ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E2_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E2_MASK, .index = ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E2_OFFSET })
#define ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E3_MASK 0x3u
#define ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E3_OFFSET 12
#define ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E3_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E3_MASK, .index = ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E3_OFFSET })
 
// Clear enable for escalation protocol of Class C alerts.
#define ALERT_HANDLER_CLASSC_CLR_REGWEN_REG_OFFSET 0x520
#define ALERT_HANDLER_CLASSC_CLR_REGWEN_REG_RESVAL 0x1u
#define ALERT_HANDLER_CLASSC_CLR_REGWEN_CLASSC_CLR_REGWEN_BIT 0
 
// Clear for escalation protocol of Class C.
#define ALERT_HANDLER_CLASSC_CLR_SHADOWED_REG_OFFSET 0x524
#define ALERT_HANDLER_CLASSC_CLR_SHADOWED_REG_RESVAL 0x0u
#define ALERT_HANDLER_CLASSC_CLR_SHADOWED_CLASSC_CLR_SHADOWED_BIT 0
 
// Current accumulation value for alert Class C. Software can clear this
// register
#define ALERT_HANDLER_CLASSC_ACCUM_CNT_REG_OFFSET 0x528
#define ALERT_HANDLER_CLASSC_ACCUM_CNT_REG_RESVAL 0x0u
#define ALERT_HANDLER_CLASSC_ACCUM_CNT_CLASSC_ACCUM_CNT_MASK 0xffffu
#define ALERT_HANDLER_CLASSC_ACCUM_CNT_CLASSC_ACCUM_CNT_OFFSET 0
#define ALERT_HANDLER_CLASSC_ACCUM_CNT_CLASSC_ACCUM_CNT_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSC_ACCUM_CNT_CLASSC_ACCUM_CNT_MASK, .index = ALERT_HANDLER_CLASSC_ACCUM_CNT_CLASSC_ACCUM_CNT_OFFSET })
 
// Accumulation threshold value for alert Class C.
#define ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_REG_OFFSET 0x52c
#define ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_REG_RESVAL 0x0u
#define ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_CLASSC_ACCUM_THRESH_SHADOWED_MASK \
  0xffffu
#define ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_CLASSC_ACCUM_THRESH_SHADOWED_OFFSET \
  0
#define ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_CLASSC_ACCUM_THRESH_SHADOWED_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_CLASSC_ACCUM_THRESH_SHADOWED_MASK, .index = ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_CLASSC_ACCUM_THRESH_SHADOWED_OFFSET })
 
// Interrupt timeout in cycles.
#define ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED_REG_OFFSET 0x530
#define ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED_REG_RESVAL 0x0u
 
// Crashdump trigger configuration for Class C.
#define ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_REG_OFFSET 0x534
#define ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_REG_RESVAL 0x0u
#define ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_MASK \
  0x3u
#define ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_OFFSET \
  0
#define ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_MASK, .index = ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_OFFSET })
 
// Duration of escalation phase 0 for Class C.
#define ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED_REG_OFFSET 0x538
#define ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED_REG_RESVAL 0x0u
 
// Duration of escalation phase 1 for Class C.
#define ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED_REG_OFFSET 0x53c
#define ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED_REG_RESVAL 0x0u
 
// Duration of escalation phase 2 for Class C.
#define ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED_REG_OFFSET 0x540
#define ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED_REG_RESVAL 0x0u
 
// Duration of escalation phase 3 for Class C.
#define ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED_REG_OFFSET 0x544
#define ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED_REG_RESVAL 0x0u
 
// Escalation counter in cycles for Class C.
#define ALERT_HANDLER_CLASSC_ESC_CNT_REG_OFFSET 0x548
#define ALERT_HANDLER_CLASSC_ESC_CNT_REG_RESVAL 0x0u
 
// Current escalation state of Class C. See also !!CLASSC_ESC_CNT.
#define ALERT_HANDLER_CLASSC_STATE_REG_OFFSET 0x54c
#define ALERT_HANDLER_CLASSC_STATE_REG_RESVAL 0x0u
#define ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_MASK 0x7u
#define ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_OFFSET 0
#define ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_MASK, .index = ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_OFFSET })
#define ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_VALUE_IDLE 0x0
#define ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_VALUE_TIMEOUT 0x1
#define ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_VALUE_FSMERROR 0x2
#define ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_VALUE_TERMINAL 0x3
#define ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_VALUE_PHASE0 0x4
#define ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_VALUE_PHASE1 0x5
#define ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_VALUE_PHASE2 0x6
#define ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_VALUE_PHASE3 0x7
 
// Lock bit for Class D configuration.
#define ALERT_HANDLER_CLASSD_REGWEN_REG_OFFSET 0x550
#define ALERT_HANDLER_CLASSD_REGWEN_REG_RESVAL 0x1u
#define ALERT_HANDLER_CLASSD_REGWEN_CLASSD_REGWEN_BIT 0
 
// Escalation control register for alert Class D. Can not be modified if
// !!CLASSD_REGWEN is false.
#define ALERT_HANDLER_CLASSD_CTRL_SHADOWED_REG_OFFSET 0x554
#define ALERT_HANDLER_CLASSD_CTRL_SHADOWED_REG_RESVAL 0x393cu
#define ALERT_HANDLER_CLASSD_CTRL_SHADOWED_EN_BIT 0
#define ALERT_HANDLER_CLASSD_CTRL_SHADOWED_LOCK_BIT 1
#define ALERT_HANDLER_CLASSD_CTRL_SHADOWED_EN_E0_BIT 2
#define ALERT_HANDLER_CLASSD_CTRL_SHADOWED_EN_E1_BIT 3
#define ALERT_HANDLER_CLASSD_CTRL_SHADOWED_EN_E2_BIT 4
#define ALERT_HANDLER_CLASSD_CTRL_SHADOWED_EN_E3_BIT 5
#define ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E0_MASK 0x3u
#define ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E0_OFFSET 6
#define ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E0_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E0_MASK, .index = ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E0_OFFSET })
#define ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E1_MASK 0x3u
#define ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E1_OFFSET 8
#define ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E1_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E1_MASK, .index = ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E1_OFFSET })
#define ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E2_MASK 0x3u
#define ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E2_OFFSET 10
#define ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E2_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E2_MASK, .index = ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E2_OFFSET })
#define ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E3_MASK 0x3u
#define ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E3_OFFSET 12
#define ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E3_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E3_MASK, .index = ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E3_OFFSET })
 
// Clear enable for escalation protocol of Class D alerts.
#define ALERT_HANDLER_CLASSD_CLR_REGWEN_REG_OFFSET 0x558
#define ALERT_HANDLER_CLASSD_CLR_REGWEN_REG_RESVAL 0x1u
#define ALERT_HANDLER_CLASSD_CLR_REGWEN_CLASSD_CLR_REGWEN_BIT 0
 
// Clear for escalation protocol of Class D.
#define ALERT_HANDLER_CLASSD_CLR_SHADOWED_REG_OFFSET 0x55c
#define ALERT_HANDLER_CLASSD_CLR_SHADOWED_REG_RESVAL 0x0u
#define ALERT_HANDLER_CLASSD_CLR_SHADOWED_CLASSD_CLR_SHADOWED_BIT 0
 
// Current accumulation value for alert Class D. Software can clear this
// register
#define ALERT_HANDLER_CLASSD_ACCUM_CNT_REG_OFFSET 0x560
#define ALERT_HANDLER_CLASSD_ACCUM_CNT_REG_RESVAL 0x0u
#define ALERT_HANDLER_CLASSD_ACCUM_CNT_CLASSD_ACCUM_CNT_MASK 0xffffu
#define ALERT_HANDLER_CLASSD_ACCUM_CNT_CLASSD_ACCUM_CNT_OFFSET 0
#define ALERT_HANDLER_CLASSD_ACCUM_CNT_CLASSD_ACCUM_CNT_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSD_ACCUM_CNT_CLASSD_ACCUM_CNT_MASK, .index = ALERT_HANDLER_CLASSD_ACCUM_CNT_CLASSD_ACCUM_CNT_OFFSET })
 
// Accumulation threshold value for alert Class D.
#define ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_REG_OFFSET 0x564
#define ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_REG_RESVAL 0x0u
#define ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_CLASSD_ACCUM_THRESH_SHADOWED_MASK \
  0xffffu
#define ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_CLASSD_ACCUM_THRESH_SHADOWED_OFFSET \
  0
#define ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_CLASSD_ACCUM_THRESH_SHADOWED_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_CLASSD_ACCUM_THRESH_SHADOWED_MASK, .index = ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_CLASSD_ACCUM_THRESH_SHADOWED_OFFSET })
 
// Interrupt timeout in cycles.
#define ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED_REG_OFFSET 0x568
#define ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED_REG_RESVAL 0x0u
 
// Crashdump trigger configuration for Class D.
#define ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_REG_OFFSET 0x56c
#define ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_REG_RESVAL 0x0u
#define ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_MASK \
  0x3u
#define ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_OFFSET \
  0
#define ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_MASK, .index = ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_OFFSET })
 
// Duration of escalation phase 0 for Class D.
#define ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED_REG_OFFSET 0x570
#define ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED_REG_RESVAL 0x0u
 
// Duration of escalation phase 1 for Class D.
#define ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED_REG_OFFSET 0x574
#define ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED_REG_RESVAL 0x0u
 
// Duration of escalation phase 2 for Class D.
#define ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED_REG_OFFSET 0x578
#define ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED_REG_RESVAL 0x0u
 
// Duration of escalation phase 3 for Class D.
#define ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED_REG_OFFSET 0x57c
#define ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED_REG_RESVAL 0x0u
 
// Escalation counter in cycles for Class D.
#define ALERT_HANDLER_CLASSD_ESC_CNT_REG_OFFSET 0x580
#define ALERT_HANDLER_CLASSD_ESC_CNT_REG_RESVAL 0x0u
 
// Current escalation state of Class D. See also !!CLASSD_ESC_CNT.
#define ALERT_HANDLER_CLASSD_STATE_REG_OFFSET 0x584
#define ALERT_HANDLER_CLASSD_STATE_REG_RESVAL 0x0u
#define ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_MASK 0x7u
#define ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_OFFSET 0
#define ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_FIELD \
  ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_MASK, .index = ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_OFFSET })
#define ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_VALUE_IDLE 0x0
#define ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_VALUE_TIMEOUT 0x1
#define ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_VALUE_FSMERROR 0x2
#define ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_VALUE_TERMINAL 0x3
#define ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_VALUE_PHASE0 0x4
#define ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_VALUE_PHASE1 0x5
#define ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_VALUE_PHASE2 0x6
#define ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_VALUE_PHASE3 0x7
 
#ifdef __cplusplus
}  // extern "C"
#endif
#endif  // _ALERT_HANDLER_REG_DEFS_
// End generated register defines for alert_handler