otp_macro_regs.h

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/**
 * @file
 * @brief Generated register defines for otp_macro
 */
 
// Copyright information found in source file:
// Copyright lowRISC contributors (OpenTitan project).
 
// Licensing information found in source file:
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
 
#ifndef _OTP_MACRO_REG_DEFS_
#define _OTP_MACRO_REG_DEFS_
 
#ifdef __cplusplus
extern "C" {
#endif
// Register width
#define OTP_MACRO_PARAM_REG_WIDTH 32
 
 
#define OTP_MACRO_CSR0_REG_OFFSET 0x0
#define OTP_MACRO_CSR0_REG_RESVAL 0x0u
#define OTP_MACRO_CSR0_FIELD0_BIT 0
#define OTP_MACRO_CSR0_FIELD1_BIT 1
#define OTP_MACRO_CSR0_FIELD2_BIT 2
#define OTP_MACRO_CSR0_FIELD3_MASK 0x3ffu
#define OTP_MACRO_CSR0_FIELD3_OFFSET 4
#define OTP_MACRO_CSR0_FIELD3_FIELD \
  ((bitfield_field32_t) { .mask = OTP_MACRO_CSR0_FIELD3_MASK, .index = OTP_MACRO_CSR0_FIELD3_OFFSET })
#define OTP_MACRO_CSR0_FIELD4_MASK 0x7ffu
#define OTP_MACRO_CSR0_FIELD4_OFFSET 16
#define OTP_MACRO_CSR0_FIELD4_FIELD \
  ((bitfield_field32_t) { .mask = OTP_MACRO_CSR0_FIELD4_MASK, .index = OTP_MACRO_CSR0_FIELD4_OFFSET })
 
 
#define OTP_MACRO_CSR1_REG_OFFSET 0x4
#define OTP_MACRO_CSR1_REG_RESVAL 0x0u
#define OTP_MACRO_CSR1_FIELD0_MASK 0x7fu
#define OTP_MACRO_CSR1_FIELD0_OFFSET 0
#define OTP_MACRO_CSR1_FIELD0_FIELD \
  ((bitfield_field32_t) { .mask = OTP_MACRO_CSR1_FIELD0_MASK, .index = OTP_MACRO_CSR1_FIELD0_OFFSET })
#define OTP_MACRO_CSR1_FIELD1_BIT 7
#define OTP_MACRO_CSR1_FIELD2_MASK 0x7fu
#define OTP_MACRO_CSR1_FIELD2_OFFSET 8
#define OTP_MACRO_CSR1_FIELD2_FIELD \
  ((bitfield_field32_t) { .mask = OTP_MACRO_CSR1_FIELD2_MASK, .index = OTP_MACRO_CSR1_FIELD2_OFFSET })
#define OTP_MACRO_CSR1_FIELD3_BIT 15
#define OTP_MACRO_CSR1_FIELD4_MASK 0xffffu
#define OTP_MACRO_CSR1_FIELD4_OFFSET 16
#define OTP_MACRO_CSR1_FIELD4_FIELD \
  ((bitfield_field32_t) { .mask = OTP_MACRO_CSR1_FIELD4_MASK, .index = OTP_MACRO_CSR1_FIELD4_OFFSET })
 
 
#define OTP_MACRO_CSR2_REG_OFFSET 0x8
#define OTP_MACRO_CSR2_REG_RESVAL 0x0u
#define OTP_MACRO_CSR2_FIELD0_BIT 0
 
 
#define OTP_MACRO_CSR3_REG_OFFSET 0xc
#define OTP_MACRO_CSR3_REG_RESVAL 0x0u
#define OTP_MACRO_CSR3_FIELD0_MASK 0x7u
#define OTP_MACRO_CSR3_FIELD0_OFFSET 0
#define OTP_MACRO_CSR3_FIELD0_FIELD \
  ((bitfield_field32_t) { .mask = OTP_MACRO_CSR3_FIELD0_MASK, .index = OTP_MACRO_CSR3_FIELD0_OFFSET })
#define OTP_MACRO_CSR3_FIELD1_MASK 0x3ffu
#define OTP_MACRO_CSR3_FIELD1_OFFSET 4
#define OTP_MACRO_CSR3_FIELD1_FIELD \
  ((bitfield_field32_t) { .mask = OTP_MACRO_CSR3_FIELD1_MASK, .index = OTP_MACRO_CSR3_FIELD1_OFFSET })
#define OTP_MACRO_CSR3_FIELD2_BIT 16
#define OTP_MACRO_CSR3_FIELD3_BIT 17
#define OTP_MACRO_CSR3_FIELD4_BIT 18
#define OTP_MACRO_CSR3_FIELD5_BIT 19
#define OTP_MACRO_CSR3_FIELD6_BIT 20
#define OTP_MACRO_CSR3_FIELD7_BIT 21
#define OTP_MACRO_CSR3_FIELD8_BIT 22
 
 
#define OTP_MACRO_CSR4_REG_OFFSET 0x10
#define OTP_MACRO_CSR4_REG_RESVAL 0x0u
#define OTP_MACRO_CSR4_FIELD0_MASK 0x3ffu
#define OTP_MACRO_CSR4_FIELD0_OFFSET 0
#define OTP_MACRO_CSR4_FIELD0_FIELD \
  ((bitfield_field32_t) { .mask = OTP_MACRO_CSR4_FIELD0_MASK, .index = OTP_MACRO_CSR4_FIELD0_OFFSET })
#define OTP_MACRO_CSR4_FIELD1_BIT 12
#define OTP_MACRO_CSR4_FIELD2_BIT 13
#define OTP_MACRO_CSR4_FIELD3_BIT 14
 
 
#define OTP_MACRO_CSR5_REG_OFFSET 0x14
#define OTP_MACRO_CSR5_REG_RESVAL 0x0u
#define OTP_MACRO_CSR5_FIELD0_MASK 0x3fu
#define OTP_MACRO_CSR5_FIELD0_OFFSET 0
#define OTP_MACRO_CSR5_FIELD0_FIELD \
  ((bitfield_field32_t) { .mask = OTP_MACRO_CSR5_FIELD0_MASK, .index = OTP_MACRO_CSR5_FIELD0_OFFSET })
#define OTP_MACRO_CSR5_FIELD1_MASK 0x3u
#define OTP_MACRO_CSR5_FIELD1_OFFSET 6
#define OTP_MACRO_CSR5_FIELD1_FIELD \
  ((bitfield_field32_t) { .mask = OTP_MACRO_CSR5_FIELD1_MASK, .index = OTP_MACRO_CSR5_FIELD1_OFFSET })
#define OTP_MACRO_CSR5_FIELD2_BIT 8
#define OTP_MACRO_CSR5_FIELD3_MASK 0x7u
#define OTP_MACRO_CSR5_FIELD3_OFFSET 9
#define OTP_MACRO_CSR5_FIELD3_FIELD \
  ((bitfield_field32_t) { .mask = OTP_MACRO_CSR5_FIELD3_MASK, .index = OTP_MACRO_CSR5_FIELD3_OFFSET })
#define OTP_MACRO_CSR5_FIELD4_BIT 12
#define OTP_MACRO_CSR5_FIELD5_BIT 13
#define OTP_MACRO_CSR5_FIELD6_MASK 0xffffu
#define OTP_MACRO_CSR5_FIELD6_OFFSET 16
#define OTP_MACRO_CSR5_FIELD6_FIELD \
  ((bitfield_field32_t) { .mask = OTP_MACRO_CSR5_FIELD6_MASK, .index = OTP_MACRO_CSR5_FIELD6_OFFSET })
 
 
#define OTP_MACRO_CSR6_REG_OFFSET 0x18
#define OTP_MACRO_CSR6_REG_RESVAL 0x0u
#define OTP_MACRO_CSR6_FIELD0_MASK 0x3ffu
#define OTP_MACRO_CSR6_FIELD0_OFFSET 0
#define OTP_MACRO_CSR6_FIELD0_FIELD \
  ((bitfield_field32_t) { .mask = OTP_MACRO_CSR6_FIELD0_MASK, .index = OTP_MACRO_CSR6_FIELD0_OFFSET })
#define OTP_MACRO_CSR6_FIELD1_BIT 11
#define OTP_MACRO_CSR6_FIELD2_BIT 12
#define OTP_MACRO_CSR6_FIELD3_MASK 0xffffu
#define OTP_MACRO_CSR6_FIELD3_OFFSET 16
#define OTP_MACRO_CSR6_FIELD3_FIELD \
  ((bitfield_field32_t) { .mask = OTP_MACRO_CSR6_FIELD3_MASK, .index = OTP_MACRO_CSR6_FIELD3_OFFSET })
 
 
#define OTP_MACRO_CSR7_REG_OFFSET 0x1c
#define OTP_MACRO_CSR7_REG_RESVAL 0x0u
#define OTP_MACRO_CSR7_FIELD0_MASK 0x3fu
#define OTP_MACRO_CSR7_FIELD0_OFFSET 0
#define OTP_MACRO_CSR7_FIELD0_FIELD \
  ((bitfield_field32_t) { .mask = OTP_MACRO_CSR7_FIELD0_MASK, .index = OTP_MACRO_CSR7_FIELD0_OFFSET })
#define OTP_MACRO_CSR7_FIELD1_MASK 0x7u
#define OTP_MACRO_CSR7_FIELD1_OFFSET 8
#define OTP_MACRO_CSR7_FIELD1_FIELD \
  ((bitfield_field32_t) { .mask = OTP_MACRO_CSR7_FIELD1_MASK, .index = OTP_MACRO_CSR7_FIELD1_OFFSET })
#define OTP_MACRO_CSR7_FIELD2_BIT 14
#define OTP_MACRO_CSR7_FIELD3_BIT 15
 
#ifdef __cplusplus
}  // extern "C"
#endif
#endif  // _OTP_MACRO_REG_DEFS_
// End generated register defines for otp_macro