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13#ifndef _OTP_CTRL_REG_DEFS_
14#define _OTP_CTRL_REG_DEFS_
20#define OTP_CTRL_PARAM_NUM_SRAM_KEY_REQ_SLOTS 4
23#define OTP_CTRL_PARAM_OTP_DEPTH 8192
26#define OTP_CTRL_PARAM_OTP_WIDTH 2
29#define OTP_CTRL_PARAM_OTP_SIZE_WIDTH 2
32#define OTP_CTRL_PARAM_OTP_BYTE_ADDR_WIDTH 14
35#define OTP_CTRL_PARAM_NUM_ERROR_ENTRIES 24
38#define OTP_CTRL_PARAM_NUM_DAI_WORDS 2
41#define OTP_CTRL_PARAM_NUM_DIGEST_WORDS 2
45#define OTP_CTRL_PARAM_NUM_SW_CFG_WINDOW_WORDS 4096
48#define OTP_CTRL_PARAM_NUM_PART 22
51#define OTP_CTRL_PARAM_NUM_PART_UNBUF 15
54#define OTP_CTRL_PARAM_NUM_PART_BUF 7
57#define OTP_CTRL_PARAM_VENDOR_TEST_OFFSET 0
60#define OTP_CTRL_PARAM_VENDOR_TEST_SIZE 64
63#define OTP_CTRL_PARAM_SCRATCH_OFFSET 0
66#define OTP_CTRL_PARAM_SCRATCH_SIZE 56
69#define OTP_CTRL_PARAM_VENDOR_TEST_DIGEST_OFFSET 56
72#define OTP_CTRL_PARAM_VENDOR_TEST_DIGEST_SIZE 8
75#define OTP_CTRL_PARAM_CREATOR_SW_CFG_OFFSET 64
78#define OTP_CTRL_PARAM_CREATOR_SW_CFG_SIZE 304
81#define OTP_CTRL_PARAM_CREATOR_SW_CFG_AST_CFG_OFFSET 64
84#define OTP_CTRL_PARAM_CREATOR_SW_CFG_AST_CFG_SIZE 124
87#define OTP_CTRL_PARAM_CREATOR_SW_CFG_AST_INIT_EN_OFFSET 188
90#define OTP_CTRL_PARAM_CREATOR_SW_CFG_AST_INIT_EN_SIZE 4
93#define OTP_CTRL_PARAM_CREATOR_SW_CFG_OVERRIDES_OFFSET 192
96#define OTP_CTRL_PARAM_CREATOR_SW_CFG_OVERRIDES_SIZE 32
99#define OTP_CTRL_PARAM_CREATOR_SW_CFG_ROM_EXT_SKU_OFFSET 224
102#define OTP_CTRL_PARAM_CREATOR_SW_CFG_ROM_EXT_SKU_SIZE 4
105#define OTP_CTRL_PARAM_CREATOR_SW_CFG_SIGVERIFY_RSA_MOD_EXP_IBEX_EN_OFFSET 228
108#define OTP_CTRL_PARAM_CREATOR_SW_CFG_SIGVERIFY_RSA_MOD_EXP_IBEX_EN_SIZE 4
111#define OTP_CTRL_PARAM_CREATOR_SW_CFG_SIGVERIFY_RSA_KEY_EN_OFFSET 232
114#define OTP_CTRL_PARAM_CREATOR_SW_CFG_SIGVERIFY_RSA_KEY_EN_SIZE 8
117#define OTP_CTRL_PARAM_CREATOR_SW_CFG_SIGVERIFY_SPX_EN_OFFSET 240
120#define OTP_CTRL_PARAM_CREATOR_SW_CFG_SIGVERIFY_SPX_EN_SIZE 4
123#define OTP_CTRL_PARAM_CREATOR_SW_CFG_SIGVERIFY_SPX_KEY_EN_OFFSET 244
126#define OTP_CTRL_PARAM_CREATOR_SW_CFG_SIGVERIFY_SPX_KEY_EN_SIZE 8
129#define OTP_CTRL_PARAM_CREATOR_SW_CFG_FLASH_DATA_DEFAULT_CFG_OFFSET 252
132#define OTP_CTRL_PARAM_CREATOR_SW_CFG_FLASH_DATA_DEFAULT_CFG_SIZE 4
135#define OTP_CTRL_PARAM_CREATOR_SW_CFG_FLASH_INFO_BOOT_DATA_CFG_OFFSET 256
138#define OTP_CTRL_PARAM_CREATOR_SW_CFG_FLASH_INFO_BOOT_DATA_CFG_SIZE 4
141#define OTP_CTRL_PARAM_CREATOR_SW_CFG_FLASH_HW_INFO_CFG_OVERRIDE_OFFSET 260
144#define OTP_CTRL_PARAM_CREATOR_SW_CFG_FLASH_HW_INFO_CFG_OVERRIDE_SIZE 4
147#define OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_EN_OFFSET 264
150#define OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_EN_SIZE 4
153#define OTP_CTRL_PARAM_CREATOR_SW_CFG_JITTER_EN_OFFSET 268
156#define OTP_CTRL_PARAM_CREATOR_SW_CFG_JITTER_EN_SIZE 4
159#define OTP_CTRL_PARAM_CREATOR_SW_CFG_RET_RAM_RESET_MASK_OFFSET 272
162#define OTP_CTRL_PARAM_CREATOR_SW_CFG_RET_RAM_RESET_MASK_SIZE 4
165#define OTP_CTRL_PARAM_CREATOR_SW_CFG_MANUF_STATE_OFFSET 276
168#define OTP_CTRL_PARAM_CREATOR_SW_CFG_MANUF_STATE_SIZE 4
171#define OTP_CTRL_PARAM_CREATOR_SW_CFG_ROM_EXEC_EN_OFFSET 280
174#define OTP_CTRL_PARAM_CREATOR_SW_CFG_ROM_EXEC_EN_SIZE 4
177#define OTP_CTRL_PARAM_CREATOR_SW_CFG_CPUCTRL_OFFSET 284
180#define OTP_CTRL_PARAM_CREATOR_SW_CFG_CPUCTRL_SIZE 4
183#define OTP_CTRL_PARAM_CREATOR_SW_CFG_MIN_SEC_VER_ROM_EXT_OFFSET 288
186#define OTP_CTRL_PARAM_CREATOR_SW_CFG_MIN_SEC_VER_ROM_EXT_SIZE 4
189#define OTP_CTRL_PARAM_CREATOR_SW_CFG_MIN_SEC_VER_BL0_OFFSET 292
192#define OTP_CTRL_PARAM_CREATOR_SW_CFG_MIN_SEC_VER_BL0_SIZE 4
195#define OTP_CTRL_PARAM_CREATOR_SW_CFG_DEFAULT_BOOT_DATA_IN_PROD_EN_OFFSET 296
198#define OTP_CTRL_PARAM_CREATOR_SW_CFG_DEFAULT_BOOT_DATA_IN_PROD_EN_SIZE 4
201#define OTP_CTRL_PARAM_CREATOR_SW_CFG_RMA_SPIN_EN_OFFSET 300
204#define OTP_CTRL_PARAM_CREATOR_SW_CFG_RMA_SPIN_EN_SIZE 4
207#define OTP_CTRL_PARAM_CREATOR_SW_CFG_RMA_SPIN_CYCLES_OFFSET 304
210#define OTP_CTRL_PARAM_CREATOR_SW_CFG_RMA_SPIN_CYCLES_SIZE 4
213#define OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_REPCNT_THRESHOLDS_OFFSET 308
216#define OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_REPCNT_THRESHOLDS_SIZE 4
219#define OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_REPCNTS_THRESHOLDS_OFFSET 312
222#define OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_REPCNTS_THRESHOLDS_SIZE 4
225#define OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_ADAPTP_HI_THRESHOLDS_OFFSET 316
228#define OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_ADAPTP_HI_THRESHOLDS_SIZE 4
231#define OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_ADAPTP_LO_THRESHOLDS_OFFSET 320
234#define OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_ADAPTP_LO_THRESHOLDS_SIZE 4
237#define OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_BUCKET_THRESHOLDS_OFFSET 324
240#define OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_BUCKET_THRESHOLDS_SIZE 4
243#define OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_MARKOV_HI_THRESHOLDS_OFFSET 328
246#define OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_MARKOV_HI_THRESHOLDS_SIZE 4
249#define OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_MARKOV_LO_THRESHOLDS_OFFSET 332
252#define OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_MARKOV_LO_THRESHOLDS_SIZE 4
255#define OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_EXTHT_HI_THRESHOLDS_OFFSET 336
258#define OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_EXTHT_HI_THRESHOLDS_SIZE 4
261#define OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_EXTHT_LO_THRESHOLDS_OFFSET 340
264#define OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_EXTHT_LO_THRESHOLDS_SIZE 4
267#define OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_ALERT_THRESHOLD_OFFSET 344
270#define OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_ALERT_THRESHOLD_SIZE 4
273#define OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_HEALTH_CONFIG_DIGEST_OFFSET 348
276#define OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_HEALTH_CONFIG_DIGEST_SIZE 4
279#define OTP_CTRL_PARAM_CREATOR_SW_CFG_SRAM_KEY_RENEW_EN_OFFSET 352
282#define OTP_CTRL_PARAM_CREATOR_SW_CFG_SRAM_KEY_RENEW_EN_SIZE 4
285#define OTP_CTRL_PARAM_CREATOR_SW_CFG_DIGEST_OFFSET 360
288#define OTP_CTRL_PARAM_CREATOR_SW_CFG_DIGEST_SIZE 8
291#define OTP_CTRL_PARAM_OWNER_SW_CFG_OFFSET 368
294#define OTP_CTRL_PARAM_OWNER_SW_CFG_SIZE 600
297#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_ERROR_REPORTING_OFFSET 368
300#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_ERROR_REPORTING_SIZE 4
303#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_BOOTSTRAP_DIS_OFFSET 372
306#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_BOOTSTRAP_DIS_SIZE 4
309#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_ALERT_CLASS_EN_OFFSET 376
312#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_ALERT_CLASS_EN_SIZE 4
315#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_ALERT_ESCALATION_OFFSET 380
318#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_ALERT_ESCALATION_SIZE 4
321#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION_OFFSET 384
324#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION_SIZE 420
327#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_LOCAL_ALERT_CLASSIFICATION_OFFSET 804
330#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_LOCAL_ALERT_CLASSIFICATION_SIZE 28
333#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_ALERT_ACCUM_THRESH_OFFSET 832
336#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_ALERT_ACCUM_THRESH_SIZE 16
339#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_ALERT_TIMEOUT_CYCLES_OFFSET 848
342#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_ALERT_TIMEOUT_CYCLES_SIZE 16
345#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_ALERT_PHASE_CYCLES_OFFSET 864
348#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_ALERT_PHASE_CYCLES_SIZE 64
351#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_ALERT_DIGEST_PROD_OFFSET 928
354#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_ALERT_DIGEST_PROD_SIZE 4
357#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_ALERT_DIGEST_PROD_END_OFFSET 932
360#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_ALERT_DIGEST_PROD_END_SIZE 4
363#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_ALERT_DIGEST_DEV_OFFSET 936
366#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_ALERT_DIGEST_DEV_SIZE 4
369#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_ALERT_DIGEST_RMA_OFFSET 940
372#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_ALERT_DIGEST_RMA_SIZE 4
375#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_WATCHDOG_BITE_THRESHOLD_CYCLES_OFFSET \
379#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_WATCHDOG_BITE_THRESHOLD_CYCLES_SIZE 4
382#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_KEYMGR_ROM_EXT_MEAS_EN_OFFSET 948
385#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_KEYMGR_ROM_EXT_MEAS_EN_SIZE 4
388#define OTP_CTRL_PARAM_OWNER_SW_CFG_MANUF_STATE_OFFSET 952
391#define OTP_CTRL_PARAM_OWNER_SW_CFG_MANUF_STATE_SIZE 4
394#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_RSTMGR_INFO_EN_OFFSET 956
397#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_RSTMGR_INFO_EN_SIZE 4
400#define OTP_CTRL_PARAM_OWNER_SW_CFG_DIGEST_OFFSET 960
403#define OTP_CTRL_PARAM_OWNER_SW_CFG_DIGEST_SIZE 8
406#define OTP_CTRL_PARAM_OWNERSHIP_SLOT_STATE_OFFSET 968
409#define OTP_CTRL_PARAM_OWNERSHIP_SLOT_STATE_SIZE 48
412#define OTP_CTRL_PARAM_OWNERSHIP_SLOT_STATE_ROT_OWNER_AUTH_OFFSET 968
415#define OTP_CTRL_PARAM_OWNERSHIP_SLOT_STATE_ROT_OWNER_AUTH_SIZE 16
418#define OTP_CTRL_PARAM_OWNERSHIP_SLOT_STATE_PLAT_INTEG_AUTH_OFFSET 984
421#define OTP_CTRL_PARAM_OWNERSHIP_SLOT_STATE_PLAT_INTEG_AUTH_SIZE 16
424#define OTP_CTRL_PARAM_OWNERSHIP_SLOT_STATE_PLAT_OWNER_AUTH_OFFSET 1000
427#define OTP_CTRL_PARAM_OWNERSHIP_SLOT_STATE_PLAT_OWNER_AUTH_SIZE 16
430#define OTP_CTRL_PARAM_ROT_CREATOR_AUTH_OFFSET 1016
433#define OTP_CTRL_PARAM_ROT_CREATOR_AUTH_SIZE 1424
436#define OTP_CTRL_PARAM_ROT_CREATOR_AUTH_NON_RAW_MFW_CODESIGN_KEY_OFFSET 1016
439#define OTP_CTRL_PARAM_ROT_CREATOR_AUTH_NON_RAW_MFW_CODESIGN_KEY_SIZE 160
442#define OTP_CTRL_PARAM_ROT_CREATOR_AUTH_OWNERSHIP_STATE_OFFSET 1176
445#define OTP_CTRL_PARAM_ROT_CREATOR_AUTH_OWNERSHIP_STATE_SIZE 4
448#define OTP_CTRL_PARAM_ROT_CREATOR_AUTH_ROM2_PATCH_SIGVERIFY_KEY_OFFSET 1180
451#define OTP_CTRL_PARAM_ROT_CREATOR_AUTH_ROM2_PATCH_SIGVERIFY_KEY_SIZE 160
454#define OTP_CTRL_PARAM_ROT_CREATOR_AUTH_KEYMANIFEST_KEY_OFFSET 1340
457#define OTP_CTRL_PARAM_ROT_CREATOR_AUTH_KEYMANIFEST_KEY_SIZE 160
460#define OTP_CTRL_PARAM_ROT_CREATOR_AUTH_UNLOCK4XFER_KEY_OFFSET 1500
463#define OTP_CTRL_PARAM_ROT_CREATOR_AUTH_UNLOCK4XFER_KEY_SIZE 160
466#define OTP_CTRL_PARAM_ROT_CREATOR_AUTH_IDENTITY_CERT_OFFSET 1660
469#define OTP_CTRL_PARAM_ROT_CREATOR_AUTH_IDENTITY_CERT_SIZE 768
472#define OTP_CTRL_PARAM_ROT_CREATOR_AUTH_DIGEST_OFFSET 2432
475#define OTP_CTRL_PARAM_ROT_CREATOR_AUTH_DIGEST_SIZE 8
478#define OTP_CTRL_PARAM_ROT_OWNER_AUTH_SLOT0_OFFSET 2440
481#define OTP_CTRL_PARAM_ROT_OWNER_AUTH_SLOT0_SIZE 328
484#define OTP_CTRL_PARAM_ROT_OWNER_AUTH_SLOT0_KEYMANIFEST_KEY_OFFSET 2440
487#define OTP_CTRL_PARAM_ROT_OWNER_AUTH_SLOT0_KEYMANIFEST_KEY_SIZE 160
490#define OTP_CTRL_PARAM_ROT_OWNER_AUTH_SLOT0_UNLOCK4XFER_KEY_OFFSET 2600
493#define OTP_CTRL_PARAM_ROT_OWNER_AUTH_SLOT0_UNLOCK4XFER_KEY_SIZE 160
496#define OTP_CTRL_PARAM_ROT_OWNER_AUTH_SLOT0_DIGEST_OFFSET 2760
499#define OTP_CTRL_PARAM_ROT_OWNER_AUTH_SLOT0_DIGEST_SIZE 8
502#define OTP_CTRL_PARAM_ROT_OWNER_AUTH_SLOT1_OFFSET 2768
505#define OTP_CTRL_PARAM_ROT_OWNER_AUTH_SLOT1_SIZE 328
508#define OTP_CTRL_PARAM_ROT_OWNER_AUTH_SLOT1_KEYMANIFEST_KEY_OFFSET 2768
511#define OTP_CTRL_PARAM_ROT_OWNER_AUTH_SLOT1_KEYMANIFEST_KEY_SIZE 160
514#define OTP_CTRL_PARAM_ROT_OWNER_AUTH_SLOT1_UNLOCK4XFER_KEY_OFFSET 2928
517#define OTP_CTRL_PARAM_ROT_OWNER_AUTH_SLOT1_UNLOCK4XFER_KEY_SIZE 160
520#define OTP_CTRL_PARAM_ROT_OWNER_AUTH_SLOT1_DIGEST_OFFSET 3088
523#define OTP_CTRL_PARAM_ROT_OWNER_AUTH_SLOT1_DIGEST_SIZE 8
526#define OTP_CTRL_PARAM_PLAT_INTEG_AUTH_SLOT0_OFFSET 3096
529#define OTP_CTRL_PARAM_PLAT_INTEG_AUTH_SLOT0_SIZE 328
532#define OTP_CTRL_PARAM_PLAT_INTEG_AUTH_SLOT0_KEYMANIFEST_KEY_OFFSET 3096
535#define OTP_CTRL_PARAM_PLAT_INTEG_AUTH_SLOT0_KEYMANIFEST_KEY_SIZE 160
538#define OTP_CTRL_PARAM_PLAT_INTEG_AUTH_SLOT0_UNLOCK4XFER_KEY_OFFSET 3256
541#define OTP_CTRL_PARAM_PLAT_INTEG_AUTH_SLOT0_UNLOCK4XFER_KEY_SIZE 160
544#define OTP_CTRL_PARAM_PLAT_INTEG_AUTH_SLOT0_DIGEST_OFFSET 3416
547#define OTP_CTRL_PARAM_PLAT_INTEG_AUTH_SLOT0_DIGEST_SIZE 8
550#define OTP_CTRL_PARAM_PLAT_INTEG_AUTH_SLOT1_OFFSET 3424
553#define OTP_CTRL_PARAM_PLAT_INTEG_AUTH_SLOT1_SIZE 328
556#define OTP_CTRL_PARAM_PLAT_INTEG_AUTH_SLOT1_KEYMANIFEST_KEY_OFFSET 3424
559#define OTP_CTRL_PARAM_PLAT_INTEG_AUTH_SLOT1_KEYMANIFEST_KEY_SIZE 160
562#define OTP_CTRL_PARAM_PLAT_INTEG_AUTH_SLOT1_UNLOCK4XFER_KEY_OFFSET 3584
565#define OTP_CTRL_PARAM_PLAT_INTEG_AUTH_SLOT1_UNLOCK4XFER_KEY_SIZE 160
568#define OTP_CTRL_PARAM_PLAT_INTEG_AUTH_SLOT1_DIGEST_OFFSET 3744
571#define OTP_CTRL_PARAM_PLAT_INTEG_AUTH_SLOT1_DIGEST_SIZE 8
574#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT0_OFFSET 3752
577#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT0_SIZE 328
580#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT0_KEYMANIFEST_KEY_OFFSET 3752
583#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT0_KEYMANIFEST_KEY_SIZE 160
586#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT0_UNLOCK4XFER_KEY_OFFSET 3912
589#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT0_UNLOCK4XFER_KEY_SIZE 160
592#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT0_DIGEST_OFFSET 4072
595#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT0_DIGEST_SIZE 8
598#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT1_OFFSET 4080
601#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT1_SIZE 328
604#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT1_KEYMANIFEST_KEY_OFFSET 4080
607#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT1_KEYMANIFEST_KEY_SIZE 160
610#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT1_UNLOCK4XFER_KEY_OFFSET 4240
613#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT1_UNLOCK4XFER_KEY_SIZE 160
616#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT1_DIGEST_OFFSET 4400
619#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT1_DIGEST_SIZE 8
622#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT2_OFFSET 4408
625#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT2_SIZE 328
628#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT2_KEYMANIFEST_KEY_OFFSET 4408
631#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT2_KEYMANIFEST_KEY_SIZE 160
634#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT2_UNLOCK4XFER_KEY_OFFSET 4568
637#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT2_UNLOCK4XFER_KEY_SIZE 160
640#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT2_DIGEST_OFFSET 4728
643#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT2_DIGEST_SIZE 8
646#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT3_OFFSET 4736
649#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT3_SIZE 328
652#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT3_KEYMANIFEST_KEY_OFFSET 4736
655#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT3_KEYMANIFEST_KEY_SIZE 160
658#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT3_UNLOCK4XFER_KEY_OFFSET 4896
661#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT3_UNLOCK4XFER_KEY_SIZE 160
664#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT3_DIGEST_OFFSET 5056
667#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT3_DIGEST_SIZE 8
670#define OTP_CTRL_PARAM_EXT_NVM_OFFSET 5064
673#define OTP_CTRL_PARAM_EXT_NVM_SIZE 1024
676#define OTP_CTRL_PARAM_EXT_NVM_ANTIREPLAY_FRESHNESS_CNT_OFFSET 5064
679#define OTP_CTRL_PARAM_EXT_NVM_ANTIREPLAY_FRESHNESS_CNT_SIZE 1024
682#define OTP_CTRL_PARAM_ROM_PATCH_OFFSET 6088
685#define OTP_CTRL_PARAM_ROM_PATCH_SIZE 9864
688#define OTP_CTRL_PARAM_ROM_PATCH_DATA_OFFSET 6088
691#define OTP_CTRL_PARAM_ROM_PATCH_DATA_SIZE 9192
694#define OTP_CTRL_PARAM_ROM_PATCH_DIGEST_OFFSET 15944
697#define OTP_CTRL_PARAM_ROM_PATCH_DIGEST_SIZE 8
700#define OTP_CTRL_PARAM_HW_CFG0_OFFSET 15952
703#define OTP_CTRL_PARAM_HW_CFG0_SIZE 72
706#define OTP_CTRL_PARAM_DEVICE_ID_OFFSET 15952
709#define OTP_CTRL_PARAM_DEVICE_ID_SIZE 32
712#define OTP_CTRL_PARAM_MANUF_STATE_OFFSET 15984
715#define OTP_CTRL_PARAM_MANUF_STATE_SIZE 32
718#define OTP_CTRL_PARAM_HW_CFG0_DIGEST_OFFSET 16016
721#define OTP_CTRL_PARAM_HW_CFG0_DIGEST_SIZE 8
724#define OTP_CTRL_PARAM_HW_CFG1_OFFSET 16024
727#define OTP_CTRL_PARAM_HW_CFG1_SIZE 16
730#define OTP_CTRL_PARAM_SOC_DBG_STATE_OFFSET 16024
733#define OTP_CTRL_PARAM_SOC_DBG_STATE_SIZE 4
736#define OTP_CTRL_PARAM_EN_CSRNG_SW_APP_READ_OFFSET 16028
739#define OTP_CTRL_PARAM_EN_CSRNG_SW_APP_READ_SIZE 1
742#define OTP_CTRL_PARAM_EN_SRAM_IFETCH_OFFSET 16029
745#define OTP_CTRL_PARAM_EN_SRAM_IFETCH_SIZE 1
748#define OTP_CTRL_PARAM_HW_CFG1_DIGEST_OFFSET 16032
751#define OTP_CTRL_PARAM_HW_CFG1_DIGEST_SIZE 8
754#define OTP_CTRL_PARAM_SECRET0_OFFSET 16040
757#define OTP_CTRL_PARAM_SECRET0_SIZE 48
760#define OTP_CTRL_PARAM_TEST_UNLOCK_TOKEN_OFFSET 16040
763#define OTP_CTRL_PARAM_TEST_UNLOCK_TOKEN_SIZE 16
766#define OTP_CTRL_PARAM_TEST_EXIT_TOKEN_OFFSET 16056
769#define OTP_CTRL_PARAM_TEST_EXIT_TOKEN_SIZE 16
772#define OTP_CTRL_PARAM_SECRET0_DIGEST_OFFSET 16072
775#define OTP_CTRL_PARAM_SECRET0_DIGEST_SIZE 8
778#define OTP_CTRL_PARAM_SECRET0_ZER_OFFSET 16080
781#define OTP_CTRL_PARAM_SECRET0_ZER_SIZE 8
784#define OTP_CTRL_PARAM_SECRET1_OFFSET 16088
787#define OTP_CTRL_PARAM_SECRET1_SIZE 32
790#define OTP_CTRL_PARAM_SRAM_DATA_KEY_SEED_OFFSET 16088
793#define OTP_CTRL_PARAM_SRAM_DATA_KEY_SEED_SIZE 16
796#define OTP_CTRL_PARAM_SECRET1_DIGEST_OFFSET 16104
799#define OTP_CTRL_PARAM_SECRET1_DIGEST_SIZE 8
802#define OTP_CTRL_PARAM_SECRET1_ZER_OFFSET 16112
805#define OTP_CTRL_PARAM_SECRET1_ZER_SIZE 8
808#define OTP_CTRL_PARAM_SECRET2_OFFSET 16120
811#define OTP_CTRL_PARAM_SECRET2_SIZE 128
814#define OTP_CTRL_PARAM_RMA_TOKEN_OFFSET 16120
817#define OTP_CTRL_PARAM_RMA_TOKEN_SIZE 16
820#define OTP_CTRL_PARAM_CREATOR_ROOT_KEY_SHARE0_OFFSET 16136
823#define OTP_CTRL_PARAM_CREATOR_ROOT_KEY_SHARE0_SIZE 32
826#define OTP_CTRL_PARAM_CREATOR_ROOT_KEY_SHARE1_OFFSET 16168
829#define OTP_CTRL_PARAM_CREATOR_ROOT_KEY_SHARE1_SIZE 32
832#define OTP_CTRL_PARAM_CREATOR_SEED_OFFSET 16200
835#define OTP_CTRL_PARAM_CREATOR_SEED_SIZE 32
838#define OTP_CTRL_PARAM_SECRET2_DIGEST_OFFSET 16232
841#define OTP_CTRL_PARAM_SECRET2_DIGEST_SIZE 8
844#define OTP_CTRL_PARAM_SECRET2_ZER_OFFSET 16240
847#define OTP_CTRL_PARAM_SECRET2_ZER_SIZE 8
850#define OTP_CTRL_PARAM_SECRET3_OFFSET 16248
853#define OTP_CTRL_PARAM_SECRET3_SIZE 48
856#define OTP_CTRL_PARAM_OWNER_SEED_OFFSET 16248
859#define OTP_CTRL_PARAM_OWNER_SEED_SIZE 32
862#define OTP_CTRL_PARAM_SECRET3_DIGEST_OFFSET 16280
865#define OTP_CTRL_PARAM_SECRET3_DIGEST_SIZE 8
868#define OTP_CTRL_PARAM_SECRET3_ZER_OFFSET 16288
871#define OTP_CTRL_PARAM_SECRET3_ZER_SIZE 8
874#define OTP_CTRL_PARAM_LIFE_CYCLE_OFFSET 16296
877#define OTP_CTRL_PARAM_LIFE_CYCLE_SIZE 88
880#define OTP_CTRL_PARAM_LC_TRANSITION_CNT_OFFSET 16296
883#define OTP_CTRL_PARAM_LC_TRANSITION_CNT_SIZE 48
886#define OTP_CTRL_PARAM_LC_STATE_OFFSET 16344
889#define OTP_CTRL_PARAM_LC_STATE_SIZE 40
892#define OTP_CTRL_PARAM_NUM_ALERTS 5
895#define OTP_CTRL_PARAM_REG_WIDTH 32
898#define OTP_CTRL_INTR_COMMON_OTP_OPERATION_DONE_BIT 0
899#define OTP_CTRL_INTR_COMMON_OTP_ERROR_BIT 1
902#define OTP_CTRL_INTR_STATE_REG_OFFSET 0x0
903#define OTP_CTRL_INTR_STATE_REG_RESVAL 0x0u
904#define OTP_CTRL_INTR_STATE_OTP_OPERATION_DONE_BIT 0
905#define OTP_CTRL_INTR_STATE_OTP_ERROR_BIT 1
908#define OTP_CTRL_INTR_ENABLE_REG_OFFSET 0x4
909#define OTP_CTRL_INTR_ENABLE_REG_RESVAL 0x0u
910#define OTP_CTRL_INTR_ENABLE_OTP_OPERATION_DONE_BIT 0
911#define OTP_CTRL_INTR_ENABLE_OTP_ERROR_BIT 1
914#define OTP_CTRL_INTR_TEST_REG_OFFSET 0x8
915#define OTP_CTRL_INTR_TEST_REG_RESVAL 0x0u
916#define OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_BIT 0
917#define OTP_CTRL_INTR_TEST_OTP_ERROR_BIT 1
920#define OTP_CTRL_ALERT_TEST_REG_OFFSET 0xc
921#define OTP_CTRL_ALERT_TEST_REG_RESVAL 0x0u
922#define OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_BIT 0
923#define OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_BIT 1
924#define OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_BIT 2
925#define OTP_CTRL_ALERT_TEST_FATAL_PRIM_OTP_ALERT_BIT 3
926#define OTP_CTRL_ALERT_TEST_RECOV_PRIM_OTP_ALERT_BIT 4
929#define OTP_CTRL_STATUS_REG_OFFSET 0x10
930#define OTP_CTRL_STATUS_REG_RESVAL 0x0u
931#define OTP_CTRL_STATUS_VENDOR_TEST_ERROR_BIT 0
932#define OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_BIT 1
933#define OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_BIT 2
934#define OTP_CTRL_STATUS_OWNERSHIP_SLOT_STATE_ERROR_BIT 3
935#define OTP_CTRL_STATUS_ROT_CREATOR_AUTH_ERROR_BIT 4
936#define OTP_CTRL_STATUS_ROT_OWNER_AUTH_SLOT0_ERROR_BIT 5
937#define OTP_CTRL_STATUS_ROT_OWNER_AUTH_SLOT1_ERROR_BIT 6
938#define OTP_CTRL_STATUS_PLAT_INTEG_AUTH_SLOT0_ERROR_BIT 7
939#define OTP_CTRL_STATUS_PLAT_INTEG_AUTH_SLOT1_ERROR_BIT 8
940#define OTP_CTRL_STATUS_PLAT_OWNER_AUTH_SLOT0_ERROR_BIT 9
941#define OTP_CTRL_STATUS_PLAT_OWNER_AUTH_SLOT1_ERROR_BIT 10
942#define OTP_CTRL_STATUS_PLAT_OWNER_AUTH_SLOT2_ERROR_BIT 11
943#define OTP_CTRL_STATUS_PLAT_OWNER_AUTH_SLOT3_ERROR_BIT 12
944#define OTP_CTRL_STATUS_EXT_NVM_ERROR_BIT 13
945#define OTP_CTRL_STATUS_ROM_PATCH_ERROR_BIT 14
946#define OTP_CTRL_STATUS_HW_CFG0_ERROR_BIT 15
947#define OTP_CTRL_STATUS_HW_CFG1_ERROR_BIT 16
948#define OTP_CTRL_STATUS_SECRET0_ERROR_BIT 17
949#define OTP_CTRL_STATUS_SECRET1_ERROR_BIT 18
950#define OTP_CTRL_STATUS_SECRET2_ERROR_BIT 19
951#define OTP_CTRL_STATUS_SECRET3_ERROR_BIT 20
952#define OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_BIT 21
953#define OTP_CTRL_STATUS_DAI_ERROR_BIT 22
954#define OTP_CTRL_STATUS_LCI_ERROR_BIT 23
955#define OTP_CTRL_STATUS_TIMEOUT_ERROR_BIT 24
956#define OTP_CTRL_STATUS_LFSR_FSM_ERROR_BIT 25
957#define OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_BIT 26
958#define OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_BIT 27
959#define OTP_CTRL_STATUS_BUS_INTEG_ERROR_BIT 28
960#define OTP_CTRL_STATUS_DAI_IDLE_BIT 29
961#define OTP_CTRL_STATUS_CHECK_PENDING_BIT 30
965#define OTP_CTRL_ERR_CODE_ERR_CODE_FIELD_WIDTH 3
966#define OTP_CTRL_ERR_CODE_MULTIREG_COUNT 24
970#define OTP_CTRL_ERR_CODE_0_REG_OFFSET 0x14
971#define OTP_CTRL_ERR_CODE_0_REG_RESVAL 0x0u
972#define OTP_CTRL_ERR_CODE_0_ERR_CODE_0_MASK 0x7u
973#define OTP_CTRL_ERR_CODE_0_ERR_CODE_0_OFFSET 0
974#define OTP_CTRL_ERR_CODE_0_ERR_CODE_0_FIELD \
975 ((bitfield_field32_t) { .mask = OTP_CTRL_ERR_CODE_0_ERR_CODE_0_MASK, .index = OTP_CTRL_ERR_CODE_0_ERR_CODE_0_OFFSET })
976#define OTP_CTRL_ERR_CODE_0_ERR_CODE_0_VALUE_NO_ERROR 0x0
977#define OTP_CTRL_ERR_CODE_0_ERR_CODE_0_VALUE_MACRO_ERROR 0x1
978#define OTP_CTRL_ERR_CODE_0_ERR_CODE_0_VALUE_MACRO_ECC_CORR_ERROR 0x2
979#define OTP_CTRL_ERR_CODE_0_ERR_CODE_0_VALUE_MACRO_ECC_UNCORR_ERROR 0x3
980#define OTP_CTRL_ERR_CODE_0_ERR_CODE_0_VALUE_MACRO_WRITE_BLANK_ERROR 0x4
981#define OTP_CTRL_ERR_CODE_0_ERR_CODE_0_VALUE_ACCESS_ERROR 0x5
982#define OTP_CTRL_ERR_CODE_0_ERR_CODE_0_VALUE_CHECK_FAIL_ERROR 0x6
983#define OTP_CTRL_ERR_CODE_0_ERR_CODE_0_VALUE_FSM_STATE_ERROR 0x7
987#define OTP_CTRL_ERR_CODE_1_REG_OFFSET 0x18
988#define OTP_CTRL_ERR_CODE_1_REG_RESVAL 0x0u
989#define OTP_CTRL_ERR_CODE_1_ERR_CODE_1_MASK 0x7u
990#define OTP_CTRL_ERR_CODE_1_ERR_CODE_1_OFFSET 0
991#define OTP_CTRL_ERR_CODE_1_ERR_CODE_1_FIELD \
992 ((bitfield_field32_t) { .mask = OTP_CTRL_ERR_CODE_1_ERR_CODE_1_MASK, .index = OTP_CTRL_ERR_CODE_1_ERR_CODE_1_OFFSET })
996#define OTP_CTRL_ERR_CODE_2_REG_OFFSET 0x1c
997#define OTP_CTRL_ERR_CODE_2_REG_RESVAL 0x0u
998#define OTP_CTRL_ERR_CODE_2_ERR_CODE_2_MASK 0x7u
999#define OTP_CTRL_ERR_CODE_2_ERR_CODE_2_OFFSET 0
1000#define OTP_CTRL_ERR_CODE_2_ERR_CODE_2_FIELD \
1001 ((bitfield_field32_t) { .mask = OTP_CTRL_ERR_CODE_2_ERR_CODE_2_MASK, .index = OTP_CTRL_ERR_CODE_2_ERR_CODE_2_OFFSET })
1005#define OTP_CTRL_ERR_CODE_3_REG_OFFSET 0x20
1006#define OTP_CTRL_ERR_CODE_3_REG_RESVAL 0x0u
1007#define OTP_CTRL_ERR_CODE_3_ERR_CODE_3_MASK 0x7u
1008#define OTP_CTRL_ERR_CODE_3_ERR_CODE_3_OFFSET 0
1009#define OTP_CTRL_ERR_CODE_3_ERR_CODE_3_FIELD \
1010 ((bitfield_field32_t) { .mask = OTP_CTRL_ERR_CODE_3_ERR_CODE_3_MASK, .index = OTP_CTRL_ERR_CODE_3_ERR_CODE_3_OFFSET })
1014#define OTP_CTRL_ERR_CODE_4_REG_OFFSET 0x24
1015#define OTP_CTRL_ERR_CODE_4_REG_RESVAL 0x0u
1016#define OTP_CTRL_ERR_CODE_4_ERR_CODE_4_MASK 0x7u
1017#define OTP_CTRL_ERR_CODE_4_ERR_CODE_4_OFFSET 0
1018#define OTP_CTRL_ERR_CODE_4_ERR_CODE_4_FIELD \
1019 ((bitfield_field32_t) { .mask = OTP_CTRL_ERR_CODE_4_ERR_CODE_4_MASK, .index = OTP_CTRL_ERR_CODE_4_ERR_CODE_4_OFFSET })
1023#define OTP_CTRL_ERR_CODE_5_REG_OFFSET 0x28
1024#define OTP_CTRL_ERR_CODE_5_REG_RESVAL 0x0u
1025#define OTP_CTRL_ERR_CODE_5_ERR_CODE_5_MASK 0x7u
1026#define OTP_CTRL_ERR_CODE_5_ERR_CODE_5_OFFSET 0
1027#define OTP_CTRL_ERR_CODE_5_ERR_CODE_5_FIELD \
1028 ((bitfield_field32_t) { .mask = OTP_CTRL_ERR_CODE_5_ERR_CODE_5_MASK, .index = OTP_CTRL_ERR_CODE_5_ERR_CODE_5_OFFSET })
1032#define OTP_CTRL_ERR_CODE_6_REG_OFFSET 0x2c
1033#define OTP_CTRL_ERR_CODE_6_REG_RESVAL 0x0u
1034#define OTP_CTRL_ERR_CODE_6_ERR_CODE_6_MASK 0x7u
1035#define OTP_CTRL_ERR_CODE_6_ERR_CODE_6_OFFSET 0
1036#define OTP_CTRL_ERR_CODE_6_ERR_CODE_6_FIELD \
1037 ((bitfield_field32_t) { .mask = OTP_CTRL_ERR_CODE_6_ERR_CODE_6_MASK, .index = OTP_CTRL_ERR_CODE_6_ERR_CODE_6_OFFSET })
1041#define OTP_CTRL_ERR_CODE_7_REG_OFFSET 0x30
1042#define OTP_CTRL_ERR_CODE_7_REG_RESVAL 0x0u
1043#define OTP_CTRL_ERR_CODE_7_ERR_CODE_7_MASK 0x7u
1044#define OTP_CTRL_ERR_CODE_7_ERR_CODE_7_OFFSET 0
1045#define OTP_CTRL_ERR_CODE_7_ERR_CODE_7_FIELD \
1046 ((bitfield_field32_t) { .mask = OTP_CTRL_ERR_CODE_7_ERR_CODE_7_MASK, .index = OTP_CTRL_ERR_CODE_7_ERR_CODE_7_OFFSET })
1050#define OTP_CTRL_ERR_CODE_8_REG_OFFSET 0x34
1051#define OTP_CTRL_ERR_CODE_8_REG_RESVAL 0x0u
1052#define OTP_CTRL_ERR_CODE_8_ERR_CODE_8_MASK 0x7u
1053#define OTP_CTRL_ERR_CODE_8_ERR_CODE_8_OFFSET 0
1054#define OTP_CTRL_ERR_CODE_8_ERR_CODE_8_FIELD \
1055 ((bitfield_field32_t) { .mask = OTP_CTRL_ERR_CODE_8_ERR_CODE_8_MASK, .index = OTP_CTRL_ERR_CODE_8_ERR_CODE_8_OFFSET })
1059#define OTP_CTRL_ERR_CODE_9_REG_OFFSET 0x38
1060#define OTP_CTRL_ERR_CODE_9_REG_RESVAL 0x0u
1061#define OTP_CTRL_ERR_CODE_9_ERR_CODE_9_MASK 0x7u
1062#define OTP_CTRL_ERR_CODE_9_ERR_CODE_9_OFFSET 0
1063#define OTP_CTRL_ERR_CODE_9_ERR_CODE_9_FIELD \
1064 ((bitfield_field32_t) { .mask = OTP_CTRL_ERR_CODE_9_ERR_CODE_9_MASK, .index = OTP_CTRL_ERR_CODE_9_ERR_CODE_9_OFFSET })
1068#define OTP_CTRL_ERR_CODE_10_REG_OFFSET 0x3c
1069#define OTP_CTRL_ERR_CODE_10_REG_RESVAL 0x0u
1070#define OTP_CTRL_ERR_CODE_10_ERR_CODE_10_MASK 0x7u
1071#define OTP_CTRL_ERR_CODE_10_ERR_CODE_10_OFFSET 0
1072#define OTP_CTRL_ERR_CODE_10_ERR_CODE_10_FIELD \
1073 ((bitfield_field32_t) { .mask = OTP_CTRL_ERR_CODE_10_ERR_CODE_10_MASK, .index = OTP_CTRL_ERR_CODE_10_ERR_CODE_10_OFFSET })
1077#define OTP_CTRL_ERR_CODE_11_REG_OFFSET 0x40
1078#define OTP_CTRL_ERR_CODE_11_REG_RESVAL 0x0u
1079#define OTP_CTRL_ERR_CODE_11_ERR_CODE_11_MASK 0x7u
1080#define OTP_CTRL_ERR_CODE_11_ERR_CODE_11_OFFSET 0
1081#define OTP_CTRL_ERR_CODE_11_ERR_CODE_11_FIELD \
1082 ((bitfield_field32_t) { .mask = OTP_CTRL_ERR_CODE_11_ERR_CODE_11_MASK, .index = OTP_CTRL_ERR_CODE_11_ERR_CODE_11_OFFSET })
1086#define OTP_CTRL_ERR_CODE_12_REG_OFFSET 0x44
1087#define OTP_CTRL_ERR_CODE_12_REG_RESVAL 0x0u
1088#define OTP_CTRL_ERR_CODE_12_ERR_CODE_12_MASK 0x7u
1089#define OTP_CTRL_ERR_CODE_12_ERR_CODE_12_OFFSET 0
1090#define OTP_CTRL_ERR_CODE_12_ERR_CODE_12_FIELD \
1091 ((bitfield_field32_t) { .mask = OTP_CTRL_ERR_CODE_12_ERR_CODE_12_MASK, .index = OTP_CTRL_ERR_CODE_12_ERR_CODE_12_OFFSET })
1095#define OTP_CTRL_ERR_CODE_13_REG_OFFSET 0x48
1096#define OTP_CTRL_ERR_CODE_13_REG_RESVAL 0x0u
1097#define OTP_CTRL_ERR_CODE_13_ERR_CODE_13_MASK 0x7u
1098#define OTP_CTRL_ERR_CODE_13_ERR_CODE_13_OFFSET 0
1099#define OTP_CTRL_ERR_CODE_13_ERR_CODE_13_FIELD \
1100 ((bitfield_field32_t) { .mask = OTP_CTRL_ERR_CODE_13_ERR_CODE_13_MASK, .index = OTP_CTRL_ERR_CODE_13_ERR_CODE_13_OFFSET })
1104#define OTP_CTRL_ERR_CODE_14_REG_OFFSET 0x4c
1105#define OTP_CTRL_ERR_CODE_14_REG_RESVAL 0x0u
1106#define OTP_CTRL_ERR_CODE_14_ERR_CODE_14_MASK 0x7u
1107#define OTP_CTRL_ERR_CODE_14_ERR_CODE_14_OFFSET 0
1108#define OTP_CTRL_ERR_CODE_14_ERR_CODE_14_FIELD \
1109 ((bitfield_field32_t) { .mask = OTP_CTRL_ERR_CODE_14_ERR_CODE_14_MASK, .index = OTP_CTRL_ERR_CODE_14_ERR_CODE_14_OFFSET })
1113#define OTP_CTRL_ERR_CODE_15_REG_OFFSET 0x50
1114#define OTP_CTRL_ERR_CODE_15_REG_RESVAL 0x0u
1115#define OTP_CTRL_ERR_CODE_15_ERR_CODE_15_MASK 0x7u
1116#define OTP_CTRL_ERR_CODE_15_ERR_CODE_15_OFFSET 0
1117#define OTP_CTRL_ERR_CODE_15_ERR_CODE_15_FIELD \
1118 ((bitfield_field32_t) { .mask = OTP_CTRL_ERR_CODE_15_ERR_CODE_15_MASK, .index = OTP_CTRL_ERR_CODE_15_ERR_CODE_15_OFFSET })
1122#define OTP_CTRL_ERR_CODE_16_REG_OFFSET 0x54
1123#define OTP_CTRL_ERR_CODE_16_REG_RESVAL 0x0u
1124#define OTP_CTRL_ERR_CODE_16_ERR_CODE_16_MASK 0x7u
1125#define OTP_CTRL_ERR_CODE_16_ERR_CODE_16_OFFSET 0
1126#define OTP_CTRL_ERR_CODE_16_ERR_CODE_16_FIELD \
1127 ((bitfield_field32_t) { .mask = OTP_CTRL_ERR_CODE_16_ERR_CODE_16_MASK, .index = OTP_CTRL_ERR_CODE_16_ERR_CODE_16_OFFSET })
1131#define OTP_CTRL_ERR_CODE_17_REG_OFFSET 0x58
1132#define OTP_CTRL_ERR_CODE_17_REG_RESVAL 0x0u
1133#define OTP_CTRL_ERR_CODE_17_ERR_CODE_17_MASK 0x7u
1134#define OTP_CTRL_ERR_CODE_17_ERR_CODE_17_OFFSET 0
1135#define OTP_CTRL_ERR_CODE_17_ERR_CODE_17_FIELD \
1136 ((bitfield_field32_t) { .mask = OTP_CTRL_ERR_CODE_17_ERR_CODE_17_MASK, .index = OTP_CTRL_ERR_CODE_17_ERR_CODE_17_OFFSET })
1140#define OTP_CTRL_ERR_CODE_18_REG_OFFSET 0x5c
1141#define OTP_CTRL_ERR_CODE_18_REG_RESVAL 0x0u
1142#define OTP_CTRL_ERR_CODE_18_ERR_CODE_18_MASK 0x7u
1143#define OTP_CTRL_ERR_CODE_18_ERR_CODE_18_OFFSET 0
1144#define OTP_CTRL_ERR_CODE_18_ERR_CODE_18_FIELD \
1145 ((bitfield_field32_t) { .mask = OTP_CTRL_ERR_CODE_18_ERR_CODE_18_MASK, .index = OTP_CTRL_ERR_CODE_18_ERR_CODE_18_OFFSET })
1149#define OTP_CTRL_ERR_CODE_19_REG_OFFSET 0x60
1150#define OTP_CTRL_ERR_CODE_19_REG_RESVAL 0x0u
1151#define OTP_CTRL_ERR_CODE_19_ERR_CODE_19_MASK 0x7u
1152#define OTP_CTRL_ERR_CODE_19_ERR_CODE_19_OFFSET 0
1153#define OTP_CTRL_ERR_CODE_19_ERR_CODE_19_FIELD \
1154 ((bitfield_field32_t) { .mask = OTP_CTRL_ERR_CODE_19_ERR_CODE_19_MASK, .index = OTP_CTRL_ERR_CODE_19_ERR_CODE_19_OFFSET })
1158#define OTP_CTRL_ERR_CODE_20_REG_OFFSET 0x64
1159#define OTP_CTRL_ERR_CODE_20_REG_RESVAL 0x0u
1160#define OTP_CTRL_ERR_CODE_20_ERR_CODE_20_MASK 0x7u
1161#define OTP_CTRL_ERR_CODE_20_ERR_CODE_20_OFFSET 0
1162#define OTP_CTRL_ERR_CODE_20_ERR_CODE_20_FIELD \
1163 ((bitfield_field32_t) { .mask = OTP_CTRL_ERR_CODE_20_ERR_CODE_20_MASK, .index = OTP_CTRL_ERR_CODE_20_ERR_CODE_20_OFFSET })
1167#define OTP_CTRL_ERR_CODE_21_REG_OFFSET 0x68
1168#define OTP_CTRL_ERR_CODE_21_REG_RESVAL 0x0u
1169#define OTP_CTRL_ERR_CODE_21_ERR_CODE_21_MASK 0x7u
1170#define OTP_CTRL_ERR_CODE_21_ERR_CODE_21_OFFSET 0
1171#define OTP_CTRL_ERR_CODE_21_ERR_CODE_21_FIELD \
1172 ((bitfield_field32_t) { .mask = OTP_CTRL_ERR_CODE_21_ERR_CODE_21_MASK, .index = OTP_CTRL_ERR_CODE_21_ERR_CODE_21_OFFSET })
1176#define OTP_CTRL_ERR_CODE_22_REG_OFFSET 0x6c
1177#define OTP_CTRL_ERR_CODE_22_REG_RESVAL 0x0u
1178#define OTP_CTRL_ERR_CODE_22_ERR_CODE_22_MASK 0x7u
1179#define OTP_CTRL_ERR_CODE_22_ERR_CODE_22_OFFSET 0
1180#define OTP_CTRL_ERR_CODE_22_ERR_CODE_22_FIELD \
1181 ((bitfield_field32_t) { .mask = OTP_CTRL_ERR_CODE_22_ERR_CODE_22_MASK, .index = OTP_CTRL_ERR_CODE_22_ERR_CODE_22_OFFSET })
1185#define OTP_CTRL_ERR_CODE_23_REG_OFFSET 0x70
1186#define OTP_CTRL_ERR_CODE_23_REG_RESVAL 0x0u
1187#define OTP_CTRL_ERR_CODE_23_ERR_CODE_23_MASK 0x7u
1188#define OTP_CTRL_ERR_CODE_23_ERR_CODE_23_OFFSET 0
1189#define OTP_CTRL_ERR_CODE_23_ERR_CODE_23_FIELD \
1190 ((bitfield_field32_t) { .mask = OTP_CTRL_ERR_CODE_23_ERR_CODE_23_MASK, .index = OTP_CTRL_ERR_CODE_23_ERR_CODE_23_OFFSET })
1193#define OTP_CTRL_DIRECT_ACCESS_REGWEN_REG_OFFSET 0x74
1194#define OTP_CTRL_DIRECT_ACCESS_REGWEN_REG_RESVAL 0x1u
1195#define OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_BIT 0
1198#define OTP_CTRL_DIRECT_ACCESS_CMD_REG_OFFSET 0x78
1199#define OTP_CTRL_DIRECT_ACCESS_CMD_REG_RESVAL 0x0u
1200#define OTP_CTRL_DIRECT_ACCESS_CMD_RD_BIT 0
1201#define OTP_CTRL_DIRECT_ACCESS_CMD_WR_BIT 1
1202#define OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_BIT 2
1203#define OTP_CTRL_DIRECT_ACCESS_CMD_ZEROIZE_BIT 3
1206#define OTP_CTRL_DIRECT_ACCESS_ADDRESS_REG_OFFSET 0x7c
1207#define OTP_CTRL_DIRECT_ACCESS_ADDRESS_REG_RESVAL 0x0u
1208#define OTP_CTRL_DIRECT_ACCESS_ADDRESS_DIRECT_ACCESS_ADDRESS_MASK 0x3fffu
1209#define OTP_CTRL_DIRECT_ACCESS_ADDRESS_DIRECT_ACCESS_ADDRESS_OFFSET 0
1210#define OTP_CTRL_DIRECT_ACCESS_ADDRESS_DIRECT_ACCESS_ADDRESS_FIELD \
1211 ((bitfield_field32_t) { .mask = OTP_CTRL_DIRECT_ACCESS_ADDRESS_DIRECT_ACCESS_ADDRESS_MASK, .index = OTP_CTRL_DIRECT_ACCESS_ADDRESS_DIRECT_ACCESS_ADDRESS_OFFSET })
1214#define OTP_CTRL_DIRECT_ACCESS_WDATA_DIRECT_ACCESS_WDATA_FIELD_WIDTH 32
1215#define OTP_CTRL_DIRECT_ACCESS_WDATA_MULTIREG_COUNT 2
1218#define OTP_CTRL_DIRECT_ACCESS_WDATA_0_REG_OFFSET 0x80
1219#define OTP_CTRL_DIRECT_ACCESS_WDATA_0_REG_RESVAL 0x0u
1222#define OTP_CTRL_DIRECT_ACCESS_WDATA_1_REG_OFFSET 0x84
1223#define OTP_CTRL_DIRECT_ACCESS_WDATA_1_REG_RESVAL 0x0u
1226#define OTP_CTRL_DIRECT_ACCESS_RDATA_DIRECT_ACCESS_RDATA_FIELD_WIDTH 32
1227#define OTP_CTRL_DIRECT_ACCESS_RDATA_MULTIREG_COUNT 2
1230#define OTP_CTRL_DIRECT_ACCESS_RDATA_0_REG_OFFSET 0x88
1231#define OTP_CTRL_DIRECT_ACCESS_RDATA_0_REG_RESVAL 0x0u
1234#define OTP_CTRL_DIRECT_ACCESS_RDATA_1_REG_OFFSET 0x8c
1235#define OTP_CTRL_DIRECT_ACCESS_RDATA_1_REG_RESVAL 0x0u
1238#define OTP_CTRL_CHECK_TRIGGER_REGWEN_REG_OFFSET 0x90
1239#define OTP_CTRL_CHECK_TRIGGER_REGWEN_REG_RESVAL 0x1u
1240#define OTP_CTRL_CHECK_TRIGGER_REGWEN_CHECK_TRIGGER_REGWEN_BIT 0
1243#define OTP_CTRL_CHECK_TRIGGER_REG_OFFSET 0x94
1244#define OTP_CTRL_CHECK_TRIGGER_REG_RESVAL 0x0u
1245#define OTP_CTRL_CHECK_TRIGGER_INTEGRITY_BIT 0
1246#define OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_BIT 1
1250#define OTP_CTRL_CHECK_REGWEN_REG_OFFSET 0x98
1251#define OTP_CTRL_CHECK_REGWEN_REG_RESVAL 0x1u
1252#define OTP_CTRL_CHECK_REGWEN_CHECK_REGWEN_BIT 0
1255#define OTP_CTRL_CHECK_TIMEOUT_REG_OFFSET 0x9c
1256#define OTP_CTRL_CHECK_TIMEOUT_REG_RESVAL 0x0u
1260#define OTP_CTRL_INTEGRITY_CHECK_PERIOD_REG_OFFSET 0xa0
1261#define OTP_CTRL_INTEGRITY_CHECK_PERIOD_REG_RESVAL 0x0u
1265#define OTP_CTRL_CONSISTENCY_CHECK_PERIOD_REG_OFFSET 0xa4
1266#define OTP_CTRL_CONSISTENCY_CHECK_PERIOD_REG_RESVAL 0x0u
1269#define OTP_CTRL_VENDOR_TEST_READ_LOCK_REG_OFFSET 0xa8
1270#define OTP_CTRL_VENDOR_TEST_READ_LOCK_REG_RESVAL 0x1u
1271#define OTP_CTRL_VENDOR_TEST_READ_LOCK_VENDOR_TEST_READ_LOCK_BIT 0
1274#define OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_REG_OFFSET 0xac
1275#define OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_REG_RESVAL 0x1u
1276#define OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_CREATOR_SW_CFG_READ_LOCK_BIT 0
1279#define OTP_CTRL_OWNER_SW_CFG_READ_LOCK_REG_OFFSET 0xb0
1280#define OTP_CTRL_OWNER_SW_CFG_READ_LOCK_REG_RESVAL 0x1u
1281#define OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OWNER_SW_CFG_READ_LOCK_BIT 0
1284#define OTP_CTRL_OWNERSHIP_SLOT_STATE_READ_LOCK_REG_OFFSET 0xb4
1285#define OTP_CTRL_OWNERSHIP_SLOT_STATE_READ_LOCK_REG_RESVAL 0x1u
1286#define OTP_CTRL_OWNERSHIP_SLOT_STATE_READ_LOCK_OWNERSHIP_SLOT_STATE_READ_LOCK_BIT \
1290#define OTP_CTRL_ROT_CREATOR_AUTH_READ_LOCK_REG_OFFSET 0xb8
1291#define OTP_CTRL_ROT_CREATOR_AUTH_READ_LOCK_REG_RESVAL 0x1u
1292#define OTP_CTRL_ROT_CREATOR_AUTH_READ_LOCK_ROT_CREATOR_AUTH_READ_LOCK_BIT 0
1295#define OTP_CTRL_ROT_OWNER_AUTH_SLOT0_READ_LOCK_REG_OFFSET 0xbc
1296#define OTP_CTRL_ROT_OWNER_AUTH_SLOT0_READ_LOCK_REG_RESVAL 0x1u
1297#define OTP_CTRL_ROT_OWNER_AUTH_SLOT0_READ_LOCK_ROT_OWNER_AUTH_SLOT0_READ_LOCK_BIT \
1301#define OTP_CTRL_ROT_OWNER_AUTH_SLOT1_READ_LOCK_REG_OFFSET 0xc0
1302#define OTP_CTRL_ROT_OWNER_AUTH_SLOT1_READ_LOCK_REG_RESVAL 0x1u
1303#define OTP_CTRL_ROT_OWNER_AUTH_SLOT1_READ_LOCK_ROT_OWNER_AUTH_SLOT1_READ_LOCK_BIT \
1307#define OTP_CTRL_PLAT_INTEG_AUTH_SLOT0_READ_LOCK_REG_OFFSET 0xc4
1308#define OTP_CTRL_PLAT_INTEG_AUTH_SLOT0_READ_LOCK_REG_RESVAL 0x1u
1309#define OTP_CTRL_PLAT_INTEG_AUTH_SLOT0_READ_LOCK_PLAT_INTEG_AUTH_SLOT0_READ_LOCK_BIT \
1313#define OTP_CTRL_PLAT_INTEG_AUTH_SLOT1_READ_LOCK_REG_OFFSET 0xc8
1314#define OTP_CTRL_PLAT_INTEG_AUTH_SLOT1_READ_LOCK_REG_RESVAL 0x1u
1315#define OTP_CTRL_PLAT_INTEG_AUTH_SLOT1_READ_LOCK_PLAT_INTEG_AUTH_SLOT1_READ_LOCK_BIT \
1319#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT0_READ_LOCK_REG_OFFSET 0xcc
1320#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT0_READ_LOCK_REG_RESVAL 0x1u
1321#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT0_READ_LOCK_PLAT_OWNER_AUTH_SLOT0_READ_LOCK_BIT \
1325#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT1_READ_LOCK_REG_OFFSET 0xd0
1326#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT1_READ_LOCK_REG_RESVAL 0x1u
1327#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT1_READ_LOCK_PLAT_OWNER_AUTH_SLOT1_READ_LOCK_BIT \
1331#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT2_READ_LOCK_REG_OFFSET 0xd4
1332#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT2_READ_LOCK_REG_RESVAL 0x1u
1333#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT2_READ_LOCK_PLAT_OWNER_AUTH_SLOT2_READ_LOCK_BIT \
1337#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT3_READ_LOCK_REG_OFFSET 0xd8
1338#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT3_READ_LOCK_REG_RESVAL 0x1u
1339#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT3_READ_LOCK_PLAT_OWNER_AUTH_SLOT3_READ_LOCK_BIT \
1343#define OTP_CTRL_EXT_NVM_READ_LOCK_REG_OFFSET 0xdc
1344#define OTP_CTRL_EXT_NVM_READ_LOCK_REG_RESVAL 0x1u
1345#define OTP_CTRL_EXT_NVM_READ_LOCK_EXT_NVM_READ_LOCK_BIT 0
1348#define OTP_CTRL_ROM_PATCH_READ_LOCK_REG_OFFSET 0xe0
1349#define OTP_CTRL_ROM_PATCH_READ_LOCK_REG_RESVAL 0x1u
1350#define OTP_CTRL_ROM_PATCH_READ_LOCK_ROM_PATCH_READ_LOCK_BIT 0
1353#define OTP_CTRL_VENDOR_TEST_DIGEST_VENDOR_TEST_DIGEST_FIELD_WIDTH 32
1354#define OTP_CTRL_VENDOR_TEST_DIGEST_MULTIREG_COUNT 2
1357#define OTP_CTRL_VENDOR_TEST_DIGEST_0_REG_OFFSET 0xe4
1358#define OTP_CTRL_VENDOR_TEST_DIGEST_0_REG_RESVAL 0x0u
1361#define OTP_CTRL_VENDOR_TEST_DIGEST_1_REG_OFFSET 0xe8
1362#define OTP_CTRL_VENDOR_TEST_DIGEST_1_REG_RESVAL 0x0u
1365#define OTP_CTRL_CREATOR_SW_CFG_DIGEST_CREATOR_SW_CFG_DIGEST_FIELD_WIDTH 32
1366#define OTP_CTRL_CREATOR_SW_CFG_DIGEST_MULTIREG_COUNT 2
1369#define OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_REG_OFFSET 0xec
1370#define OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_REG_RESVAL 0x0u
1373#define OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_REG_OFFSET 0xf0
1374#define OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_REG_RESVAL 0x0u
1377#define OTP_CTRL_OWNER_SW_CFG_DIGEST_OWNER_SW_CFG_DIGEST_FIELD_WIDTH 32
1378#define OTP_CTRL_OWNER_SW_CFG_DIGEST_MULTIREG_COUNT 2
1381#define OTP_CTRL_OWNER_SW_CFG_DIGEST_0_REG_OFFSET 0xf4
1382#define OTP_CTRL_OWNER_SW_CFG_DIGEST_0_REG_RESVAL 0x0u
1385#define OTP_CTRL_OWNER_SW_CFG_DIGEST_1_REG_OFFSET 0xf8
1386#define OTP_CTRL_OWNER_SW_CFG_DIGEST_1_REG_RESVAL 0x0u
1389#define OTP_CTRL_ROT_CREATOR_AUTH_DIGEST_ROT_CREATOR_AUTH_DIGEST_FIELD_WIDTH 32
1390#define OTP_CTRL_ROT_CREATOR_AUTH_DIGEST_MULTIREG_COUNT 2
1393#define OTP_CTRL_ROT_CREATOR_AUTH_DIGEST_0_REG_OFFSET 0xfc
1394#define OTP_CTRL_ROT_CREATOR_AUTH_DIGEST_0_REG_RESVAL 0x0u
1397#define OTP_CTRL_ROT_CREATOR_AUTH_DIGEST_1_REG_OFFSET 0x100
1398#define OTP_CTRL_ROT_CREATOR_AUTH_DIGEST_1_REG_RESVAL 0x0u
1401#define OTP_CTRL_ROT_OWNER_AUTH_SLOT0_DIGEST_ROT_OWNER_AUTH_SLOT0_DIGEST_FIELD_WIDTH \
1403#define OTP_CTRL_ROT_OWNER_AUTH_SLOT0_DIGEST_MULTIREG_COUNT 2
1406#define OTP_CTRL_ROT_OWNER_AUTH_SLOT0_DIGEST_0_REG_OFFSET 0x104
1407#define OTP_CTRL_ROT_OWNER_AUTH_SLOT0_DIGEST_0_REG_RESVAL 0x0u
1410#define OTP_CTRL_ROT_OWNER_AUTH_SLOT0_DIGEST_1_REG_OFFSET 0x108
1411#define OTP_CTRL_ROT_OWNER_AUTH_SLOT0_DIGEST_1_REG_RESVAL 0x0u
1414#define OTP_CTRL_ROT_OWNER_AUTH_SLOT1_DIGEST_ROT_OWNER_AUTH_SLOT1_DIGEST_FIELD_WIDTH \
1416#define OTP_CTRL_ROT_OWNER_AUTH_SLOT1_DIGEST_MULTIREG_COUNT 2
1419#define OTP_CTRL_ROT_OWNER_AUTH_SLOT1_DIGEST_0_REG_OFFSET 0x10c
1420#define OTP_CTRL_ROT_OWNER_AUTH_SLOT1_DIGEST_0_REG_RESVAL 0x0u
1423#define OTP_CTRL_ROT_OWNER_AUTH_SLOT1_DIGEST_1_REG_OFFSET 0x110
1424#define OTP_CTRL_ROT_OWNER_AUTH_SLOT1_DIGEST_1_REG_RESVAL 0x0u
1427#define OTP_CTRL_PLAT_INTEG_AUTH_SLOT0_DIGEST_PLAT_INTEG_AUTH_SLOT0_DIGEST_FIELD_WIDTH \
1429#define OTP_CTRL_PLAT_INTEG_AUTH_SLOT0_DIGEST_MULTIREG_COUNT 2
1432#define OTP_CTRL_PLAT_INTEG_AUTH_SLOT0_DIGEST_0_REG_OFFSET 0x114
1433#define OTP_CTRL_PLAT_INTEG_AUTH_SLOT0_DIGEST_0_REG_RESVAL 0x0u
1436#define OTP_CTRL_PLAT_INTEG_AUTH_SLOT0_DIGEST_1_REG_OFFSET 0x118
1437#define OTP_CTRL_PLAT_INTEG_AUTH_SLOT0_DIGEST_1_REG_RESVAL 0x0u
1440#define OTP_CTRL_PLAT_INTEG_AUTH_SLOT1_DIGEST_PLAT_INTEG_AUTH_SLOT1_DIGEST_FIELD_WIDTH \
1442#define OTP_CTRL_PLAT_INTEG_AUTH_SLOT1_DIGEST_MULTIREG_COUNT 2
1445#define OTP_CTRL_PLAT_INTEG_AUTH_SLOT1_DIGEST_0_REG_OFFSET 0x11c
1446#define OTP_CTRL_PLAT_INTEG_AUTH_SLOT1_DIGEST_0_REG_RESVAL 0x0u
1449#define OTP_CTRL_PLAT_INTEG_AUTH_SLOT1_DIGEST_1_REG_OFFSET 0x120
1450#define OTP_CTRL_PLAT_INTEG_AUTH_SLOT1_DIGEST_1_REG_RESVAL 0x0u
1453#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT0_DIGEST_PLAT_OWNER_AUTH_SLOT0_DIGEST_FIELD_WIDTH \
1455#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT0_DIGEST_MULTIREG_COUNT 2
1458#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT0_DIGEST_0_REG_OFFSET 0x124
1459#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT0_DIGEST_0_REG_RESVAL 0x0u
1462#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT0_DIGEST_1_REG_OFFSET 0x128
1463#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT0_DIGEST_1_REG_RESVAL 0x0u
1466#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT1_DIGEST_PLAT_OWNER_AUTH_SLOT1_DIGEST_FIELD_WIDTH \
1468#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT1_DIGEST_MULTIREG_COUNT 2
1471#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT1_DIGEST_0_REG_OFFSET 0x12c
1472#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT1_DIGEST_0_REG_RESVAL 0x0u
1475#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT1_DIGEST_1_REG_OFFSET 0x130
1476#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT1_DIGEST_1_REG_RESVAL 0x0u
1479#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT2_DIGEST_PLAT_OWNER_AUTH_SLOT2_DIGEST_FIELD_WIDTH \
1481#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT2_DIGEST_MULTIREG_COUNT 2
1484#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT2_DIGEST_0_REG_OFFSET 0x134
1485#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT2_DIGEST_0_REG_RESVAL 0x0u
1488#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT2_DIGEST_1_REG_OFFSET 0x138
1489#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT2_DIGEST_1_REG_RESVAL 0x0u
1492#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT3_DIGEST_PLAT_OWNER_AUTH_SLOT3_DIGEST_FIELD_WIDTH \
1494#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT3_DIGEST_MULTIREG_COUNT 2
1497#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT3_DIGEST_0_REG_OFFSET 0x13c
1498#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT3_DIGEST_0_REG_RESVAL 0x0u
1501#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT3_DIGEST_1_REG_OFFSET 0x140
1502#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT3_DIGEST_1_REG_RESVAL 0x0u
1505#define OTP_CTRL_ROM_PATCH_DIGEST_ROM_PATCH_DIGEST_FIELD_WIDTH 32
1506#define OTP_CTRL_ROM_PATCH_DIGEST_MULTIREG_COUNT 2
1509#define OTP_CTRL_ROM_PATCH_DIGEST_0_REG_OFFSET 0x144
1510#define OTP_CTRL_ROM_PATCH_DIGEST_0_REG_RESVAL 0x0u
1513#define OTP_CTRL_ROM_PATCH_DIGEST_1_REG_OFFSET 0x148
1514#define OTP_CTRL_ROM_PATCH_DIGEST_1_REG_RESVAL 0x0u
1517#define OTP_CTRL_HW_CFG0_DIGEST_HW_CFG0_DIGEST_FIELD_WIDTH 32
1518#define OTP_CTRL_HW_CFG0_DIGEST_MULTIREG_COUNT 2
1521#define OTP_CTRL_HW_CFG0_DIGEST_0_REG_OFFSET 0x14c
1522#define OTP_CTRL_HW_CFG0_DIGEST_0_REG_RESVAL 0x0u
1525#define OTP_CTRL_HW_CFG0_DIGEST_1_REG_OFFSET 0x150
1526#define OTP_CTRL_HW_CFG0_DIGEST_1_REG_RESVAL 0x0u
1529#define OTP_CTRL_HW_CFG1_DIGEST_HW_CFG1_DIGEST_FIELD_WIDTH 32
1530#define OTP_CTRL_HW_CFG1_DIGEST_MULTIREG_COUNT 2
1533#define OTP_CTRL_HW_CFG1_DIGEST_0_REG_OFFSET 0x154
1534#define OTP_CTRL_HW_CFG1_DIGEST_0_REG_RESVAL 0x0u
1537#define OTP_CTRL_HW_CFG1_DIGEST_1_REG_OFFSET 0x158
1538#define OTP_CTRL_HW_CFG1_DIGEST_1_REG_RESVAL 0x0u
1541#define OTP_CTRL_SECRET0_DIGEST_SECRET0_DIGEST_FIELD_WIDTH 32
1542#define OTP_CTRL_SECRET0_DIGEST_MULTIREG_COUNT 2
1545#define OTP_CTRL_SECRET0_DIGEST_0_REG_OFFSET 0x15c
1546#define OTP_CTRL_SECRET0_DIGEST_0_REG_RESVAL 0x0u
1549#define OTP_CTRL_SECRET0_DIGEST_1_REG_OFFSET 0x160
1550#define OTP_CTRL_SECRET0_DIGEST_1_REG_RESVAL 0x0u
1553#define OTP_CTRL_SECRET1_DIGEST_SECRET1_DIGEST_FIELD_WIDTH 32
1554#define OTP_CTRL_SECRET1_DIGEST_MULTIREG_COUNT 2
1557#define OTP_CTRL_SECRET1_DIGEST_0_REG_OFFSET 0x164
1558#define OTP_CTRL_SECRET1_DIGEST_0_REG_RESVAL 0x0u
1561#define OTP_CTRL_SECRET1_DIGEST_1_REG_OFFSET 0x168
1562#define OTP_CTRL_SECRET1_DIGEST_1_REG_RESVAL 0x0u
1565#define OTP_CTRL_SECRET2_DIGEST_SECRET2_DIGEST_FIELD_WIDTH 32
1566#define OTP_CTRL_SECRET2_DIGEST_MULTIREG_COUNT 2
1569#define OTP_CTRL_SECRET2_DIGEST_0_REG_OFFSET 0x16c
1570#define OTP_CTRL_SECRET2_DIGEST_0_REG_RESVAL 0x0u
1573#define OTP_CTRL_SECRET2_DIGEST_1_REG_OFFSET 0x170
1574#define OTP_CTRL_SECRET2_DIGEST_1_REG_RESVAL 0x0u
1577#define OTP_CTRL_SECRET3_DIGEST_SECRET3_DIGEST_FIELD_WIDTH 32
1578#define OTP_CTRL_SECRET3_DIGEST_MULTIREG_COUNT 2
1581#define OTP_CTRL_SECRET3_DIGEST_0_REG_OFFSET 0x174
1582#define OTP_CTRL_SECRET3_DIGEST_0_REG_RESVAL 0x0u
1585#define OTP_CTRL_SECRET3_DIGEST_1_REG_OFFSET 0x178
1586#define OTP_CTRL_SECRET3_DIGEST_1_REG_RESVAL 0x0u
1590#define OTP_CTRL_SW_CFG_WINDOW_REG_OFFSET 0x4000
1591#define OTP_CTRL_SW_CFG_WINDOW_SIZE_WORDS 4096
1592#define OTP_CTRL_SW_CFG_WINDOW_SIZE_BYTES 16384