Software APIs
otp_ctrl_regs.h
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1/**
2 * @file
3 * @brief Generated register defines for otp_ctrl
4 */
5
6// Copyright information found in source file:
7// Copyright lowRISC contributors (OpenTitan project).
8
9// Licensing information found in source file:
10// Licensed under the Apache License, Version 2.0, see LICENSE for details.
11// SPDX-License-Identifier: Apache-2.0
12
13#ifndef _OTP_CTRL_REG_DEFS_
14#define _OTP_CTRL_REG_DEFS_
15
16#ifdef __cplusplus
17extern "C" {
18#endif
19// Number of key slots
20#define OTP_CTRL_PARAM_NUM_SRAM_KEY_REQ_SLOTS 4
21
22// Number of native words.
23#define OTP_CTRL_PARAM_OTP_DEPTH 8192
24
25// Number of bytes in native words.
26#define OTP_CTRL_PARAM_OTP_WIDTH 2
27
28// Number of bits to represent the native words per transaction.
29#define OTP_CTRL_PARAM_OTP_SIZE_WIDTH 2
30
31// Width of the OTP byte address.
32#define OTP_CTRL_PARAM_OTP_BYTE_ADDR_WIDTH 14
33
34// Number of error register entries.
35#define OTP_CTRL_PARAM_NUM_ERROR_ENTRIES 24
36
37// Number of 32bit words in the DAI.
38#define OTP_CTRL_PARAM_NUM_DAI_WORDS 2
39
40// Size of the digest fields in 32bit words.
41#define OTP_CTRL_PARAM_NUM_DIGEST_WORDS 2
42
43// Size of the TL-UL window in 32bit words. Note that the effective partition
44// size is smaller than that.
45#define OTP_CTRL_PARAM_NUM_SW_CFG_WINDOW_WORDS 4096
46
47// Number of partitions
48#define OTP_CTRL_PARAM_NUM_PART 22
49
50// Number of unbuffered partitions
51#define OTP_CTRL_PARAM_NUM_PART_UNBUF 15
52
53// Number of buffered partitions (including 1 lifecycle partition)
54#define OTP_CTRL_PARAM_NUM_PART_BUF 7
55
56// Offset of the VENDOR_TEST partition
57#define OTP_CTRL_PARAM_VENDOR_TEST_OFFSET 0
58
59// Size of the VENDOR_TEST partition
60#define OTP_CTRL_PARAM_VENDOR_TEST_SIZE 64
61
62// Offset of SCRATCH
63#define OTP_CTRL_PARAM_SCRATCH_OFFSET 0
64
65// Size of SCRATCH
66#define OTP_CTRL_PARAM_SCRATCH_SIZE 56
67
68// Offset of VENDOR_TEST_DIGEST
69#define OTP_CTRL_PARAM_VENDOR_TEST_DIGEST_OFFSET 56
70
71// Size of VENDOR_TEST_DIGEST
72#define OTP_CTRL_PARAM_VENDOR_TEST_DIGEST_SIZE 8
73
74// Offset of the CREATOR_SW_CFG partition
75#define OTP_CTRL_PARAM_CREATOR_SW_CFG_OFFSET 64
76
77// Size of the CREATOR_SW_CFG partition
78#define OTP_CTRL_PARAM_CREATOR_SW_CFG_SIZE 304
79
80// Offset of CREATOR_SW_CFG_AST_CFG
81#define OTP_CTRL_PARAM_CREATOR_SW_CFG_AST_CFG_OFFSET 64
82
83// Size of CREATOR_SW_CFG_AST_CFG
84#define OTP_CTRL_PARAM_CREATOR_SW_CFG_AST_CFG_SIZE 124
85
86// Offset of CREATOR_SW_CFG_AST_INIT_EN
87#define OTP_CTRL_PARAM_CREATOR_SW_CFG_AST_INIT_EN_OFFSET 188
88
89// Size of CREATOR_SW_CFG_AST_INIT_EN
90#define OTP_CTRL_PARAM_CREATOR_SW_CFG_AST_INIT_EN_SIZE 4
91
92// Offset of CREATOR_SW_CFG_OVERRIDES
93#define OTP_CTRL_PARAM_CREATOR_SW_CFG_OVERRIDES_OFFSET 192
94
95// Size of CREATOR_SW_CFG_OVERRIDES
96#define OTP_CTRL_PARAM_CREATOR_SW_CFG_OVERRIDES_SIZE 32
97
98// Offset of CREATOR_SW_CFG_ROM_EXT_SKU
99#define OTP_CTRL_PARAM_CREATOR_SW_CFG_ROM_EXT_SKU_OFFSET 224
100
101// Size of CREATOR_SW_CFG_ROM_EXT_SKU
102#define OTP_CTRL_PARAM_CREATOR_SW_CFG_ROM_EXT_SKU_SIZE 4
103
104// Offset of CREATOR_SW_CFG_SIGVERIFY_RSA_MOD_EXP_IBEX_EN
105#define OTP_CTRL_PARAM_CREATOR_SW_CFG_SIGVERIFY_RSA_MOD_EXP_IBEX_EN_OFFSET 228
106
107// Size of CREATOR_SW_CFG_SIGVERIFY_RSA_MOD_EXP_IBEX_EN
108#define OTP_CTRL_PARAM_CREATOR_SW_CFG_SIGVERIFY_RSA_MOD_EXP_IBEX_EN_SIZE 4
109
110// Offset of CREATOR_SW_CFG_SIGVERIFY_RSA_KEY_EN
111#define OTP_CTRL_PARAM_CREATOR_SW_CFG_SIGVERIFY_RSA_KEY_EN_OFFSET 232
112
113// Size of CREATOR_SW_CFG_SIGVERIFY_RSA_KEY_EN
114#define OTP_CTRL_PARAM_CREATOR_SW_CFG_SIGVERIFY_RSA_KEY_EN_SIZE 8
115
116// Offset of CREATOR_SW_CFG_SIGVERIFY_SPX_EN
117#define OTP_CTRL_PARAM_CREATOR_SW_CFG_SIGVERIFY_SPX_EN_OFFSET 240
118
119// Size of CREATOR_SW_CFG_SIGVERIFY_SPX_EN
120#define OTP_CTRL_PARAM_CREATOR_SW_CFG_SIGVERIFY_SPX_EN_SIZE 4
121
122// Offset of CREATOR_SW_CFG_SIGVERIFY_SPX_KEY_EN
123#define OTP_CTRL_PARAM_CREATOR_SW_CFG_SIGVERIFY_SPX_KEY_EN_OFFSET 244
124
125// Size of CREATOR_SW_CFG_SIGVERIFY_SPX_KEY_EN
126#define OTP_CTRL_PARAM_CREATOR_SW_CFG_SIGVERIFY_SPX_KEY_EN_SIZE 8
127
128// Offset of CREATOR_SW_CFG_FLASH_DATA_DEFAULT_CFG
129#define OTP_CTRL_PARAM_CREATOR_SW_CFG_FLASH_DATA_DEFAULT_CFG_OFFSET 252
130
131// Size of CREATOR_SW_CFG_FLASH_DATA_DEFAULT_CFG
132#define OTP_CTRL_PARAM_CREATOR_SW_CFG_FLASH_DATA_DEFAULT_CFG_SIZE 4
133
134// Offset of CREATOR_SW_CFG_FLASH_INFO_BOOT_DATA_CFG
135#define OTP_CTRL_PARAM_CREATOR_SW_CFG_FLASH_INFO_BOOT_DATA_CFG_OFFSET 256
136
137// Size of CREATOR_SW_CFG_FLASH_INFO_BOOT_DATA_CFG
138#define OTP_CTRL_PARAM_CREATOR_SW_CFG_FLASH_INFO_BOOT_DATA_CFG_SIZE 4
139
140// Offset of CREATOR_SW_CFG_FLASH_HW_INFO_CFG_OVERRIDE
141#define OTP_CTRL_PARAM_CREATOR_SW_CFG_FLASH_HW_INFO_CFG_OVERRIDE_OFFSET 260
142
143// Size of CREATOR_SW_CFG_FLASH_HW_INFO_CFG_OVERRIDE
144#define OTP_CTRL_PARAM_CREATOR_SW_CFG_FLASH_HW_INFO_CFG_OVERRIDE_SIZE 4
145
146// Offset of CREATOR_SW_CFG_RNG_EN
147#define OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_EN_OFFSET 264
148
149// Size of CREATOR_SW_CFG_RNG_EN
150#define OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_EN_SIZE 4
151
152// Offset of CREATOR_SW_CFG_JITTER_EN
153#define OTP_CTRL_PARAM_CREATOR_SW_CFG_JITTER_EN_OFFSET 268
154
155// Size of CREATOR_SW_CFG_JITTER_EN
156#define OTP_CTRL_PARAM_CREATOR_SW_CFG_JITTER_EN_SIZE 4
157
158// Offset of CREATOR_SW_CFG_RET_RAM_RESET_MASK
159#define OTP_CTRL_PARAM_CREATOR_SW_CFG_RET_RAM_RESET_MASK_OFFSET 272
160
161// Size of CREATOR_SW_CFG_RET_RAM_RESET_MASK
162#define OTP_CTRL_PARAM_CREATOR_SW_CFG_RET_RAM_RESET_MASK_SIZE 4
163
164// Offset of CREATOR_SW_CFG_MANUF_STATE
165#define OTP_CTRL_PARAM_CREATOR_SW_CFG_MANUF_STATE_OFFSET 276
166
167// Size of CREATOR_SW_CFG_MANUF_STATE
168#define OTP_CTRL_PARAM_CREATOR_SW_CFG_MANUF_STATE_SIZE 4
169
170// Offset of CREATOR_SW_CFG_ROM_EXEC_EN
171#define OTP_CTRL_PARAM_CREATOR_SW_CFG_ROM_EXEC_EN_OFFSET 280
172
173// Size of CREATOR_SW_CFG_ROM_EXEC_EN
174#define OTP_CTRL_PARAM_CREATOR_SW_CFG_ROM_EXEC_EN_SIZE 4
175
176// Offset of CREATOR_SW_CFG_CPUCTRL
177#define OTP_CTRL_PARAM_CREATOR_SW_CFG_CPUCTRL_OFFSET 284
178
179// Size of CREATOR_SW_CFG_CPUCTRL
180#define OTP_CTRL_PARAM_CREATOR_SW_CFG_CPUCTRL_SIZE 4
181
182// Offset of CREATOR_SW_CFG_MIN_SEC_VER_ROM_EXT
183#define OTP_CTRL_PARAM_CREATOR_SW_CFG_MIN_SEC_VER_ROM_EXT_OFFSET 288
184
185// Size of CREATOR_SW_CFG_MIN_SEC_VER_ROM_EXT
186#define OTP_CTRL_PARAM_CREATOR_SW_CFG_MIN_SEC_VER_ROM_EXT_SIZE 4
187
188// Offset of CREATOR_SW_CFG_MIN_SEC_VER_BL0
189#define OTP_CTRL_PARAM_CREATOR_SW_CFG_MIN_SEC_VER_BL0_OFFSET 292
190
191// Size of CREATOR_SW_CFG_MIN_SEC_VER_BL0
192#define OTP_CTRL_PARAM_CREATOR_SW_CFG_MIN_SEC_VER_BL0_SIZE 4
193
194// Offset of CREATOR_SW_CFG_DEFAULT_BOOT_DATA_IN_PROD_EN
195#define OTP_CTRL_PARAM_CREATOR_SW_CFG_DEFAULT_BOOT_DATA_IN_PROD_EN_OFFSET 296
196
197// Size of CREATOR_SW_CFG_DEFAULT_BOOT_DATA_IN_PROD_EN
198#define OTP_CTRL_PARAM_CREATOR_SW_CFG_DEFAULT_BOOT_DATA_IN_PROD_EN_SIZE 4
199
200// Offset of CREATOR_SW_CFG_RMA_SPIN_EN
201#define OTP_CTRL_PARAM_CREATOR_SW_CFG_RMA_SPIN_EN_OFFSET 300
202
203// Size of CREATOR_SW_CFG_RMA_SPIN_EN
204#define OTP_CTRL_PARAM_CREATOR_SW_CFG_RMA_SPIN_EN_SIZE 4
205
206// Offset of CREATOR_SW_CFG_RMA_SPIN_CYCLES
207#define OTP_CTRL_PARAM_CREATOR_SW_CFG_RMA_SPIN_CYCLES_OFFSET 304
208
209// Size of CREATOR_SW_CFG_RMA_SPIN_CYCLES
210#define OTP_CTRL_PARAM_CREATOR_SW_CFG_RMA_SPIN_CYCLES_SIZE 4
211
212// Offset of CREATOR_SW_CFG_RNG_REPCNT_THRESHOLDS
213#define OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_REPCNT_THRESHOLDS_OFFSET 308
214
215// Size of CREATOR_SW_CFG_RNG_REPCNT_THRESHOLDS
216#define OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_REPCNT_THRESHOLDS_SIZE 4
217
218// Offset of CREATOR_SW_CFG_RNG_REPCNTS_THRESHOLDS
219#define OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_REPCNTS_THRESHOLDS_OFFSET 312
220
221// Size of CREATOR_SW_CFG_RNG_REPCNTS_THRESHOLDS
222#define OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_REPCNTS_THRESHOLDS_SIZE 4
223
224// Offset of CREATOR_SW_CFG_RNG_ADAPTP_HI_THRESHOLDS
225#define OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_ADAPTP_HI_THRESHOLDS_OFFSET 316
226
227// Size of CREATOR_SW_CFG_RNG_ADAPTP_HI_THRESHOLDS
228#define OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_ADAPTP_HI_THRESHOLDS_SIZE 4
229
230// Offset of CREATOR_SW_CFG_RNG_ADAPTP_LO_THRESHOLDS
231#define OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_ADAPTP_LO_THRESHOLDS_OFFSET 320
232
233// Size of CREATOR_SW_CFG_RNG_ADAPTP_LO_THRESHOLDS
234#define OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_ADAPTP_LO_THRESHOLDS_SIZE 4
235
236// Offset of CREATOR_SW_CFG_RNG_BUCKET_THRESHOLDS
237#define OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_BUCKET_THRESHOLDS_OFFSET 324
238
239// Size of CREATOR_SW_CFG_RNG_BUCKET_THRESHOLDS
240#define OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_BUCKET_THRESHOLDS_SIZE 4
241
242// Offset of CREATOR_SW_CFG_RNG_MARKOV_HI_THRESHOLDS
243#define OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_MARKOV_HI_THRESHOLDS_OFFSET 328
244
245// Size of CREATOR_SW_CFG_RNG_MARKOV_HI_THRESHOLDS
246#define OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_MARKOV_HI_THRESHOLDS_SIZE 4
247
248// Offset of CREATOR_SW_CFG_RNG_MARKOV_LO_THRESHOLDS
249#define OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_MARKOV_LO_THRESHOLDS_OFFSET 332
250
251// Size of CREATOR_SW_CFG_RNG_MARKOV_LO_THRESHOLDS
252#define OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_MARKOV_LO_THRESHOLDS_SIZE 4
253
254// Offset of CREATOR_SW_CFG_RNG_EXTHT_HI_THRESHOLDS
255#define OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_EXTHT_HI_THRESHOLDS_OFFSET 336
256
257// Size of CREATOR_SW_CFG_RNG_EXTHT_HI_THRESHOLDS
258#define OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_EXTHT_HI_THRESHOLDS_SIZE 4
259
260// Offset of CREATOR_SW_CFG_RNG_EXTHT_LO_THRESHOLDS
261#define OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_EXTHT_LO_THRESHOLDS_OFFSET 340
262
263// Size of CREATOR_SW_CFG_RNG_EXTHT_LO_THRESHOLDS
264#define OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_EXTHT_LO_THRESHOLDS_SIZE 4
265
266// Offset of CREATOR_SW_CFG_RNG_ALERT_THRESHOLD
267#define OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_ALERT_THRESHOLD_OFFSET 344
268
269// Size of CREATOR_SW_CFG_RNG_ALERT_THRESHOLD
270#define OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_ALERT_THRESHOLD_SIZE 4
271
272// Offset of CREATOR_SW_CFG_RNG_HEALTH_CONFIG_DIGEST
273#define OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_HEALTH_CONFIG_DIGEST_OFFSET 348
274
275// Size of CREATOR_SW_CFG_RNG_HEALTH_CONFIG_DIGEST
276#define OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_HEALTH_CONFIG_DIGEST_SIZE 4
277
278// Offset of CREATOR_SW_CFG_SRAM_KEY_RENEW_EN
279#define OTP_CTRL_PARAM_CREATOR_SW_CFG_SRAM_KEY_RENEW_EN_OFFSET 352
280
281// Size of CREATOR_SW_CFG_SRAM_KEY_RENEW_EN
282#define OTP_CTRL_PARAM_CREATOR_SW_CFG_SRAM_KEY_RENEW_EN_SIZE 4
283
284// Offset of CREATOR_SW_CFG_DIGEST
285#define OTP_CTRL_PARAM_CREATOR_SW_CFG_DIGEST_OFFSET 360
286
287// Size of CREATOR_SW_CFG_DIGEST
288#define OTP_CTRL_PARAM_CREATOR_SW_CFG_DIGEST_SIZE 8
289
290// Offset of the OWNER_SW_CFG partition
291#define OTP_CTRL_PARAM_OWNER_SW_CFG_OFFSET 368
292
293// Size of the OWNER_SW_CFG partition
294#define OTP_CTRL_PARAM_OWNER_SW_CFG_SIZE 600
295
296// Offset of OWNER_SW_CFG_ROM_ERROR_REPORTING
297#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_ERROR_REPORTING_OFFSET 368
298
299// Size of OWNER_SW_CFG_ROM_ERROR_REPORTING
300#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_ERROR_REPORTING_SIZE 4
301
302// Offset of OWNER_SW_CFG_ROM_BOOTSTRAP_DIS
303#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_BOOTSTRAP_DIS_OFFSET 372
304
305// Size of OWNER_SW_CFG_ROM_BOOTSTRAP_DIS
306#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_BOOTSTRAP_DIS_SIZE 4
307
308// Offset of OWNER_SW_CFG_ROM_ALERT_CLASS_EN
309#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_ALERT_CLASS_EN_OFFSET 376
310
311// Size of OWNER_SW_CFG_ROM_ALERT_CLASS_EN
312#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_ALERT_CLASS_EN_SIZE 4
313
314// Offset of OWNER_SW_CFG_ROM_ALERT_ESCALATION
315#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_ALERT_ESCALATION_OFFSET 380
316
317// Size of OWNER_SW_CFG_ROM_ALERT_ESCALATION
318#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_ALERT_ESCALATION_SIZE 4
319
320// Offset of OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION
321#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION_OFFSET 384
322
323// Size of OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION
324#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION_SIZE 420
325
326// Offset of OWNER_SW_CFG_ROM_LOCAL_ALERT_CLASSIFICATION
327#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_LOCAL_ALERT_CLASSIFICATION_OFFSET 804
328
329// Size of OWNER_SW_CFG_ROM_LOCAL_ALERT_CLASSIFICATION
330#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_LOCAL_ALERT_CLASSIFICATION_SIZE 28
331
332// Offset of OWNER_SW_CFG_ROM_ALERT_ACCUM_THRESH
333#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_ALERT_ACCUM_THRESH_OFFSET 832
334
335// Size of OWNER_SW_CFG_ROM_ALERT_ACCUM_THRESH
336#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_ALERT_ACCUM_THRESH_SIZE 16
337
338// Offset of OWNER_SW_CFG_ROM_ALERT_TIMEOUT_CYCLES
339#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_ALERT_TIMEOUT_CYCLES_OFFSET 848
340
341// Size of OWNER_SW_CFG_ROM_ALERT_TIMEOUT_CYCLES
342#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_ALERT_TIMEOUT_CYCLES_SIZE 16
343
344// Offset of OWNER_SW_CFG_ROM_ALERT_PHASE_CYCLES
345#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_ALERT_PHASE_CYCLES_OFFSET 864
346
347// Size of OWNER_SW_CFG_ROM_ALERT_PHASE_CYCLES
348#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_ALERT_PHASE_CYCLES_SIZE 64
349
350// Offset of OWNER_SW_CFG_ROM_ALERT_DIGEST_PROD
351#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_ALERT_DIGEST_PROD_OFFSET 928
352
353// Size of OWNER_SW_CFG_ROM_ALERT_DIGEST_PROD
354#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_ALERT_DIGEST_PROD_SIZE 4
355
356// Offset of OWNER_SW_CFG_ROM_ALERT_DIGEST_PROD_END
357#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_ALERT_DIGEST_PROD_END_OFFSET 932
358
359// Size of OWNER_SW_CFG_ROM_ALERT_DIGEST_PROD_END
360#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_ALERT_DIGEST_PROD_END_SIZE 4
361
362// Offset of OWNER_SW_CFG_ROM_ALERT_DIGEST_DEV
363#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_ALERT_DIGEST_DEV_OFFSET 936
364
365// Size of OWNER_SW_CFG_ROM_ALERT_DIGEST_DEV
366#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_ALERT_DIGEST_DEV_SIZE 4
367
368// Offset of OWNER_SW_CFG_ROM_ALERT_DIGEST_RMA
369#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_ALERT_DIGEST_RMA_OFFSET 940
370
371// Size of OWNER_SW_CFG_ROM_ALERT_DIGEST_RMA
372#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_ALERT_DIGEST_RMA_SIZE 4
373
374// Offset of OWNER_SW_CFG_ROM_WATCHDOG_BITE_THRESHOLD_CYCLES
375#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_WATCHDOG_BITE_THRESHOLD_CYCLES_OFFSET \
376 944
377
378// Size of OWNER_SW_CFG_ROM_WATCHDOG_BITE_THRESHOLD_CYCLES
379#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_WATCHDOG_BITE_THRESHOLD_CYCLES_SIZE 4
380
381// Offset of OWNER_SW_CFG_ROM_KEYMGR_ROM_EXT_MEAS_EN
382#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_KEYMGR_ROM_EXT_MEAS_EN_OFFSET 948
383
384// Size of OWNER_SW_CFG_ROM_KEYMGR_ROM_EXT_MEAS_EN
385#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_KEYMGR_ROM_EXT_MEAS_EN_SIZE 4
386
387// Offset of OWNER_SW_CFG_MANUF_STATE
388#define OTP_CTRL_PARAM_OWNER_SW_CFG_MANUF_STATE_OFFSET 952
389
390// Size of OWNER_SW_CFG_MANUF_STATE
391#define OTP_CTRL_PARAM_OWNER_SW_CFG_MANUF_STATE_SIZE 4
392
393// Offset of OWNER_SW_CFG_ROM_RSTMGR_INFO_EN
394#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_RSTMGR_INFO_EN_OFFSET 956
395
396// Size of OWNER_SW_CFG_ROM_RSTMGR_INFO_EN
397#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_RSTMGR_INFO_EN_SIZE 4
398
399// Offset of OWNER_SW_CFG_DIGEST
400#define OTP_CTRL_PARAM_OWNER_SW_CFG_DIGEST_OFFSET 960
401
402// Size of OWNER_SW_CFG_DIGEST
403#define OTP_CTRL_PARAM_OWNER_SW_CFG_DIGEST_SIZE 8
404
405// Offset of the OWNERSHIP_SLOT_STATE partition
406#define OTP_CTRL_PARAM_OWNERSHIP_SLOT_STATE_OFFSET 968
407
408// Size of the OWNERSHIP_SLOT_STATE partition
409#define OTP_CTRL_PARAM_OWNERSHIP_SLOT_STATE_SIZE 48
410
411// Offset of OWNERSHIP_SLOT_STATE_ROT_OWNER_AUTH
412#define OTP_CTRL_PARAM_OWNERSHIP_SLOT_STATE_ROT_OWNER_AUTH_OFFSET 968
413
414// Size of OWNERSHIP_SLOT_STATE_ROT_OWNER_AUTH
415#define OTP_CTRL_PARAM_OWNERSHIP_SLOT_STATE_ROT_OWNER_AUTH_SIZE 16
416
417// Offset of OWNERSHIP_SLOT_STATE_PLAT_INTEG_AUTH
418#define OTP_CTRL_PARAM_OWNERSHIP_SLOT_STATE_PLAT_INTEG_AUTH_OFFSET 984
419
420// Size of OWNERSHIP_SLOT_STATE_PLAT_INTEG_AUTH
421#define OTP_CTRL_PARAM_OWNERSHIP_SLOT_STATE_PLAT_INTEG_AUTH_SIZE 16
422
423// Offset of OWNERSHIP_SLOT_STATE_PLAT_OWNER_AUTH
424#define OTP_CTRL_PARAM_OWNERSHIP_SLOT_STATE_PLAT_OWNER_AUTH_OFFSET 1000
425
426// Size of OWNERSHIP_SLOT_STATE_PLAT_OWNER_AUTH
427#define OTP_CTRL_PARAM_OWNERSHIP_SLOT_STATE_PLAT_OWNER_AUTH_SIZE 16
428
429// Offset of the ROT_CREATOR_AUTH partition
430#define OTP_CTRL_PARAM_ROT_CREATOR_AUTH_OFFSET 1016
431
432// Size of the ROT_CREATOR_AUTH partition
433#define OTP_CTRL_PARAM_ROT_CREATOR_AUTH_SIZE 1424
434
435// Offset of ROT_CREATOR_AUTH_NON_RAW_MFW_CODESIGN_KEY
436#define OTP_CTRL_PARAM_ROT_CREATOR_AUTH_NON_RAW_MFW_CODESIGN_KEY_OFFSET 1016
437
438// Size of ROT_CREATOR_AUTH_NON_RAW_MFW_CODESIGN_KEY
439#define OTP_CTRL_PARAM_ROT_CREATOR_AUTH_NON_RAW_MFW_CODESIGN_KEY_SIZE 160
440
441// Offset of ROT_CREATOR_AUTH_OWNERSHIP_STATE
442#define OTP_CTRL_PARAM_ROT_CREATOR_AUTH_OWNERSHIP_STATE_OFFSET 1176
443
444// Size of ROT_CREATOR_AUTH_OWNERSHIP_STATE
445#define OTP_CTRL_PARAM_ROT_CREATOR_AUTH_OWNERSHIP_STATE_SIZE 4
446
447// Offset of ROT_CREATOR_AUTH_ROM2_PATCH_SIGVERIFY_KEY
448#define OTP_CTRL_PARAM_ROT_CREATOR_AUTH_ROM2_PATCH_SIGVERIFY_KEY_OFFSET 1180
449
450// Size of ROT_CREATOR_AUTH_ROM2_PATCH_SIGVERIFY_KEY
451#define OTP_CTRL_PARAM_ROT_CREATOR_AUTH_ROM2_PATCH_SIGVERIFY_KEY_SIZE 160
452
453// Offset of ROT_CREATOR_AUTH_KEYMANIFEST_KEY
454#define OTP_CTRL_PARAM_ROT_CREATOR_AUTH_KEYMANIFEST_KEY_OFFSET 1340
455
456// Size of ROT_CREATOR_AUTH_KEYMANIFEST_KEY
457#define OTP_CTRL_PARAM_ROT_CREATOR_AUTH_KEYMANIFEST_KEY_SIZE 160
458
459// Offset of ROT_CREATOR_AUTH_UNLOCK4XFER_KEY
460#define OTP_CTRL_PARAM_ROT_CREATOR_AUTH_UNLOCK4XFER_KEY_OFFSET 1500
461
462// Size of ROT_CREATOR_AUTH_UNLOCK4XFER_KEY
463#define OTP_CTRL_PARAM_ROT_CREATOR_AUTH_UNLOCK4XFER_KEY_SIZE 160
464
465// Offset of ROT_CREATOR_AUTH_IDENTITY_CERT
466#define OTP_CTRL_PARAM_ROT_CREATOR_AUTH_IDENTITY_CERT_OFFSET 1660
467
468// Size of ROT_CREATOR_AUTH_IDENTITY_CERT
469#define OTP_CTRL_PARAM_ROT_CREATOR_AUTH_IDENTITY_CERT_SIZE 768
470
471// Offset of ROT_CREATOR_AUTH_DIGEST
472#define OTP_CTRL_PARAM_ROT_CREATOR_AUTH_DIGEST_OFFSET 2432
473
474// Size of ROT_CREATOR_AUTH_DIGEST
475#define OTP_CTRL_PARAM_ROT_CREATOR_AUTH_DIGEST_SIZE 8
476
477// Offset of the ROT_OWNER_AUTH_SLOT0 partition
478#define OTP_CTRL_PARAM_ROT_OWNER_AUTH_SLOT0_OFFSET 2440
479
480// Size of the ROT_OWNER_AUTH_SLOT0 partition
481#define OTP_CTRL_PARAM_ROT_OWNER_AUTH_SLOT0_SIZE 328
482
483// Offset of ROT_OWNER_AUTH_SLOT0_KEYMANIFEST_KEY
484#define OTP_CTRL_PARAM_ROT_OWNER_AUTH_SLOT0_KEYMANIFEST_KEY_OFFSET 2440
485
486// Size of ROT_OWNER_AUTH_SLOT0_KEYMANIFEST_KEY
487#define OTP_CTRL_PARAM_ROT_OWNER_AUTH_SLOT0_KEYMANIFEST_KEY_SIZE 160
488
489// Offset of ROT_OWNER_AUTH_SLOT0_UNLOCK4XFER_KEY
490#define OTP_CTRL_PARAM_ROT_OWNER_AUTH_SLOT0_UNLOCK4XFER_KEY_OFFSET 2600
491
492// Size of ROT_OWNER_AUTH_SLOT0_UNLOCK4XFER_KEY
493#define OTP_CTRL_PARAM_ROT_OWNER_AUTH_SLOT0_UNLOCK4XFER_KEY_SIZE 160
494
495// Offset of ROT_OWNER_AUTH_SLOT0_DIGEST
496#define OTP_CTRL_PARAM_ROT_OWNER_AUTH_SLOT0_DIGEST_OFFSET 2760
497
498// Size of ROT_OWNER_AUTH_SLOT0_DIGEST
499#define OTP_CTRL_PARAM_ROT_OWNER_AUTH_SLOT0_DIGEST_SIZE 8
500
501// Offset of the ROT_OWNER_AUTH_SLOT1 partition
502#define OTP_CTRL_PARAM_ROT_OWNER_AUTH_SLOT1_OFFSET 2768
503
504// Size of the ROT_OWNER_AUTH_SLOT1 partition
505#define OTP_CTRL_PARAM_ROT_OWNER_AUTH_SLOT1_SIZE 328
506
507// Offset of ROT_OWNER_AUTH_SLOT1_KEYMANIFEST_KEY
508#define OTP_CTRL_PARAM_ROT_OWNER_AUTH_SLOT1_KEYMANIFEST_KEY_OFFSET 2768
509
510// Size of ROT_OWNER_AUTH_SLOT1_KEYMANIFEST_KEY
511#define OTP_CTRL_PARAM_ROT_OWNER_AUTH_SLOT1_KEYMANIFEST_KEY_SIZE 160
512
513// Offset of ROT_OWNER_AUTH_SLOT1_UNLOCK4XFER_KEY
514#define OTP_CTRL_PARAM_ROT_OWNER_AUTH_SLOT1_UNLOCK4XFER_KEY_OFFSET 2928
515
516// Size of ROT_OWNER_AUTH_SLOT1_UNLOCK4XFER_KEY
517#define OTP_CTRL_PARAM_ROT_OWNER_AUTH_SLOT1_UNLOCK4XFER_KEY_SIZE 160
518
519// Offset of ROT_OWNER_AUTH_SLOT1_DIGEST
520#define OTP_CTRL_PARAM_ROT_OWNER_AUTH_SLOT1_DIGEST_OFFSET 3088
521
522// Size of ROT_OWNER_AUTH_SLOT1_DIGEST
523#define OTP_CTRL_PARAM_ROT_OWNER_AUTH_SLOT1_DIGEST_SIZE 8
524
525// Offset of the PLAT_INTEG_AUTH_SLOT0 partition
526#define OTP_CTRL_PARAM_PLAT_INTEG_AUTH_SLOT0_OFFSET 3096
527
528// Size of the PLAT_INTEG_AUTH_SLOT0 partition
529#define OTP_CTRL_PARAM_PLAT_INTEG_AUTH_SLOT0_SIZE 328
530
531// Offset of PLAT_INTEG_AUTH_SLOT0_KEYMANIFEST_KEY
532#define OTP_CTRL_PARAM_PLAT_INTEG_AUTH_SLOT0_KEYMANIFEST_KEY_OFFSET 3096
533
534// Size of PLAT_INTEG_AUTH_SLOT0_KEYMANIFEST_KEY
535#define OTP_CTRL_PARAM_PLAT_INTEG_AUTH_SLOT0_KEYMANIFEST_KEY_SIZE 160
536
537// Offset of PLAT_INTEG_AUTH_SLOT0_UNLOCK4XFER_KEY
538#define OTP_CTRL_PARAM_PLAT_INTEG_AUTH_SLOT0_UNLOCK4XFER_KEY_OFFSET 3256
539
540// Size of PLAT_INTEG_AUTH_SLOT0_UNLOCK4XFER_KEY
541#define OTP_CTRL_PARAM_PLAT_INTEG_AUTH_SLOT0_UNLOCK4XFER_KEY_SIZE 160
542
543// Offset of PLAT_INTEG_AUTH_SLOT0_DIGEST
544#define OTP_CTRL_PARAM_PLAT_INTEG_AUTH_SLOT0_DIGEST_OFFSET 3416
545
546// Size of PLAT_INTEG_AUTH_SLOT0_DIGEST
547#define OTP_CTRL_PARAM_PLAT_INTEG_AUTH_SLOT0_DIGEST_SIZE 8
548
549// Offset of the PLAT_INTEG_AUTH_SLOT1 partition
550#define OTP_CTRL_PARAM_PLAT_INTEG_AUTH_SLOT1_OFFSET 3424
551
552// Size of the PLAT_INTEG_AUTH_SLOT1 partition
553#define OTP_CTRL_PARAM_PLAT_INTEG_AUTH_SLOT1_SIZE 328
554
555// Offset of PLAT_INTEG_AUTH_SLOT1_KEYMANIFEST_KEY
556#define OTP_CTRL_PARAM_PLAT_INTEG_AUTH_SLOT1_KEYMANIFEST_KEY_OFFSET 3424
557
558// Size of PLAT_INTEG_AUTH_SLOT1_KEYMANIFEST_KEY
559#define OTP_CTRL_PARAM_PLAT_INTEG_AUTH_SLOT1_KEYMANIFEST_KEY_SIZE 160
560
561// Offset of PLAT_INTEG_AUTH_SLOT1_UNLOCK4XFER_KEY
562#define OTP_CTRL_PARAM_PLAT_INTEG_AUTH_SLOT1_UNLOCK4XFER_KEY_OFFSET 3584
563
564// Size of PLAT_INTEG_AUTH_SLOT1_UNLOCK4XFER_KEY
565#define OTP_CTRL_PARAM_PLAT_INTEG_AUTH_SLOT1_UNLOCK4XFER_KEY_SIZE 160
566
567// Offset of PLAT_INTEG_AUTH_SLOT1_DIGEST
568#define OTP_CTRL_PARAM_PLAT_INTEG_AUTH_SLOT1_DIGEST_OFFSET 3744
569
570// Size of PLAT_INTEG_AUTH_SLOT1_DIGEST
571#define OTP_CTRL_PARAM_PLAT_INTEG_AUTH_SLOT1_DIGEST_SIZE 8
572
573// Offset of the PLAT_OWNER_AUTH_SLOT0 partition
574#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT0_OFFSET 3752
575
576// Size of the PLAT_OWNER_AUTH_SLOT0 partition
577#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT0_SIZE 328
578
579// Offset of PLAT_OWNER_AUTH_SLOT0_KEYMANIFEST_KEY
580#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT0_KEYMANIFEST_KEY_OFFSET 3752
581
582// Size of PLAT_OWNER_AUTH_SLOT0_KEYMANIFEST_KEY
583#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT0_KEYMANIFEST_KEY_SIZE 160
584
585// Offset of PLAT_OWNER_AUTH_SLOT0_UNLOCK4XFER_KEY
586#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT0_UNLOCK4XFER_KEY_OFFSET 3912
587
588// Size of PLAT_OWNER_AUTH_SLOT0_UNLOCK4XFER_KEY
589#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT0_UNLOCK4XFER_KEY_SIZE 160
590
591// Offset of PLAT_OWNER_AUTH_SLOT0_DIGEST
592#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT0_DIGEST_OFFSET 4072
593
594// Size of PLAT_OWNER_AUTH_SLOT0_DIGEST
595#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT0_DIGEST_SIZE 8
596
597// Offset of the PLAT_OWNER_AUTH_SLOT1 partition
598#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT1_OFFSET 4080
599
600// Size of the PLAT_OWNER_AUTH_SLOT1 partition
601#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT1_SIZE 328
602
603// Offset of PLAT_OWNER_AUTH_SLOT1_KEYMANIFEST_KEY
604#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT1_KEYMANIFEST_KEY_OFFSET 4080
605
606// Size of PLAT_OWNER_AUTH_SLOT1_KEYMANIFEST_KEY
607#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT1_KEYMANIFEST_KEY_SIZE 160
608
609// Offset of PLAT_OWNER_AUTH_SLOT1_UNLOCK4XFER_KEY
610#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT1_UNLOCK4XFER_KEY_OFFSET 4240
611
612// Size of PLAT_OWNER_AUTH_SLOT1_UNLOCK4XFER_KEY
613#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT1_UNLOCK4XFER_KEY_SIZE 160
614
615// Offset of PLAT_OWNER_AUTH_SLOT1_DIGEST
616#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT1_DIGEST_OFFSET 4400
617
618// Size of PLAT_OWNER_AUTH_SLOT1_DIGEST
619#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT1_DIGEST_SIZE 8
620
621// Offset of the PLAT_OWNER_AUTH_SLOT2 partition
622#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT2_OFFSET 4408
623
624// Size of the PLAT_OWNER_AUTH_SLOT2 partition
625#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT2_SIZE 328
626
627// Offset of PLAT_OWNER_AUTH_SLOT2_KEYMANIFEST_KEY
628#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT2_KEYMANIFEST_KEY_OFFSET 4408
629
630// Size of PLAT_OWNER_AUTH_SLOT2_KEYMANIFEST_KEY
631#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT2_KEYMANIFEST_KEY_SIZE 160
632
633// Offset of PLAT_OWNER_AUTH_SLOT2_UNLOCK4XFER_KEY
634#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT2_UNLOCK4XFER_KEY_OFFSET 4568
635
636// Size of PLAT_OWNER_AUTH_SLOT2_UNLOCK4XFER_KEY
637#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT2_UNLOCK4XFER_KEY_SIZE 160
638
639// Offset of PLAT_OWNER_AUTH_SLOT2_DIGEST
640#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT2_DIGEST_OFFSET 4728
641
642// Size of PLAT_OWNER_AUTH_SLOT2_DIGEST
643#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT2_DIGEST_SIZE 8
644
645// Offset of the PLAT_OWNER_AUTH_SLOT3 partition
646#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT3_OFFSET 4736
647
648// Size of the PLAT_OWNER_AUTH_SLOT3 partition
649#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT3_SIZE 328
650
651// Offset of PLAT_OWNER_AUTH_SLOT3_KEYMANIFEST_KEY
652#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT3_KEYMANIFEST_KEY_OFFSET 4736
653
654// Size of PLAT_OWNER_AUTH_SLOT3_KEYMANIFEST_KEY
655#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT3_KEYMANIFEST_KEY_SIZE 160
656
657// Offset of PLAT_OWNER_AUTH_SLOT3_UNLOCK4XFER_KEY
658#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT3_UNLOCK4XFER_KEY_OFFSET 4896
659
660// Size of PLAT_OWNER_AUTH_SLOT3_UNLOCK4XFER_KEY
661#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT3_UNLOCK4XFER_KEY_SIZE 160
662
663// Offset of PLAT_OWNER_AUTH_SLOT3_DIGEST
664#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT3_DIGEST_OFFSET 5056
665
666// Size of PLAT_OWNER_AUTH_SLOT3_DIGEST
667#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT3_DIGEST_SIZE 8
668
669// Offset of the EXT_NVM partition
670#define OTP_CTRL_PARAM_EXT_NVM_OFFSET 5064
671
672// Size of the EXT_NVM partition
673#define OTP_CTRL_PARAM_EXT_NVM_SIZE 1024
674
675// Offset of EXT_NVM_ANTIREPLAY_FRESHNESS_CNT
676#define OTP_CTRL_PARAM_EXT_NVM_ANTIREPLAY_FRESHNESS_CNT_OFFSET 5064
677
678// Size of EXT_NVM_ANTIREPLAY_FRESHNESS_CNT
679#define OTP_CTRL_PARAM_EXT_NVM_ANTIREPLAY_FRESHNESS_CNT_SIZE 1024
680
681// Offset of the ROM_PATCH partition
682#define OTP_CTRL_PARAM_ROM_PATCH_OFFSET 6088
683
684// Size of the ROM_PATCH partition
685#define OTP_CTRL_PARAM_ROM_PATCH_SIZE 9864
686
687// Offset of ROM_PATCH_DATA
688#define OTP_CTRL_PARAM_ROM_PATCH_DATA_OFFSET 6088
689
690// Size of ROM_PATCH_DATA
691#define OTP_CTRL_PARAM_ROM_PATCH_DATA_SIZE 9192
692
693// Offset of ROM_PATCH_DIGEST
694#define OTP_CTRL_PARAM_ROM_PATCH_DIGEST_OFFSET 15944
695
696// Size of ROM_PATCH_DIGEST
697#define OTP_CTRL_PARAM_ROM_PATCH_DIGEST_SIZE 8
698
699// Offset of the HW_CFG0 partition
700#define OTP_CTRL_PARAM_HW_CFG0_OFFSET 15952
701
702// Size of the HW_CFG0 partition
703#define OTP_CTRL_PARAM_HW_CFG0_SIZE 72
704
705// Offset of DEVICE_ID
706#define OTP_CTRL_PARAM_DEVICE_ID_OFFSET 15952
707
708// Size of DEVICE_ID
709#define OTP_CTRL_PARAM_DEVICE_ID_SIZE 32
710
711// Offset of MANUF_STATE
712#define OTP_CTRL_PARAM_MANUF_STATE_OFFSET 15984
713
714// Size of MANUF_STATE
715#define OTP_CTRL_PARAM_MANUF_STATE_SIZE 32
716
717// Offset of HW_CFG0_DIGEST
718#define OTP_CTRL_PARAM_HW_CFG0_DIGEST_OFFSET 16016
719
720// Size of HW_CFG0_DIGEST
721#define OTP_CTRL_PARAM_HW_CFG0_DIGEST_SIZE 8
722
723// Offset of the HW_CFG1 partition
724#define OTP_CTRL_PARAM_HW_CFG1_OFFSET 16024
725
726// Size of the HW_CFG1 partition
727#define OTP_CTRL_PARAM_HW_CFG1_SIZE 16
728
729// Offset of SOC_DBG_STATE
730#define OTP_CTRL_PARAM_SOC_DBG_STATE_OFFSET 16024
731
732// Size of SOC_DBG_STATE
733#define OTP_CTRL_PARAM_SOC_DBG_STATE_SIZE 4
734
735// Offset of EN_CSRNG_SW_APP_READ
736#define OTP_CTRL_PARAM_EN_CSRNG_SW_APP_READ_OFFSET 16028
737
738// Size of EN_CSRNG_SW_APP_READ
739#define OTP_CTRL_PARAM_EN_CSRNG_SW_APP_READ_SIZE 1
740
741// Offset of EN_SRAM_IFETCH
742#define OTP_CTRL_PARAM_EN_SRAM_IFETCH_OFFSET 16029
743
744// Size of EN_SRAM_IFETCH
745#define OTP_CTRL_PARAM_EN_SRAM_IFETCH_SIZE 1
746
747// Offset of HW_CFG1_DIGEST
748#define OTP_CTRL_PARAM_HW_CFG1_DIGEST_OFFSET 16032
749
750// Size of HW_CFG1_DIGEST
751#define OTP_CTRL_PARAM_HW_CFG1_DIGEST_SIZE 8
752
753// Offset of the SECRET0 partition
754#define OTP_CTRL_PARAM_SECRET0_OFFSET 16040
755
756// Size of the SECRET0 partition
757#define OTP_CTRL_PARAM_SECRET0_SIZE 48
758
759// Offset of TEST_UNLOCK_TOKEN
760#define OTP_CTRL_PARAM_TEST_UNLOCK_TOKEN_OFFSET 16040
761
762// Size of TEST_UNLOCK_TOKEN
763#define OTP_CTRL_PARAM_TEST_UNLOCK_TOKEN_SIZE 16
764
765// Offset of TEST_EXIT_TOKEN
766#define OTP_CTRL_PARAM_TEST_EXIT_TOKEN_OFFSET 16056
767
768// Size of TEST_EXIT_TOKEN
769#define OTP_CTRL_PARAM_TEST_EXIT_TOKEN_SIZE 16
770
771// Offset of SECRET0_DIGEST
772#define OTP_CTRL_PARAM_SECRET0_DIGEST_OFFSET 16072
773
774// Size of SECRET0_DIGEST
775#define OTP_CTRL_PARAM_SECRET0_DIGEST_SIZE 8
776
777// Offset of SECRET0_ZER
778#define OTP_CTRL_PARAM_SECRET0_ZER_OFFSET 16080
779
780// Size of SECRET0_ZER
781#define OTP_CTRL_PARAM_SECRET0_ZER_SIZE 8
782
783// Offset of the SECRET1 partition
784#define OTP_CTRL_PARAM_SECRET1_OFFSET 16088
785
786// Size of the SECRET1 partition
787#define OTP_CTRL_PARAM_SECRET1_SIZE 32
788
789// Offset of SRAM_DATA_KEY_SEED
790#define OTP_CTRL_PARAM_SRAM_DATA_KEY_SEED_OFFSET 16088
791
792// Size of SRAM_DATA_KEY_SEED
793#define OTP_CTRL_PARAM_SRAM_DATA_KEY_SEED_SIZE 16
794
795// Offset of SECRET1_DIGEST
796#define OTP_CTRL_PARAM_SECRET1_DIGEST_OFFSET 16104
797
798// Size of SECRET1_DIGEST
799#define OTP_CTRL_PARAM_SECRET1_DIGEST_SIZE 8
800
801// Offset of SECRET1_ZER
802#define OTP_CTRL_PARAM_SECRET1_ZER_OFFSET 16112
803
804// Size of SECRET1_ZER
805#define OTP_CTRL_PARAM_SECRET1_ZER_SIZE 8
806
807// Offset of the SECRET2 partition
808#define OTP_CTRL_PARAM_SECRET2_OFFSET 16120
809
810// Size of the SECRET2 partition
811#define OTP_CTRL_PARAM_SECRET2_SIZE 128
812
813// Offset of RMA_TOKEN
814#define OTP_CTRL_PARAM_RMA_TOKEN_OFFSET 16120
815
816// Size of RMA_TOKEN
817#define OTP_CTRL_PARAM_RMA_TOKEN_SIZE 16
818
819// Offset of CREATOR_ROOT_KEY_SHARE0
820#define OTP_CTRL_PARAM_CREATOR_ROOT_KEY_SHARE0_OFFSET 16136
821
822// Size of CREATOR_ROOT_KEY_SHARE0
823#define OTP_CTRL_PARAM_CREATOR_ROOT_KEY_SHARE0_SIZE 32
824
825// Offset of CREATOR_ROOT_KEY_SHARE1
826#define OTP_CTRL_PARAM_CREATOR_ROOT_KEY_SHARE1_OFFSET 16168
827
828// Size of CREATOR_ROOT_KEY_SHARE1
829#define OTP_CTRL_PARAM_CREATOR_ROOT_KEY_SHARE1_SIZE 32
830
831// Offset of CREATOR_SEED
832#define OTP_CTRL_PARAM_CREATOR_SEED_OFFSET 16200
833
834// Size of CREATOR_SEED
835#define OTP_CTRL_PARAM_CREATOR_SEED_SIZE 32
836
837// Offset of SECRET2_DIGEST
838#define OTP_CTRL_PARAM_SECRET2_DIGEST_OFFSET 16232
839
840// Size of SECRET2_DIGEST
841#define OTP_CTRL_PARAM_SECRET2_DIGEST_SIZE 8
842
843// Offset of SECRET2_ZER
844#define OTP_CTRL_PARAM_SECRET2_ZER_OFFSET 16240
845
846// Size of SECRET2_ZER
847#define OTP_CTRL_PARAM_SECRET2_ZER_SIZE 8
848
849// Offset of the SECRET3 partition
850#define OTP_CTRL_PARAM_SECRET3_OFFSET 16248
851
852// Size of the SECRET3 partition
853#define OTP_CTRL_PARAM_SECRET3_SIZE 48
854
855// Offset of OWNER_SEED
856#define OTP_CTRL_PARAM_OWNER_SEED_OFFSET 16248
857
858// Size of OWNER_SEED
859#define OTP_CTRL_PARAM_OWNER_SEED_SIZE 32
860
861// Offset of SECRET3_DIGEST
862#define OTP_CTRL_PARAM_SECRET3_DIGEST_OFFSET 16280
863
864// Size of SECRET3_DIGEST
865#define OTP_CTRL_PARAM_SECRET3_DIGEST_SIZE 8
866
867// Offset of SECRET3_ZER
868#define OTP_CTRL_PARAM_SECRET3_ZER_OFFSET 16288
869
870// Size of SECRET3_ZER
871#define OTP_CTRL_PARAM_SECRET3_ZER_SIZE 8
872
873// Offset of the LIFE_CYCLE partition
874#define OTP_CTRL_PARAM_LIFE_CYCLE_OFFSET 16296
875
876// Size of the LIFE_CYCLE partition
877#define OTP_CTRL_PARAM_LIFE_CYCLE_SIZE 88
878
879// Offset of LC_TRANSITION_CNT
880#define OTP_CTRL_PARAM_LC_TRANSITION_CNT_OFFSET 16296
881
882// Size of LC_TRANSITION_CNT
883#define OTP_CTRL_PARAM_LC_TRANSITION_CNT_SIZE 48
884
885// Offset of LC_STATE
886#define OTP_CTRL_PARAM_LC_STATE_OFFSET 16344
887
888// Size of LC_STATE
889#define OTP_CTRL_PARAM_LC_STATE_SIZE 40
890
891// Number of alerts
892#define OTP_CTRL_PARAM_NUM_ALERTS 5
893
894// Register width
895#define OTP_CTRL_PARAM_REG_WIDTH 32
896
897// Common Interrupt Offsets
898#define OTP_CTRL_INTR_COMMON_OTP_OPERATION_DONE_BIT 0
899#define OTP_CTRL_INTR_COMMON_OTP_ERROR_BIT 1
900
901// Interrupt State Register
902#define OTP_CTRL_INTR_STATE_REG_OFFSET 0x0
903#define OTP_CTRL_INTR_STATE_REG_RESVAL 0x0u
904#define OTP_CTRL_INTR_STATE_OTP_OPERATION_DONE_BIT 0
905#define OTP_CTRL_INTR_STATE_OTP_ERROR_BIT 1
906
907// Interrupt Enable Register
908#define OTP_CTRL_INTR_ENABLE_REG_OFFSET 0x4
909#define OTP_CTRL_INTR_ENABLE_REG_RESVAL 0x0u
910#define OTP_CTRL_INTR_ENABLE_OTP_OPERATION_DONE_BIT 0
911#define OTP_CTRL_INTR_ENABLE_OTP_ERROR_BIT 1
912
913// Interrupt Test Register
914#define OTP_CTRL_INTR_TEST_REG_OFFSET 0x8
915#define OTP_CTRL_INTR_TEST_REG_RESVAL 0x0u
916#define OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_BIT 0
917#define OTP_CTRL_INTR_TEST_OTP_ERROR_BIT 1
918
919// Alert Test Register
920#define OTP_CTRL_ALERT_TEST_REG_OFFSET 0xc
921#define OTP_CTRL_ALERT_TEST_REG_RESVAL 0x0u
922#define OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_BIT 0
923#define OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_BIT 1
924#define OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_BIT 2
925#define OTP_CTRL_ALERT_TEST_FATAL_PRIM_OTP_ALERT_BIT 3
926#define OTP_CTRL_ALERT_TEST_RECOV_PRIM_OTP_ALERT_BIT 4
927
928// OTP status register.
929#define OTP_CTRL_STATUS_REG_OFFSET 0x10
930#define OTP_CTRL_STATUS_REG_RESVAL 0x0u
931#define OTP_CTRL_STATUS_VENDOR_TEST_ERROR_BIT 0
932#define OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_BIT 1
933#define OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_BIT 2
934#define OTP_CTRL_STATUS_OWNERSHIP_SLOT_STATE_ERROR_BIT 3
935#define OTP_CTRL_STATUS_ROT_CREATOR_AUTH_ERROR_BIT 4
936#define OTP_CTRL_STATUS_ROT_OWNER_AUTH_SLOT0_ERROR_BIT 5
937#define OTP_CTRL_STATUS_ROT_OWNER_AUTH_SLOT1_ERROR_BIT 6
938#define OTP_CTRL_STATUS_PLAT_INTEG_AUTH_SLOT0_ERROR_BIT 7
939#define OTP_CTRL_STATUS_PLAT_INTEG_AUTH_SLOT1_ERROR_BIT 8
940#define OTP_CTRL_STATUS_PLAT_OWNER_AUTH_SLOT0_ERROR_BIT 9
941#define OTP_CTRL_STATUS_PLAT_OWNER_AUTH_SLOT1_ERROR_BIT 10
942#define OTP_CTRL_STATUS_PLAT_OWNER_AUTH_SLOT2_ERROR_BIT 11
943#define OTP_CTRL_STATUS_PLAT_OWNER_AUTH_SLOT3_ERROR_BIT 12
944#define OTP_CTRL_STATUS_EXT_NVM_ERROR_BIT 13
945#define OTP_CTRL_STATUS_ROM_PATCH_ERROR_BIT 14
946#define OTP_CTRL_STATUS_HW_CFG0_ERROR_BIT 15
947#define OTP_CTRL_STATUS_HW_CFG1_ERROR_BIT 16
948#define OTP_CTRL_STATUS_SECRET0_ERROR_BIT 17
949#define OTP_CTRL_STATUS_SECRET1_ERROR_BIT 18
950#define OTP_CTRL_STATUS_SECRET2_ERROR_BIT 19
951#define OTP_CTRL_STATUS_SECRET3_ERROR_BIT 20
952#define OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_BIT 21
953#define OTP_CTRL_STATUS_DAI_ERROR_BIT 22
954#define OTP_CTRL_STATUS_LCI_ERROR_BIT 23
955#define OTP_CTRL_STATUS_TIMEOUT_ERROR_BIT 24
956#define OTP_CTRL_STATUS_LFSR_FSM_ERROR_BIT 25
957#define OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_BIT 26
958#define OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_BIT 27
959#define OTP_CTRL_STATUS_BUS_INTEG_ERROR_BIT 28
960#define OTP_CTRL_STATUS_DAI_IDLE_BIT 29
961#define OTP_CTRL_STATUS_CHECK_PENDING_BIT 30
962
963// This register holds information about error conditions that occurred in
964// the agents
965#define OTP_CTRL_ERR_CODE_ERR_CODE_FIELD_WIDTH 3
966#define OTP_CTRL_ERR_CODE_MULTIREG_COUNT 24
967
968// This register holds information about error conditions that occurred in
969// the agents
970#define OTP_CTRL_ERR_CODE_0_REG_OFFSET 0x14
971#define OTP_CTRL_ERR_CODE_0_REG_RESVAL 0x0u
972#define OTP_CTRL_ERR_CODE_0_ERR_CODE_0_MASK 0x7u
973#define OTP_CTRL_ERR_CODE_0_ERR_CODE_0_OFFSET 0
974#define OTP_CTRL_ERR_CODE_0_ERR_CODE_0_FIELD \
975 ((bitfield_field32_t) { .mask = OTP_CTRL_ERR_CODE_0_ERR_CODE_0_MASK, .index = OTP_CTRL_ERR_CODE_0_ERR_CODE_0_OFFSET })
976#define OTP_CTRL_ERR_CODE_0_ERR_CODE_0_VALUE_NO_ERROR 0x0
977#define OTP_CTRL_ERR_CODE_0_ERR_CODE_0_VALUE_MACRO_ERROR 0x1
978#define OTP_CTRL_ERR_CODE_0_ERR_CODE_0_VALUE_MACRO_ECC_CORR_ERROR 0x2
979#define OTP_CTRL_ERR_CODE_0_ERR_CODE_0_VALUE_MACRO_ECC_UNCORR_ERROR 0x3
980#define OTP_CTRL_ERR_CODE_0_ERR_CODE_0_VALUE_MACRO_WRITE_BLANK_ERROR 0x4
981#define OTP_CTRL_ERR_CODE_0_ERR_CODE_0_VALUE_ACCESS_ERROR 0x5
982#define OTP_CTRL_ERR_CODE_0_ERR_CODE_0_VALUE_CHECK_FAIL_ERROR 0x6
983#define OTP_CTRL_ERR_CODE_0_ERR_CODE_0_VALUE_FSM_STATE_ERROR 0x7
984
985// This register holds information about error conditions that occurred in
986// the agents
987#define OTP_CTRL_ERR_CODE_1_REG_OFFSET 0x18
988#define OTP_CTRL_ERR_CODE_1_REG_RESVAL 0x0u
989#define OTP_CTRL_ERR_CODE_1_ERR_CODE_1_MASK 0x7u
990#define OTP_CTRL_ERR_CODE_1_ERR_CODE_1_OFFSET 0
991#define OTP_CTRL_ERR_CODE_1_ERR_CODE_1_FIELD \
992 ((bitfield_field32_t) { .mask = OTP_CTRL_ERR_CODE_1_ERR_CODE_1_MASK, .index = OTP_CTRL_ERR_CODE_1_ERR_CODE_1_OFFSET })
993
994// This register holds information about error conditions that occurred in
995// the agents
996#define OTP_CTRL_ERR_CODE_2_REG_OFFSET 0x1c
997#define OTP_CTRL_ERR_CODE_2_REG_RESVAL 0x0u
998#define OTP_CTRL_ERR_CODE_2_ERR_CODE_2_MASK 0x7u
999#define OTP_CTRL_ERR_CODE_2_ERR_CODE_2_OFFSET 0
1000#define OTP_CTRL_ERR_CODE_2_ERR_CODE_2_FIELD \
1001 ((bitfield_field32_t) { .mask = OTP_CTRL_ERR_CODE_2_ERR_CODE_2_MASK, .index = OTP_CTRL_ERR_CODE_2_ERR_CODE_2_OFFSET })
1002
1003// This register holds information about error conditions that occurred in
1004// the agents
1005#define OTP_CTRL_ERR_CODE_3_REG_OFFSET 0x20
1006#define OTP_CTRL_ERR_CODE_3_REG_RESVAL 0x0u
1007#define OTP_CTRL_ERR_CODE_3_ERR_CODE_3_MASK 0x7u
1008#define OTP_CTRL_ERR_CODE_3_ERR_CODE_3_OFFSET 0
1009#define OTP_CTRL_ERR_CODE_3_ERR_CODE_3_FIELD \
1010 ((bitfield_field32_t) { .mask = OTP_CTRL_ERR_CODE_3_ERR_CODE_3_MASK, .index = OTP_CTRL_ERR_CODE_3_ERR_CODE_3_OFFSET })
1011
1012// This register holds information about error conditions that occurred in
1013// the agents
1014#define OTP_CTRL_ERR_CODE_4_REG_OFFSET 0x24
1015#define OTP_CTRL_ERR_CODE_4_REG_RESVAL 0x0u
1016#define OTP_CTRL_ERR_CODE_4_ERR_CODE_4_MASK 0x7u
1017#define OTP_CTRL_ERR_CODE_4_ERR_CODE_4_OFFSET 0
1018#define OTP_CTRL_ERR_CODE_4_ERR_CODE_4_FIELD \
1019 ((bitfield_field32_t) { .mask = OTP_CTRL_ERR_CODE_4_ERR_CODE_4_MASK, .index = OTP_CTRL_ERR_CODE_4_ERR_CODE_4_OFFSET })
1020
1021// This register holds information about error conditions that occurred in
1022// the agents
1023#define OTP_CTRL_ERR_CODE_5_REG_OFFSET 0x28
1024#define OTP_CTRL_ERR_CODE_5_REG_RESVAL 0x0u
1025#define OTP_CTRL_ERR_CODE_5_ERR_CODE_5_MASK 0x7u
1026#define OTP_CTRL_ERR_CODE_5_ERR_CODE_5_OFFSET 0
1027#define OTP_CTRL_ERR_CODE_5_ERR_CODE_5_FIELD \
1028 ((bitfield_field32_t) { .mask = OTP_CTRL_ERR_CODE_5_ERR_CODE_5_MASK, .index = OTP_CTRL_ERR_CODE_5_ERR_CODE_5_OFFSET })
1029
1030// This register holds information about error conditions that occurred in
1031// the agents
1032#define OTP_CTRL_ERR_CODE_6_REG_OFFSET 0x2c
1033#define OTP_CTRL_ERR_CODE_6_REG_RESVAL 0x0u
1034#define OTP_CTRL_ERR_CODE_6_ERR_CODE_6_MASK 0x7u
1035#define OTP_CTRL_ERR_CODE_6_ERR_CODE_6_OFFSET 0
1036#define OTP_CTRL_ERR_CODE_6_ERR_CODE_6_FIELD \
1037 ((bitfield_field32_t) { .mask = OTP_CTRL_ERR_CODE_6_ERR_CODE_6_MASK, .index = OTP_CTRL_ERR_CODE_6_ERR_CODE_6_OFFSET })
1038
1039// This register holds information about error conditions that occurred in
1040// the agents
1041#define OTP_CTRL_ERR_CODE_7_REG_OFFSET 0x30
1042#define OTP_CTRL_ERR_CODE_7_REG_RESVAL 0x0u
1043#define OTP_CTRL_ERR_CODE_7_ERR_CODE_7_MASK 0x7u
1044#define OTP_CTRL_ERR_CODE_7_ERR_CODE_7_OFFSET 0
1045#define OTP_CTRL_ERR_CODE_7_ERR_CODE_7_FIELD \
1046 ((bitfield_field32_t) { .mask = OTP_CTRL_ERR_CODE_7_ERR_CODE_7_MASK, .index = OTP_CTRL_ERR_CODE_7_ERR_CODE_7_OFFSET })
1047
1048// This register holds information about error conditions that occurred in
1049// the agents
1050#define OTP_CTRL_ERR_CODE_8_REG_OFFSET 0x34
1051#define OTP_CTRL_ERR_CODE_8_REG_RESVAL 0x0u
1052#define OTP_CTRL_ERR_CODE_8_ERR_CODE_8_MASK 0x7u
1053#define OTP_CTRL_ERR_CODE_8_ERR_CODE_8_OFFSET 0
1054#define OTP_CTRL_ERR_CODE_8_ERR_CODE_8_FIELD \
1055 ((bitfield_field32_t) { .mask = OTP_CTRL_ERR_CODE_8_ERR_CODE_8_MASK, .index = OTP_CTRL_ERR_CODE_8_ERR_CODE_8_OFFSET })
1056
1057// This register holds information about error conditions that occurred in
1058// the agents
1059#define OTP_CTRL_ERR_CODE_9_REG_OFFSET 0x38
1060#define OTP_CTRL_ERR_CODE_9_REG_RESVAL 0x0u
1061#define OTP_CTRL_ERR_CODE_9_ERR_CODE_9_MASK 0x7u
1062#define OTP_CTRL_ERR_CODE_9_ERR_CODE_9_OFFSET 0
1063#define OTP_CTRL_ERR_CODE_9_ERR_CODE_9_FIELD \
1064 ((bitfield_field32_t) { .mask = OTP_CTRL_ERR_CODE_9_ERR_CODE_9_MASK, .index = OTP_CTRL_ERR_CODE_9_ERR_CODE_9_OFFSET })
1065
1066// This register holds information about error conditions that occurred in
1067// the agents
1068#define OTP_CTRL_ERR_CODE_10_REG_OFFSET 0x3c
1069#define OTP_CTRL_ERR_CODE_10_REG_RESVAL 0x0u
1070#define OTP_CTRL_ERR_CODE_10_ERR_CODE_10_MASK 0x7u
1071#define OTP_CTRL_ERR_CODE_10_ERR_CODE_10_OFFSET 0
1072#define OTP_CTRL_ERR_CODE_10_ERR_CODE_10_FIELD \
1073 ((bitfield_field32_t) { .mask = OTP_CTRL_ERR_CODE_10_ERR_CODE_10_MASK, .index = OTP_CTRL_ERR_CODE_10_ERR_CODE_10_OFFSET })
1074
1075// This register holds information about error conditions that occurred in
1076// the agents
1077#define OTP_CTRL_ERR_CODE_11_REG_OFFSET 0x40
1078#define OTP_CTRL_ERR_CODE_11_REG_RESVAL 0x0u
1079#define OTP_CTRL_ERR_CODE_11_ERR_CODE_11_MASK 0x7u
1080#define OTP_CTRL_ERR_CODE_11_ERR_CODE_11_OFFSET 0
1081#define OTP_CTRL_ERR_CODE_11_ERR_CODE_11_FIELD \
1082 ((bitfield_field32_t) { .mask = OTP_CTRL_ERR_CODE_11_ERR_CODE_11_MASK, .index = OTP_CTRL_ERR_CODE_11_ERR_CODE_11_OFFSET })
1083
1084// This register holds information about error conditions that occurred in
1085// the agents
1086#define OTP_CTRL_ERR_CODE_12_REG_OFFSET 0x44
1087#define OTP_CTRL_ERR_CODE_12_REG_RESVAL 0x0u
1088#define OTP_CTRL_ERR_CODE_12_ERR_CODE_12_MASK 0x7u
1089#define OTP_CTRL_ERR_CODE_12_ERR_CODE_12_OFFSET 0
1090#define OTP_CTRL_ERR_CODE_12_ERR_CODE_12_FIELD \
1091 ((bitfield_field32_t) { .mask = OTP_CTRL_ERR_CODE_12_ERR_CODE_12_MASK, .index = OTP_CTRL_ERR_CODE_12_ERR_CODE_12_OFFSET })
1092
1093// This register holds information about error conditions that occurred in
1094// the agents
1095#define OTP_CTRL_ERR_CODE_13_REG_OFFSET 0x48
1096#define OTP_CTRL_ERR_CODE_13_REG_RESVAL 0x0u
1097#define OTP_CTRL_ERR_CODE_13_ERR_CODE_13_MASK 0x7u
1098#define OTP_CTRL_ERR_CODE_13_ERR_CODE_13_OFFSET 0
1099#define OTP_CTRL_ERR_CODE_13_ERR_CODE_13_FIELD \
1100 ((bitfield_field32_t) { .mask = OTP_CTRL_ERR_CODE_13_ERR_CODE_13_MASK, .index = OTP_CTRL_ERR_CODE_13_ERR_CODE_13_OFFSET })
1101
1102// This register holds information about error conditions that occurred in
1103// the agents
1104#define OTP_CTRL_ERR_CODE_14_REG_OFFSET 0x4c
1105#define OTP_CTRL_ERR_CODE_14_REG_RESVAL 0x0u
1106#define OTP_CTRL_ERR_CODE_14_ERR_CODE_14_MASK 0x7u
1107#define OTP_CTRL_ERR_CODE_14_ERR_CODE_14_OFFSET 0
1108#define OTP_CTRL_ERR_CODE_14_ERR_CODE_14_FIELD \
1109 ((bitfield_field32_t) { .mask = OTP_CTRL_ERR_CODE_14_ERR_CODE_14_MASK, .index = OTP_CTRL_ERR_CODE_14_ERR_CODE_14_OFFSET })
1110
1111// This register holds information about error conditions that occurred in
1112// the agents
1113#define OTP_CTRL_ERR_CODE_15_REG_OFFSET 0x50
1114#define OTP_CTRL_ERR_CODE_15_REG_RESVAL 0x0u
1115#define OTP_CTRL_ERR_CODE_15_ERR_CODE_15_MASK 0x7u
1116#define OTP_CTRL_ERR_CODE_15_ERR_CODE_15_OFFSET 0
1117#define OTP_CTRL_ERR_CODE_15_ERR_CODE_15_FIELD \
1118 ((bitfield_field32_t) { .mask = OTP_CTRL_ERR_CODE_15_ERR_CODE_15_MASK, .index = OTP_CTRL_ERR_CODE_15_ERR_CODE_15_OFFSET })
1119
1120// This register holds information about error conditions that occurred in
1121// the agents
1122#define OTP_CTRL_ERR_CODE_16_REG_OFFSET 0x54
1123#define OTP_CTRL_ERR_CODE_16_REG_RESVAL 0x0u
1124#define OTP_CTRL_ERR_CODE_16_ERR_CODE_16_MASK 0x7u
1125#define OTP_CTRL_ERR_CODE_16_ERR_CODE_16_OFFSET 0
1126#define OTP_CTRL_ERR_CODE_16_ERR_CODE_16_FIELD \
1127 ((bitfield_field32_t) { .mask = OTP_CTRL_ERR_CODE_16_ERR_CODE_16_MASK, .index = OTP_CTRL_ERR_CODE_16_ERR_CODE_16_OFFSET })
1128
1129// This register holds information about error conditions that occurred in
1130// the agents
1131#define OTP_CTRL_ERR_CODE_17_REG_OFFSET 0x58
1132#define OTP_CTRL_ERR_CODE_17_REG_RESVAL 0x0u
1133#define OTP_CTRL_ERR_CODE_17_ERR_CODE_17_MASK 0x7u
1134#define OTP_CTRL_ERR_CODE_17_ERR_CODE_17_OFFSET 0
1135#define OTP_CTRL_ERR_CODE_17_ERR_CODE_17_FIELD \
1136 ((bitfield_field32_t) { .mask = OTP_CTRL_ERR_CODE_17_ERR_CODE_17_MASK, .index = OTP_CTRL_ERR_CODE_17_ERR_CODE_17_OFFSET })
1137
1138// This register holds information about error conditions that occurred in
1139// the agents
1140#define OTP_CTRL_ERR_CODE_18_REG_OFFSET 0x5c
1141#define OTP_CTRL_ERR_CODE_18_REG_RESVAL 0x0u
1142#define OTP_CTRL_ERR_CODE_18_ERR_CODE_18_MASK 0x7u
1143#define OTP_CTRL_ERR_CODE_18_ERR_CODE_18_OFFSET 0
1144#define OTP_CTRL_ERR_CODE_18_ERR_CODE_18_FIELD \
1145 ((bitfield_field32_t) { .mask = OTP_CTRL_ERR_CODE_18_ERR_CODE_18_MASK, .index = OTP_CTRL_ERR_CODE_18_ERR_CODE_18_OFFSET })
1146
1147// This register holds information about error conditions that occurred in
1148// the agents
1149#define OTP_CTRL_ERR_CODE_19_REG_OFFSET 0x60
1150#define OTP_CTRL_ERR_CODE_19_REG_RESVAL 0x0u
1151#define OTP_CTRL_ERR_CODE_19_ERR_CODE_19_MASK 0x7u
1152#define OTP_CTRL_ERR_CODE_19_ERR_CODE_19_OFFSET 0
1153#define OTP_CTRL_ERR_CODE_19_ERR_CODE_19_FIELD \
1154 ((bitfield_field32_t) { .mask = OTP_CTRL_ERR_CODE_19_ERR_CODE_19_MASK, .index = OTP_CTRL_ERR_CODE_19_ERR_CODE_19_OFFSET })
1155
1156// This register holds information about error conditions that occurred in
1157// the agents
1158#define OTP_CTRL_ERR_CODE_20_REG_OFFSET 0x64
1159#define OTP_CTRL_ERR_CODE_20_REG_RESVAL 0x0u
1160#define OTP_CTRL_ERR_CODE_20_ERR_CODE_20_MASK 0x7u
1161#define OTP_CTRL_ERR_CODE_20_ERR_CODE_20_OFFSET 0
1162#define OTP_CTRL_ERR_CODE_20_ERR_CODE_20_FIELD \
1163 ((bitfield_field32_t) { .mask = OTP_CTRL_ERR_CODE_20_ERR_CODE_20_MASK, .index = OTP_CTRL_ERR_CODE_20_ERR_CODE_20_OFFSET })
1164
1165// This register holds information about error conditions that occurred in
1166// the agents
1167#define OTP_CTRL_ERR_CODE_21_REG_OFFSET 0x68
1168#define OTP_CTRL_ERR_CODE_21_REG_RESVAL 0x0u
1169#define OTP_CTRL_ERR_CODE_21_ERR_CODE_21_MASK 0x7u
1170#define OTP_CTRL_ERR_CODE_21_ERR_CODE_21_OFFSET 0
1171#define OTP_CTRL_ERR_CODE_21_ERR_CODE_21_FIELD \
1172 ((bitfield_field32_t) { .mask = OTP_CTRL_ERR_CODE_21_ERR_CODE_21_MASK, .index = OTP_CTRL_ERR_CODE_21_ERR_CODE_21_OFFSET })
1173
1174// This register holds information about error conditions that occurred in
1175// the agents
1176#define OTP_CTRL_ERR_CODE_22_REG_OFFSET 0x6c
1177#define OTP_CTRL_ERR_CODE_22_REG_RESVAL 0x0u
1178#define OTP_CTRL_ERR_CODE_22_ERR_CODE_22_MASK 0x7u
1179#define OTP_CTRL_ERR_CODE_22_ERR_CODE_22_OFFSET 0
1180#define OTP_CTRL_ERR_CODE_22_ERR_CODE_22_FIELD \
1181 ((bitfield_field32_t) { .mask = OTP_CTRL_ERR_CODE_22_ERR_CODE_22_MASK, .index = OTP_CTRL_ERR_CODE_22_ERR_CODE_22_OFFSET })
1182
1183// This register holds information about error conditions that occurred in
1184// the agents
1185#define OTP_CTRL_ERR_CODE_23_REG_OFFSET 0x70
1186#define OTP_CTRL_ERR_CODE_23_REG_RESVAL 0x0u
1187#define OTP_CTRL_ERR_CODE_23_ERR_CODE_23_MASK 0x7u
1188#define OTP_CTRL_ERR_CODE_23_ERR_CODE_23_OFFSET 0
1189#define OTP_CTRL_ERR_CODE_23_ERR_CODE_23_FIELD \
1190 ((bitfield_field32_t) { .mask = OTP_CTRL_ERR_CODE_23_ERR_CODE_23_MASK, .index = OTP_CTRL_ERR_CODE_23_ERR_CODE_23_OFFSET })
1191
1192// Register write enable for all direct access interface registers.
1193#define OTP_CTRL_DIRECT_ACCESS_REGWEN_REG_OFFSET 0x74
1194#define OTP_CTRL_DIRECT_ACCESS_REGWEN_REG_RESVAL 0x1u
1195#define OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_BIT 0
1196
1197// Command register for direct accesses.
1198#define OTP_CTRL_DIRECT_ACCESS_CMD_REG_OFFSET 0x78
1199#define OTP_CTRL_DIRECT_ACCESS_CMD_REG_RESVAL 0x0u
1200#define OTP_CTRL_DIRECT_ACCESS_CMD_RD_BIT 0
1201#define OTP_CTRL_DIRECT_ACCESS_CMD_WR_BIT 1
1202#define OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_BIT 2
1203#define OTP_CTRL_DIRECT_ACCESS_CMD_ZEROIZE_BIT 3
1204
1205// Address register for direct accesses.
1206#define OTP_CTRL_DIRECT_ACCESS_ADDRESS_REG_OFFSET 0x7c
1207#define OTP_CTRL_DIRECT_ACCESS_ADDRESS_REG_RESVAL 0x0u
1208#define OTP_CTRL_DIRECT_ACCESS_ADDRESS_DIRECT_ACCESS_ADDRESS_MASK 0x3fffu
1209#define OTP_CTRL_DIRECT_ACCESS_ADDRESS_DIRECT_ACCESS_ADDRESS_OFFSET 0
1210#define OTP_CTRL_DIRECT_ACCESS_ADDRESS_DIRECT_ACCESS_ADDRESS_FIELD \
1211 ((bitfield_field32_t) { .mask = OTP_CTRL_DIRECT_ACCESS_ADDRESS_DIRECT_ACCESS_ADDRESS_MASK, .index = OTP_CTRL_DIRECT_ACCESS_ADDRESS_DIRECT_ACCESS_ADDRESS_OFFSET })
1212
1213// Write data for direct accesses.
1214#define OTP_CTRL_DIRECT_ACCESS_WDATA_DIRECT_ACCESS_WDATA_FIELD_WIDTH 32
1215#define OTP_CTRL_DIRECT_ACCESS_WDATA_MULTIREG_COUNT 2
1216
1217// Write data for direct accesses.
1218#define OTP_CTRL_DIRECT_ACCESS_WDATA_0_REG_OFFSET 0x80
1219#define OTP_CTRL_DIRECT_ACCESS_WDATA_0_REG_RESVAL 0x0u
1220
1221// Write data for direct accesses.
1222#define OTP_CTRL_DIRECT_ACCESS_WDATA_1_REG_OFFSET 0x84
1223#define OTP_CTRL_DIRECT_ACCESS_WDATA_1_REG_RESVAL 0x0u
1224
1225// Read data for direct accesses.
1226#define OTP_CTRL_DIRECT_ACCESS_RDATA_DIRECT_ACCESS_RDATA_FIELD_WIDTH 32
1227#define OTP_CTRL_DIRECT_ACCESS_RDATA_MULTIREG_COUNT 2
1228
1229// Read data for direct accesses.
1230#define OTP_CTRL_DIRECT_ACCESS_RDATA_0_REG_OFFSET 0x88
1231#define OTP_CTRL_DIRECT_ACCESS_RDATA_0_REG_RESVAL 0x0u
1232
1233// Read data for direct accesses.
1234#define OTP_CTRL_DIRECT_ACCESS_RDATA_1_REG_OFFSET 0x8c
1235#define OTP_CTRL_DIRECT_ACCESS_RDATA_1_REG_RESVAL 0x0u
1236
1237// Register write enable for !!CHECK_TRIGGER.
1238#define OTP_CTRL_CHECK_TRIGGER_REGWEN_REG_OFFSET 0x90
1239#define OTP_CTRL_CHECK_TRIGGER_REGWEN_REG_RESVAL 0x1u
1240#define OTP_CTRL_CHECK_TRIGGER_REGWEN_CHECK_TRIGGER_REGWEN_BIT 0
1241
1242// Command register for direct accesses.
1243#define OTP_CTRL_CHECK_TRIGGER_REG_OFFSET 0x94
1244#define OTP_CTRL_CHECK_TRIGGER_REG_RESVAL 0x0u
1245#define OTP_CTRL_CHECK_TRIGGER_INTEGRITY_BIT 0
1246#define OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_BIT 1
1247
1248// Register write enable for !!INTEGRITY_CHECK_PERIOD and
1249// !!CONSISTENCY_CHECK_PERIOD.
1250#define OTP_CTRL_CHECK_REGWEN_REG_OFFSET 0x98
1251#define OTP_CTRL_CHECK_REGWEN_REG_RESVAL 0x1u
1252#define OTP_CTRL_CHECK_REGWEN_CHECK_REGWEN_BIT 0
1253
1254// Timeout value for the integrity and consistency checks.
1255#define OTP_CTRL_CHECK_TIMEOUT_REG_OFFSET 0x9c
1256#define OTP_CTRL_CHECK_TIMEOUT_REG_RESVAL 0x0u
1257
1258// This value specifies the maximum period that can be generated pseudo-
1259// randomly.
1260#define OTP_CTRL_INTEGRITY_CHECK_PERIOD_REG_OFFSET 0xa0
1261#define OTP_CTRL_INTEGRITY_CHECK_PERIOD_REG_RESVAL 0x0u
1262
1263// This value specifies the maximum period that can be generated pseudo-
1264// randomly.
1265#define OTP_CTRL_CONSISTENCY_CHECK_PERIOD_REG_OFFSET 0xa4
1266#define OTP_CTRL_CONSISTENCY_CHECK_PERIOD_REG_RESVAL 0x0u
1267
1268// Runtime read lock for the VENDOR_TEST partition.
1269#define OTP_CTRL_VENDOR_TEST_READ_LOCK_REG_OFFSET 0xa8
1270#define OTP_CTRL_VENDOR_TEST_READ_LOCK_REG_RESVAL 0x1u
1271#define OTP_CTRL_VENDOR_TEST_READ_LOCK_VENDOR_TEST_READ_LOCK_BIT 0
1272
1273// Runtime read lock for the CREATOR_SW_CFG partition.
1274#define OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_REG_OFFSET 0xac
1275#define OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_REG_RESVAL 0x1u
1276#define OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_CREATOR_SW_CFG_READ_LOCK_BIT 0
1277
1278// Runtime read lock for the OWNER_SW_CFG partition.
1279#define OTP_CTRL_OWNER_SW_CFG_READ_LOCK_REG_OFFSET 0xb0
1280#define OTP_CTRL_OWNER_SW_CFG_READ_LOCK_REG_RESVAL 0x1u
1281#define OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OWNER_SW_CFG_READ_LOCK_BIT 0
1282
1283// Runtime read lock for the OWNERSHIP_SLOT_STATE partition.
1284#define OTP_CTRL_OWNERSHIP_SLOT_STATE_READ_LOCK_REG_OFFSET 0xb4
1285#define OTP_CTRL_OWNERSHIP_SLOT_STATE_READ_LOCK_REG_RESVAL 0x1u
1286#define OTP_CTRL_OWNERSHIP_SLOT_STATE_READ_LOCK_OWNERSHIP_SLOT_STATE_READ_LOCK_BIT \
1287 0
1288
1289// Runtime read lock for the ROT_CREATOR_AUTH partition.
1290#define OTP_CTRL_ROT_CREATOR_AUTH_READ_LOCK_REG_OFFSET 0xb8
1291#define OTP_CTRL_ROT_CREATOR_AUTH_READ_LOCK_REG_RESVAL 0x1u
1292#define OTP_CTRL_ROT_CREATOR_AUTH_READ_LOCK_ROT_CREATOR_AUTH_READ_LOCK_BIT 0
1293
1294// Runtime read lock for the ROT_OWNER_AUTH_SLOT0 partition.
1295#define OTP_CTRL_ROT_OWNER_AUTH_SLOT0_READ_LOCK_REG_OFFSET 0xbc
1296#define OTP_CTRL_ROT_OWNER_AUTH_SLOT0_READ_LOCK_REG_RESVAL 0x1u
1297#define OTP_CTRL_ROT_OWNER_AUTH_SLOT0_READ_LOCK_ROT_OWNER_AUTH_SLOT0_READ_LOCK_BIT \
1298 0
1299
1300// Runtime read lock for the ROT_OWNER_AUTH_SLOT1 partition.
1301#define OTP_CTRL_ROT_OWNER_AUTH_SLOT1_READ_LOCK_REG_OFFSET 0xc0
1302#define OTP_CTRL_ROT_OWNER_AUTH_SLOT1_READ_LOCK_REG_RESVAL 0x1u
1303#define OTP_CTRL_ROT_OWNER_AUTH_SLOT1_READ_LOCK_ROT_OWNER_AUTH_SLOT1_READ_LOCK_BIT \
1304 0
1305
1306// Runtime read lock for the PLAT_INTEG_AUTH_SLOT0 partition.
1307#define OTP_CTRL_PLAT_INTEG_AUTH_SLOT0_READ_LOCK_REG_OFFSET 0xc4
1308#define OTP_CTRL_PLAT_INTEG_AUTH_SLOT0_READ_LOCK_REG_RESVAL 0x1u
1309#define OTP_CTRL_PLAT_INTEG_AUTH_SLOT0_READ_LOCK_PLAT_INTEG_AUTH_SLOT0_READ_LOCK_BIT \
1310 0
1311
1312// Runtime read lock for the PLAT_INTEG_AUTH_SLOT1 partition.
1313#define OTP_CTRL_PLAT_INTEG_AUTH_SLOT1_READ_LOCK_REG_OFFSET 0xc8
1314#define OTP_CTRL_PLAT_INTEG_AUTH_SLOT1_READ_LOCK_REG_RESVAL 0x1u
1315#define OTP_CTRL_PLAT_INTEG_AUTH_SLOT1_READ_LOCK_PLAT_INTEG_AUTH_SLOT1_READ_LOCK_BIT \
1316 0
1317
1318// Runtime read lock for the PLAT_OWNER_AUTH_SLOT0 partition.
1319#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT0_READ_LOCK_REG_OFFSET 0xcc
1320#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT0_READ_LOCK_REG_RESVAL 0x1u
1321#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT0_READ_LOCK_PLAT_OWNER_AUTH_SLOT0_READ_LOCK_BIT \
1322 0
1323
1324// Runtime read lock for the PLAT_OWNER_AUTH_SLOT1 partition.
1325#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT1_READ_LOCK_REG_OFFSET 0xd0
1326#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT1_READ_LOCK_REG_RESVAL 0x1u
1327#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT1_READ_LOCK_PLAT_OWNER_AUTH_SLOT1_READ_LOCK_BIT \
1328 0
1329
1330// Runtime read lock for the PLAT_OWNER_AUTH_SLOT2 partition.
1331#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT2_READ_LOCK_REG_OFFSET 0xd4
1332#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT2_READ_LOCK_REG_RESVAL 0x1u
1333#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT2_READ_LOCK_PLAT_OWNER_AUTH_SLOT2_READ_LOCK_BIT \
1334 0
1335
1336// Runtime read lock for the PLAT_OWNER_AUTH_SLOT3 partition.
1337#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT3_READ_LOCK_REG_OFFSET 0xd8
1338#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT3_READ_LOCK_REG_RESVAL 0x1u
1339#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT3_READ_LOCK_PLAT_OWNER_AUTH_SLOT3_READ_LOCK_BIT \
1340 0
1341
1342// Runtime read lock for the EXT_NVM partition.
1343#define OTP_CTRL_EXT_NVM_READ_LOCK_REG_OFFSET 0xdc
1344#define OTP_CTRL_EXT_NVM_READ_LOCK_REG_RESVAL 0x1u
1345#define OTP_CTRL_EXT_NVM_READ_LOCK_EXT_NVM_READ_LOCK_BIT 0
1346
1347// Runtime read lock for the ROM_PATCH partition.
1348#define OTP_CTRL_ROM_PATCH_READ_LOCK_REG_OFFSET 0xe0
1349#define OTP_CTRL_ROM_PATCH_READ_LOCK_REG_RESVAL 0x1u
1350#define OTP_CTRL_ROM_PATCH_READ_LOCK_ROM_PATCH_READ_LOCK_BIT 0
1351
1352// Integrity digest for the VENDOR_TEST partition.
1353#define OTP_CTRL_VENDOR_TEST_DIGEST_VENDOR_TEST_DIGEST_FIELD_WIDTH 32
1354#define OTP_CTRL_VENDOR_TEST_DIGEST_MULTIREG_COUNT 2
1355
1356// Integrity digest for the VENDOR_TEST partition.
1357#define OTP_CTRL_VENDOR_TEST_DIGEST_0_REG_OFFSET 0xe4
1358#define OTP_CTRL_VENDOR_TEST_DIGEST_0_REG_RESVAL 0x0u
1359
1360// Integrity digest for the VENDOR_TEST partition.
1361#define OTP_CTRL_VENDOR_TEST_DIGEST_1_REG_OFFSET 0xe8
1362#define OTP_CTRL_VENDOR_TEST_DIGEST_1_REG_RESVAL 0x0u
1363
1364// Integrity digest for the CREATOR_SW_CFG partition.
1365#define OTP_CTRL_CREATOR_SW_CFG_DIGEST_CREATOR_SW_CFG_DIGEST_FIELD_WIDTH 32
1366#define OTP_CTRL_CREATOR_SW_CFG_DIGEST_MULTIREG_COUNT 2
1367
1368// Integrity digest for the CREATOR_SW_CFG partition.
1369#define OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_REG_OFFSET 0xec
1370#define OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_REG_RESVAL 0x0u
1371
1372// Integrity digest for the CREATOR_SW_CFG partition.
1373#define OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_REG_OFFSET 0xf0
1374#define OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_REG_RESVAL 0x0u
1375
1376// Integrity digest for the OWNER_SW_CFG partition.
1377#define OTP_CTRL_OWNER_SW_CFG_DIGEST_OWNER_SW_CFG_DIGEST_FIELD_WIDTH 32
1378#define OTP_CTRL_OWNER_SW_CFG_DIGEST_MULTIREG_COUNT 2
1379
1380// Integrity digest for the OWNER_SW_CFG partition.
1381#define OTP_CTRL_OWNER_SW_CFG_DIGEST_0_REG_OFFSET 0xf4
1382#define OTP_CTRL_OWNER_SW_CFG_DIGEST_0_REG_RESVAL 0x0u
1383
1384// Integrity digest for the OWNER_SW_CFG partition.
1385#define OTP_CTRL_OWNER_SW_CFG_DIGEST_1_REG_OFFSET 0xf8
1386#define OTP_CTRL_OWNER_SW_CFG_DIGEST_1_REG_RESVAL 0x0u
1387
1388// Integrity digest for the ROT_CREATOR_AUTH partition.
1389#define OTP_CTRL_ROT_CREATOR_AUTH_DIGEST_ROT_CREATOR_AUTH_DIGEST_FIELD_WIDTH 32
1390#define OTP_CTRL_ROT_CREATOR_AUTH_DIGEST_MULTIREG_COUNT 2
1391
1392// Integrity digest for the ROT_CREATOR_AUTH partition.
1393#define OTP_CTRL_ROT_CREATOR_AUTH_DIGEST_0_REG_OFFSET 0xfc
1394#define OTP_CTRL_ROT_CREATOR_AUTH_DIGEST_0_REG_RESVAL 0x0u
1395
1396// Integrity digest for the ROT_CREATOR_AUTH partition.
1397#define OTP_CTRL_ROT_CREATOR_AUTH_DIGEST_1_REG_OFFSET 0x100
1398#define OTP_CTRL_ROT_CREATOR_AUTH_DIGEST_1_REG_RESVAL 0x0u
1399
1400// Integrity digest for the ROT_OWNER_AUTH_SLOT0 partition.
1401#define OTP_CTRL_ROT_OWNER_AUTH_SLOT0_DIGEST_ROT_OWNER_AUTH_SLOT0_DIGEST_FIELD_WIDTH \
1402 32
1403#define OTP_CTRL_ROT_OWNER_AUTH_SLOT0_DIGEST_MULTIREG_COUNT 2
1404
1405// Integrity digest for the ROT_OWNER_AUTH_SLOT0 partition.
1406#define OTP_CTRL_ROT_OWNER_AUTH_SLOT0_DIGEST_0_REG_OFFSET 0x104
1407#define OTP_CTRL_ROT_OWNER_AUTH_SLOT0_DIGEST_0_REG_RESVAL 0x0u
1408
1409// Integrity digest for the ROT_OWNER_AUTH_SLOT0 partition.
1410#define OTP_CTRL_ROT_OWNER_AUTH_SLOT0_DIGEST_1_REG_OFFSET 0x108
1411#define OTP_CTRL_ROT_OWNER_AUTH_SLOT0_DIGEST_1_REG_RESVAL 0x0u
1412
1413// Integrity digest for the ROT_OWNER_AUTH_SLOT1 partition.
1414#define OTP_CTRL_ROT_OWNER_AUTH_SLOT1_DIGEST_ROT_OWNER_AUTH_SLOT1_DIGEST_FIELD_WIDTH \
1415 32
1416#define OTP_CTRL_ROT_OWNER_AUTH_SLOT1_DIGEST_MULTIREG_COUNT 2
1417
1418// Integrity digest for the ROT_OWNER_AUTH_SLOT1 partition.
1419#define OTP_CTRL_ROT_OWNER_AUTH_SLOT1_DIGEST_0_REG_OFFSET 0x10c
1420#define OTP_CTRL_ROT_OWNER_AUTH_SLOT1_DIGEST_0_REG_RESVAL 0x0u
1421
1422// Integrity digest for the ROT_OWNER_AUTH_SLOT1 partition.
1423#define OTP_CTRL_ROT_OWNER_AUTH_SLOT1_DIGEST_1_REG_OFFSET 0x110
1424#define OTP_CTRL_ROT_OWNER_AUTH_SLOT1_DIGEST_1_REG_RESVAL 0x0u
1425
1426// Integrity digest for the PLAT_INTEG_AUTH_SLOT0 partition.
1427#define OTP_CTRL_PLAT_INTEG_AUTH_SLOT0_DIGEST_PLAT_INTEG_AUTH_SLOT0_DIGEST_FIELD_WIDTH \
1428 32
1429#define OTP_CTRL_PLAT_INTEG_AUTH_SLOT0_DIGEST_MULTIREG_COUNT 2
1430
1431// Integrity digest for the PLAT_INTEG_AUTH_SLOT0 partition.
1432#define OTP_CTRL_PLAT_INTEG_AUTH_SLOT0_DIGEST_0_REG_OFFSET 0x114
1433#define OTP_CTRL_PLAT_INTEG_AUTH_SLOT0_DIGEST_0_REG_RESVAL 0x0u
1434
1435// Integrity digest for the PLAT_INTEG_AUTH_SLOT0 partition.
1436#define OTP_CTRL_PLAT_INTEG_AUTH_SLOT0_DIGEST_1_REG_OFFSET 0x118
1437#define OTP_CTRL_PLAT_INTEG_AUTH_SLOT0_DIGEST_1_REG_RESVAL 0x0u
1438
1439// Integrity digest for the PLAT_INTEG_AUTH_SLOT1 partition.
1440#define OTP_CTRL_PLAT_INTEG_AUTH_SLOT1_DIGEST_PLAT_INTEG_AUTH_SLOT1_DIGEST_FIELD_WIDTH \
1441 32
1442#define OTP_CTRL_PLAT_INTEG_AUTH_SLOT1_DIGEST_MULTIREG_COUNT 2
1443
1444// Integrity digest for the PLAT_INTEG_AUTH_SLOT1 partition.
1445#define OTP_CTRL_PLAT_INTEG_AUTH_SLOT1_DIGEST_0_REG_OFFSET 0x11c
1446#define OTP_CTRL_PLAT_INTEG_AUTH_SLOT1_DIGEST_0_REG_RESVAL 0x0u
1447
1448// Integrity digest for the PLAT_INTEG_AUTH_SLOT1 partition.
1449#define OTP_CTRL_PLAT_INTEG_AUTH_SLOT1_DIGEST_1_REG_OFFSET 0x120
1450#define OTP_CTRL_PLAT_INTEG_AUTH_SLOT1_DIGEST_1_REG_RESVAL 0x0u
1451
1452// Integrity digest for the PLAT_OWNER_AUTH_SLOT0 partition.
1453#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT0_DIGEST_PLAT_OWNER_AUTH_SLOT0_DIGEST_FIELD_WIDTH \
1454 32
1455#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT0_DIGEST_MULTIREG_COUNT 2
1456
1457// Integrity digest for the PLAT_OWNER_AUTH_SLOT0 partition.
1458#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT0_DIGEST_0_REG_OFFSET 0x124
1459#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT0_DIGEST_0_REG_RESVAL 0x0u
1460
1461// Integrity digest for the PLAT_OWNER_AUTH_SLOT0 partition.
1462#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT0_DIGEST_1_REG_OFFSET 0x128
1463#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT0_DIGEST_1_REG_RESVAL 0x0u
1464
1465// Integrity digest for the PLAT_OWNER_AUTH_SLOT1 partition.
1466#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT1_DIGEST_PLAT_OWNER_AUTH_SLOT1_DIGEST_FIELD_WIDTH \
1467 32
1468#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT1_DIGEST_MULTIREG_COUNT 2
1469
1470// Integrity digest for the PLAT_OWNER_AUTH_SLOT1 partition.
1471#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT1_DIGEST_0_REG_OFFSET 0x12c
1472#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT1_DIGEST_0_REG_RESVAL 0x0u
1473
1474// Integrity digest for the PLAT_OWNER_AUTH_SLOT1 partition.
1475#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT1_DIGEST_1_REG_OFFSET 0x130
1476#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT1_DIGEST_1_REG_RESVAL 0x0u
1477
1478// Integrity digest for the PLAT_OWNER_AUTH_SLOT2 partition.
1479#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT2_DIGEST_PLAT_OWNER_AUTH_SLOT2_DIGEST_FIELD_WIDTH \
1480 32
1481#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT2_DIGEST_MULTIREG_COUNT 2
1482
1483// Integrity digest for the PLAT_OWNER_AUTH_SLOT2 partition.
1484#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT2_DIGEST_0_REG_OFFSET 0x134
1485#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT2_DIGEST_0_REG_RESVAL 0x0u
1486
1487// Integrity digest for the PLAT_OWNER_AUTH_SLOT2 partition.
1488#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT2_DIGEST_1_REG_OFFSET 0x138
1489#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT2_DIGEST_1_REG_RESVAL 0x0u
1490
1491// Integrity digest for the PLAT_OWNER_AUTH_SLOT3 partition.
1492#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT3_DIGEST_PLAT_OWNER_AUTH_SLOT3_DIGEST_FIELD_WIDTH \
1493 32
1494#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT3_DIGEST_MULTIREG_COUNT 2
1495
1496// Integrity digest for the PLAT_OWNER_AUTH_SLOT3 partition.
1497#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT3_DIGEST_0_REG_OFFSET 0x13c
1498#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT3_DIGEST_0_REG_RESVAL 0x0u
1499
1500// Integrity digest for the PLAT_OWNER_AUTH_SLOT3 partition.
1501#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT3_DIGEST_1_REG_OFFSET 0x140
1502#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT3_DIGEST_1_REG_RESVAL 0x0u
1503
1504// Integrity digest for the ROM_PATCH partition.
1505#define OTP_CTRL_ROM_PATCH_DIGEST_ROM_PATCH_DIGEST_FIELD_WIDTH 32
1506#define OTP_CTRL_ROM_PATCH_DIGEST_MULTIREG_COUNT 2
1507
1508// Integrity digest for the ROM_PATCH partition.
1509#define OTP_CTRL_ROM_PATCH_DIGEST_0_REG_OFFSET 0x144
1510#define OTP_CTRL_ROM_PATCH_DIGEST_0_REG_RESVAL 0x0u
1511
1512// Integrity digest for the ROM_PATCH partition.
1513#define OTP_CTRL_ROM_PATCH_DIGEST_1_REG_OFFSET 0x148
1514#define OTP_CTRL_ROM_PATCH_DIGEST_1_REG_RESVAL 0x0u
1515
1516// Integrity digest for the HW_CFG0 partition.
1517#define OTP_CTRL_HW_CFG0_DIGEST_HW_CFG0_DIGEST_FIELD_WIDTH 32
1518#define OTP_CTRL_HW_CFG0_DIGEST_MULTIREG_COUNT 2
1519
1520// Integrity digest for the HW_CFG0 partition.
1521#define OTP_CTRL_HW_CFG0_DIGEST_0_REG_OFFSET 0x14c
1522#define OTP_CTRL_HW_CFG0_DIGEST_0_REG_RESVAL 0x0u
1523
1524// Integrity digest for the HW_CFG0 partition.
1525#define OTP_CTRL_HW_CFG0_DIGEST_1_REG_OFFSET 0x150
1526#define OTP_CTRL_HW_CFG0_DIGEST_1_REG_RESVAL 0x0u
1527
1528// Integrity digest for the HW_CFG1 partition.
1529#define OTP_CTRL_HW_CFG1_DIGEST_HW_CFG1_DIGEST_FIELD_WIDTH 32
1530#define OTP_CTRL_HW_CFG1_DIGEST_MULTIREG_COUNT 2
1531
1532// Integrity digest for the HW_CFG1 partition.
1533#define OTP_CTRL_HW_CFG1_DIGEST_0_REG_OFFSET 0x154
1534#define OTP_CTRL_HW_CFG1_DIGEST_0_REG_RESVAL 0x0u
1535
1536// Integrity digest for the HW_CFG1 partition.
1537#define OTP_CTRL_HW_CFG1_DIGEST_1_REG_OFFSET 0x158
1538#define OTP_CTRL_HW_CFG1_DIGEST_1_REG_RESVAL 0x0u
1539
1540// Integrity digest for the SECRET0 partition.
1541#define OTP_CTRL_SECRET0_DIGEST_SECRET0_DIGEST_FIELD_WIDTH 32
1542#define OTP_CTRL_SECRET0_DIGEST_MULTIREG_COUNT 2
1543
1544// Integrity digest for the SECRET0 partition.
1545#define OTP_CTRL_SECRET0_DIGEST_0_REG_OFFSET 0x15c
1546#define OTP_CTRL_SECRET0_DIGEST_0_REG_RESVAL 0x0u
1547
1548// Integrity digest for the SECRET0 partition.
1549#define OTP_CTRL_SECRET0_DIGEST_1_REG_OFFSET 0x160
1550#define OTP_CTRL_SECRET0_DIGEST_1_REG_RESVAL 0x0u
1551
1552// Integrity digest for the SECRET1 partition.
1553#define OTP_CTRL_SECRET1_DIGEST_SECRET1_DIGEST_FIELD_WIDTH 32
1554#define OTP_CTRL_SECRET1_DIGEST_MULTIREG_COUNT 2
1555
1556// Integrity digest for the SECRET1 partition.
1557#define OTP_CTRL_SECRET1_DIGEST_0_REG_OFFSET 0x164
1558#define OTP_CTRL_SECRET1_DIGEST_0_REG_RESVAL 0x0u
1559
1560// Integrity digest for the SECRET1 partition.
1561#define OTP_CTRL_SECRET1_DIGEST_1_REG_OFFSET 0x168
1562#define OTP_CTRL_SECRET1_DIGEST_1_REG_RESVAL 0x0u
1563
1564// Integrity digest for the SECRET2 partition.
1565#define OTP_CTRL_SECRET2_DIGEST_SECRET2_DIGEST_FIELD_WIDTH 32
1566#define OTP_CTRL_SECRET2_DIGEST_MULTIREG_COUNT 2
1567
1568// Integrity digest for the SECRET2 partition.
1569#define OTP_CTRL_SECRET2_DIGEST_0_REG_OFFSET 0x16c
1570#define OTP_CTRL_SECRET2_DIGEST_0_REG_RESVAL 0x0u
1571
1572// Integrity digest for the SECRET2 partition.
1573#define OTP_CTRL_SECRET2_DIGEST_1_REG_OFFSET 0x170
1574#define OTP_CTRL_SECRET2_DIGEST_1_REG_RESVAL 0x0u
1575
1576// Integrity digest for the SECRET3 partition.
1577#define OTP_CTRL_SECRET3_DIGEST_SECRET3_DIGEST_FIELD_WIDTH 32
1578#define OTP_CTRL_SECRET3_DIGEST_MULTIREG_COUNT 2
1579
1580// Integrity digest for the SECRET3 partition.
1581#define OTP_CTRL_SECRET3_DIGEST_0_REG_OFFSET 0x174
1582#define OTP_CTRL_SECRET3_DIGEST_0_REG_RESVAL 0x0u
1583
1584// Integrity digest for the SECRET3 partition.
1585#define OTP_CTRL_SECRET3_DIGEST_1_REG_OFFSET 0x178
1586#define OTP_CTRL_SECRET3_DIGEST_1_REG_RESVAL 0x0u
1587
1588// Memory area: Any read to this window directly maps to the corresponding
1589// offset in the creator and owner software
1590#define OTP_CTRL_SW_CFG_WINDOW_REG_OFFSET 0x4000
1591#define OTP_CTRL_SW_CFG_WINDOW_SIZE_WORDS 4096
1592#define OTP_CTRL_SW_CFG_WINDOW_SIZE_BYTES 16384
1593#ifdef __cplusplus
1594} // extern "C"
1595#endif
1596#endif // _OTP_CTRL_REG_DEFS_
1597// End generated register defines for otp_ctrl