otp_ctrl_regs.h

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/**
 * @file
 * @brief Generated register defines for otp_ctrl
 */
 
// Copyright information found in source file:
// Copyright lowRISC contributors (OpenTitan project).
 
// Licensing information found in source file:
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
 
#ifndef _OTP_CTRL_REG_DEFS_
#define _OTP_CTRL_REG_DEFS_
 
#ifdef __cplusplus
extern "C" {
#endif
// Number of key slots
#define OTP_CTRL_PARAM_NUM_SRAM_KEY_REQ_SLOTS 4
 
// Number of native words.
#define OTP_CTRL_PARAM_OTP_DEPTH 8192
 
// Number of bytes in native words.
#define OTP_CTRL_PARAM_OTP_WIDTH 2
 
// Number of bits to represent the native words per transaction.
#define OTP_CTRL_PARAM_OTP_SIZE_WIDTH 2
 
// Width of the OTP byte address.
#define OTP_CTRL_PARAM_OTP_BYTE_ADDR_WIDTH 14
 
// Number of error register entries.
#define OTP_CTRL_PARAM_NUM_ERROR_ENTRIES 24
 
// Number of 32bit words in the DAI.
#define OTP_CTRL_PARAM_NUM_DAI_WORDS 2
 
// Size of the digest fields in 32bit words.
#define OTP_CTRL_PARAM_NUM_DIGEST_WORDS 2
 
// Size of the TL-UL window in 32bit words. Note that the effective partition
// size is smaller than that.
#define OTP_CTRL_PARAM_NUM_SW_CFG_WINDOW_WORDS 4096
 
// Number of partitions
#define OTP_CTRL_PARAM_NUM_PART 22
 
// Number of unbuffered partitions
#define OTP_CTRL_PARAM_NUM_PART_UNBUF 15
 
// Number of buffered partitions (including 1 lifecycle partition)
#define OTP_CTRL_PARAM_NUM_PART_BUF 7
 
// Offset of the VENDOR_TEST partition
#define OTP_CTRL_PARAM_VENDOR_TEST_OFFSET 0
 
// Size of the VENDOR_TEST partition
#define OTP_CTRL_PARAM_VENDOR_TEST_SIZE 64
 
// Offset of SCRATCH
#define OTP_CTRL_PARAM_SCRATCH_OFFSET 0
 
// Size of SCRATCH
#define OTP_CTRL_PARAM_SCRATCH_SIZE 56
 
// Offset of VENDOR_TEST_DIGEST
#define OTP_CTRL_PARAM_VENDOR_TEST_DIGEST_OFFSET 56
 
// Size of VENDOR_TEST_DIGEST
#define OTP_CTRL_PARAM_VENDOR_TEST_DIGEST_SIZE 8
 
// Offset of the CREATOR_SW_CFG partition
#define OTP_CTRL_PARAM_CREATOR_SW_CFG_OFFSET 64
 
// Size of the CREATOR_SW_CFG partition
#define OTP_CTRL_PARAM_CREATOR_SW_CFG_SIZE 320
 
// Offset of CREATOR_SW_CFG_AST_CFG
#define OTP_CTRL_PARAM_CREATOR_SW_CFG_AST_CFG_OFFSET 64
 
// Size of CREATOR_SW_CFG_AST_CFG
#define OTP_CTRL_PARAM_CREATOR_SW_CFG_AST_CFG_SIZE 124
 
// Offset of CREATOR_SW_CFG_AST_INIT_EN
#define OTP_CTRL_PARAM_CREATOR_SW_CFG_AST_INIT_EN_OFFSET 188
 
// Size of CREATOR_SW_CFG_AST_INIT_EN
#define OTP_CTRL_PARAM_CREATOR_SW_CFG_AST_INIT_EN_SIZE 4
 
// Offset of CREATOR_SW_CFG_OVERRIDES
#define OTP_CTRL_PARAM_CREATOR_SW_CFG_OVERRIDES_OFFSET 192
 
// Size of CREATOR_SW_CFG_OVERRIDES
#define OTP_CTRL_PARAM_CREATOR_SW_CFG_OVERRIDES_SIZE 32
 
// Offset of CREATOR_SW_CFG_ROM_EXT_SKU
#define OTP_CTRL_PARAM_CREATOR_SW_CFG_ROM_EXT_SKU_OFFSET 224
 
// Size of CREATOR_SW_CFG_ROM_EXT_SKU
#define OTP_CTRL_PARAM_CREATOR_SW_CFG_ROM_EXT_SKU_SIZE 4
 
// Offset of CREATOR_SW_CFG_SIGVERIFY_RSA_MOD_EXP_IBEX_EN
#define OTP_CTRL_PARAM_CREATOR_SW_CFG_SIGVERIFY_RSA_MOD_EXP_IBEX_EN_OFFSET 228
 
// Size of CREATOR_SW_CFG_SIGVERIFY_RSA_MOD_EXP_IBEX_EN
#define OTP_CTRL_PARAM_CREATOR_SW_CFG_SIGVERIFY_RSA_MOD_EXP_IBEX_EN_SIZE 4
 
// Offset of CREATOR_SW_CFG_SIGVERIFY_RSA_KEY_EN
#define OTP_CTRL_PARAM_CREATOR_SW_CFG_SIGVERIFY_RSA_KEY_EN_OFFSET 232
 
// Size of CREATOR_SW_CFG_SIGVERIFY_RSA_KEY_EN
#define OTP_CTRL_PARAM_CREATOR_SW_CFG_SIGVERIFY_RSA_KEY_EN_SIZE 8
 
// Offset of CREATOR_SW_CFG_SIGVERIFY_SPX_EN
#define OTP_CTRL_PARAM_CREATOR_SW_CFG_SIGVERIFY_SPX_EN_OFFSET 240
 
// Size of CREATOR_SW_CFG_SIGVERIFY_SPX_EN
#define OTP_CTRL_PARAM_CREATOR_SW_CFG_SIGVERIFY_SPX_EN_SIZE 4
 
// Offset of CREATOR_SW_CFG_SIGVERIFY_SPX_KEY_EN
#define OTP_CTRL_PARAM_CREATOR_SW_CFG_SIGVERIFY_SPX_KEY_EN_OFFSET 244
 
// Size of CREATOR_SW_CFG_SIGVERIFY_SPX_KEY_EN
#define OTP_CTRL_PARAM_CREATOR_SW_CFG_SIGVERIFY_SPX_KEY_EN_SIZE 8
 
// Offset of CREATOR_SW_CFG_FLASH_DATA_DEFAULT_CFG
#define OTP_CTRL_PARAM_CREATOR_SW_CFG_FLASH_DATA_DEFAULT_CFG_OFFSET 252
 
// Size of CREATOR_SW_CFG_FLASH_DATA_DEFAULT_CFG
#define OTP_CTRL_PARAM_CREATOR_SW_CFG_FLASH_DATA_DEFAULT_CFG_SIZE 4
 
// Offset of CREATOR_SW_CFG_FLASH_INFO_BOOT_DATA_CFG
#define OTP_CTRL_PARAM_CREATOR_SW_CFG_FLASH_INFO_BOOT_DATA_CFG_OFFSET 256
 
// Size of CREATOR_SW_CFG_FLASH_INFO_BOOT_DATA_CFG
#define OTP_CTRL_PARAM_CREATOR_SW_CFG_FLASH_INFO_BOOT_DATA_CFG_SIZE 4
 
// Offset of CREATOR_SW_CFG_FLASH_HW_INFO_CFG_OVERRIDE
#define OTP_CTRL_PARAM_CREATOR_SW_CFG_FLASH_HW_INFO_CFG_OVERRIDE_OFFSET 260
 
// Size of CREATOR_SW_CFG_FLASH_HW_INFO_CFG_OVERRIDE
#define OTP_CTRL_PARAM_CREATOR_SW_CFG_FLASH_HW_INFO_CFG_OVERRIDE_SIZE 4
 
// Offset of CREATOR_SW_CFG_RNG_EN
#define OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_EN_OFFSET 264
 
// Size of CREATOR_SW_CFG_RNG_EN
#define OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_EN_SIZE 4
 
// Offset of CREATOR_SW_CFG_JITTER_EN
#define OTP_CTRL_PARAM_CREATOR_SW_CFG_JITTER_EN_OFFSET 268
 
// Size of CREATOR_SW_CFG_JITTER_EN
#define OTP_CTRL_PARAM_CREATOR_SW_CFG_JITTER_EN_SIZE 4
 
// Offset of CREATOR_SW_CFG_RET_RAM_RESET_MASK
#define OTP_CTRL_PARAM_CREATOR_SW_CFG_RET_RAM_RESET_MASK_OFFSET 272
 
// Size of CREATOR_SW_CFG_RET_RAM_RESET_MASK
#define OTP_CTRL_PARAM_CREATOR_SW_CFG_RET_RAM_RESET_MASK_SIZE 4
 
// Offset of CREATOR_SW_CFG_MANUF_STATE
#define OTP_CTRL_PARAM_CREATOR_SW_CFG_MANUF_STATE_OFFSET 276
 
// Size of CREATOR_SW_CFG_MANUF_STATE
#define OTP_CTRL_PARAM_CREATOR_SW_CFG_MANUF_STATE_SIZE 4
 
// Offset of CREATOR_SW_CFG_ROM_EXEC_EN
#define OTP_CTRL_PARAM_CREATOR_SW_CFG_ROM_EXEC_EN_OFFSET 280
 
// Size of CREATOR_SW_CFG_ROM_EXEC_EN
#define OTP_CTRL_PARAM_CREATOR_SW_CFG_ROM_EXEC_EN_SIZE 4
 
// Offset of CREATOR_SW_CFG_CPUCTRL
#define OTP_CTRL_PARAM_CREATOR_SW_CFG_CPUCTRL_OFFSET 284
 
// Size of CREATOR_SW_CFG_CPUCTRL
#define OTP_CTRL_PARAM_CREATOR_SW_CFG_CPUCTRL_SIZE 4
 
// Offset of CREATOR_SW_CFG_MIN_SEC_VER_ROM_EXT
#define OTP_CTRL_PARAM_CREATOR_SW_CFG_MIN_SEC_VER_ROM_EXT_OFFSET 288
 
// Size of CREATOR_SW_CFG_MIN_SEC_VER_ROM_EXT
#define OTP_CTRL_PARAM_CREATOR_SW_CFG_MIN_SEC_VER_ROM_EXT_SIZE 4
 
// Offset of CREATOR_SW_CFG_MIN_SEC_VER_BL0
#define OTP_CTRL_PARAM_CREATOR_SW_CFG_MIN_SEC_VER_BL0_OFFSET 292
 
// Size of CREATOR_SW_CFG_MIN_SEC_VER_BL0
#define OTP_CTRL_PARAM_CREATOR_SW_CFG_MIN_SEC_VER_BL0_SIZE 4
 
// Offset of CREATOR_SW_CFG_DEFAULT_BOOT_DATA_IN_PROD_EN
#define OTP_CTRL_PARAM_CREATOR_SW_CFG_DEFAULT_BOOT_DATA_IN_PROD_EN_OFFSET 296
 
// Size of CREATOR_SW_CFG_DEFAULT_BOOT_DATA_IN_PROD_EN
#define OTP_CTRL_PARAM_CREATOR_SW_CFG_DEFAULT_BOOT_DATA_IN_PROD_EN_SIZE 4
 
// Offset of CREATOR_SW_CFG_RMA_SPIN_EN
#define OTP_CTRL_PARAM_CREATOR_SW_CFG_RMA_SPIN_EN_OFFSET 300
 
// Size of CREATOR_SW_CFG_RMA_SPIN_EN
#define OTP_CTRL_PARAM_CREATOR_SW_CFG_RMA_SPIN_EN_SIZE 4
 
// Offset of CREATOR_SW_CFG_RMA_SPIN_CYCLES
#define OTP_CTRL_PARAM_CREATOR_SW_CFG_RMA_SPIN_CYCLES_OFFSET 304
 
// Size of CREATOR_SW_CFG_RMA_SPIN_CYCLES
#define OTP_CTRL_PARAM_CREATOR_SW_CFG_RMA_SPIN_CYCLES_SIZE 4
 
// Offset of CREATOR_SW_CFG_RNG_REPCNT_THRESHOLDS
#define OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_REPCNT_THRESHOLDS_OFFSET 308
 
// Size of CREATOR_SW_CFG_RNG_REPCNT_THRESHOLDS
#define OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_REPCNT_THRESHOLDS_SIZE 4
 
// Offset of CREATOR_SW_CFG_RNG_REPCNTS_THRESHOLDS
#define OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_REPCNTS_THRESHOLDS_OFFSET 312
 
// Size of CREATOR_SW_CFG_RNG_REPCNTS_THRESHOLDS
#define OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_REPCNTS_THRESHOLDS_SIZE 4
 
// Offset of CREATOR_SW_CFG_RNG_ADAPTP_HI_THRESHOLDS
#define OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_ADAPTP_HI_THRESHOLDS_OFFSET 316
 
// Size of CREATOR_SW_CFG_RNG_ADAPTP_HI_THRESHOLDS
#define OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_ADAPTP_HI_THRESHOLDS_SIZE 4
 
// Offset of CREATOR_SW_CFG_RNG_ADAPTP_LO_THRESHOLDS
#define OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_ADAPTP_LO_THRESHOLDS_OFFSET 320
 
// Size of CREATOR_SW_CFG_RNG_ADAPTP_LO_THRESHOLDS
#define OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_ADAPTP_LO_THRESHOLDS_SIZE 4
 
// Offset of CREATOR_SW_CFG_RNG_BUCKET_THRESHOLDS
#define OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_BUCKET_THRESHOLDS_OFFSET 324
 
// Size of CREATOR_SW_CFG_RNG_BUCKET_THRESHOLDS
#define OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_BUCKET_THRESHOLDS_SIZE 4
 
// Offset of CREATOR_SW_CFG_RNG_MARKOV_HI_THRESHOLDS
#define OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_MARKOV_HI_THRESHOLDS_OFFSET 328
 
// Size of CREATOR_SW_CFG_RNG_MARKOV_HI_THRESHOLDS
#define OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_MARKOV_HI_THRESHOLDS_SIZE 4
 
// Offset of CREATOR_SW_CFG_RNG_MARKOV_LO_THRESHOLDS
#define OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_MARKOV_LO_THRESHOLDS_OFFSET 332
 
// Size of CREATOR_SW_CFG_RNG_MARKOV_LO_THRESHOLDS
#define OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_MARKOV_LO_THRESHOLDS_SIZE 4
 
// Offset of CREATOR_SW_CFG_RNG_EXTHT_HI_THRESHOLDS
#define OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_EXTHT_HI_THRESHOLDS_OFFSET 336
 
// Size of CREATOR_SW_CFG_RNG_EXTHT_HI_THRESHOLDS
#define OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_EXTHT_HI_THRESHOLDS_SIZE 4
 
// Offset of CREATOR_SW_CFG_RNG_EXTHT_LO_THRESHOLDS
#define OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_EXTHT_LO_THRESHOLDS_OFFSET 340
 
// Size of CREATOR_SW_CFG_RNG_EXTHT_LO_THRESHOLDS
#define OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_EXTHT_LO_THRESHOLDS_SIZE 4
 
// Offset of CREATOR_SW_CFG_RNG_ALERT_THRESHOLD
#define OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_ALERT_THRESHOLD_OFFSET 344
 
// Size of CREATOR_SW_CFG_RNG_ALERT_THRESHOLD
#define OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_ALERT_THRESHOLD_SIZE 4
 
// Offset of CREATOR_SW_CFG_RNG_HEALTH_CONFIG_DIGEST
#define OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_HEALTH_CONFIG_DIGEST_OFFSET 348
 
// Size of CREATOR_SW_CFG_RNG_HEALTH_CONFIG_DIGEST
#define OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_HEALTH_CONFIG_DIGEST_SIZE 4
 
// Offset of CREATOR_SW_CFG_SRAM_KEY_RENEW_EN
#define OTP_CTRL_PARAM_CREATOR_SW_CFG_SRAM_KEY_RENEW_EN_OFFSET 352
 
// Size of CREATOR_SW_CFG_SRAM_KEY_RENEW_EN
#define OTP_CTRL_PARAM_CREATOR_SW_CFG_SRAM_KEY_RENEW_EN_SIZE 4
 
// Offset of CREATOR_SW_CFG_DIGEST
#define OTP_CTRL_PARAM_CREATOR_SW_CFG_DIGEST_OFFSET 376
 
// Size of CREATOR_SW_CFG_DIGEST
#define OTP_CTRL_PARAM_CREATOR_SW_CFG_DIGEST_SIZE 8
 
// Offset of the OWNER_SW_CFG partition
#define OTP_CTRL_PARAM_OWNER_SW_CFG_OFFSET 384
 
// Size of the OWNER_SW_CFG partition
#define OTP_CTRL_PARAM_OWNER_SW_CFG_SIZE 632
 
// Offset of OWNER_SW_CFG_ROM_ERROR_REPORTING
#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_ERROR_REPORTING_OFFSET 384
 
// Size of OWNER_SW_CFG_ROM_ERROR_REPORTING
#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_ERROR_REPORTING_SIZE 4
 
// Offset of OWNER_SW_CFG_ROM_BOOTSTRAP_DIS
#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_BOOTSTRAP_DIS_OFFSET 388
 
// Size of OWNER_SW_CFG_ROM_BOOTSTRAP_DIS
#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_BOOTSTRAP_DIS_SIZE 4
 
// Offset of OWNER_SW_CFG_ROM_ALERT_CLASS_EN
#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_ALERT_CLASS_EN_OFFSET 392
 
// Size of OWNER_SW_CFG_ROM_ALERT_CLASS_EN
#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_ALERT_CLASS_EN_SIZE 4
 
// Offset of OWNER_SW_CFG_ROM_ALERT_ESCALATION
#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_ALERT_ESCALATION_OFFSET 396
 
// Size of OWNER_SW_CFG_ROM_ALERT_ESCALATION
#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_ALERT_ESCALATION_SIZE 4
 
// Offset of OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION
#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION_OFFSET 400
 
// Size of OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION
#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION_SIZE 400
 
// Offset of OWNER_SW_CFG_ROM_LOCAL_ALERT_CLASSIFICATION
#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_LOCAL_ALERT_CLASSIFICATION_OFFSET 800
 
// Size of OWNER_SW_CFG_ROM_LOCAL_ALERT_CLASSIFICATION
#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_LOCAL_ALERT_CLASSIFICATION_SIZE 64
 
// Offset of OWNER_SW_CFG_ROM_ALERT_ACCUM_THRESH
#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_ALERT_ACCUM_THRESH_OFFSET 864
 
// Size of OWNER_SW_CFG_ROM_ALERT_ACCUM_THRESH
#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_ALERT_ACCUM_THRESH_SIZE 16
 
// Offset of OWNER_SW_CFG_ROM_ALERT_TIMEOUT_CYCLES
#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_ALERT_TIMEOUT_CYCLES_OFFSET 880
 
// Size of OWNER_SW_CFG_ROM_ALERT_TIMEOUT_CYCLES
#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_ALERT_TIMEOUT_CYCLES_SIZE 16
 
// Offset of OWNER_SW_CFG_ROM_ALERT_PHASE_CYCLES
#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_ALERT_PHASE_CYCLES_OFFSET 896
 
// Size of OWNER_SW_CFG_ROM_ALERT_PHASE_CYCLES
#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_ALERT_PHASE_CYCLES_SIZE 64
 
// Offset of OWNER_SW_CFG_ROM_ALERT_DIGEST_PROD
#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_ALERT_DIGEST_PROD_OFFSET 960
 
// Size of OWNER_SW_CFG_ROM_ALERT_DIGEST_PROD
#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_ALERT_DIGEST_PROD_SIZE 4
 
// Offset of OWNER_SW_CFG_ROM_ALERT_DIGEST_PROD_END
#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_ALERT_DIGEST_PROD_END_OFFSET 964
 
// Size of OWNER_SW_CFG_ROM_ALERT_DIGEST_PROD_END
#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_ALERT_DIGEST_PROD_END_SIZE 4
 
// Offset of OWNER_SW_CFG_ROM_ALERT_DIGEST_DEV
#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_ALERT_DIGEST_DEV_OFFSET 968
 
// Size of OWNER_SW_CFG_ROM_ALERT_DIGEST_DEV
#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_ALERT_DIGEST_DEV_SIZE 4
 
// Offset of OWNER_SW_CFG_ROM_ALERT_DIGEST_RMA
#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_ALERT_DIGEST_RMA_OFFSET 972
 
// Size of OWNER_SW_CFG_ROM_ALERT_DIGEST_RMA
#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_ALERT_DIGEST_RMA_SIZE 4
 
// Offset of OWNER_SW_CFG_ROM_WATCHDOG_BITE_THRESHOLD_CYCLES
#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_WATCHDOG_BITE_THRESHOLD_CYCLES_OFFSET \
  976
 
// Size of OWNER_SW_CFG_ROM_WATCHDOG_BITE_THRESHOLD_CYCLES
#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_WATCHDOG_BITE_THRESHOLD_CYCLES_SIZE 4
 
// Offset of OWNER_SW_CFG_ROM_KEYMGR_ROM_EXT_MEAS_EN
#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_KEYMGR_ROM_EXT_MEAS_EN_OFFSET 980
 
// Size of OWNER_SW_CFG_ROM_KEYMGR_ROM_EXT_MEAS_EN
#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_KEYMGR_ROM_EXT_MEAS_EN_SIZE 4
 
// Offset of OWNER_SW_CFG_MANUF_STATE
#define OTP_CTRL_PARAM_OWNER_SW_CFG_MANUF_STATE_OFFSET 984
 
// Size of OWNER_SW_CFG_MANUF_STATE
#define OTP_CTRL_PARAM_OWNER_SW_CFG_MANUF_STATE_SIZE 4
 
// Offset of OWNER_SW_CFG_ROM_RSTMGR_INFO_EN
#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_RSTMGR_INFO_EN_OFFSET 988
 
// Size of OWNER_SW_CFG_ROM_RSTMGR_INFO_EN
#define OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_RSTMGR_INFO_EN_SIZE 4
 
// Offset of OWNER_SW_CFG_DIGEST
#define OTP_CTRL_PARAM_OWNER_SW_CFG_DIGEST_OFFSET 1008
 
// Size of OWNER_SW_CFG_DIGEST
#define OTP_CTRL_PARAM_OWNER_SW_CFG_DIGEST_SIZE 8
 
// Offset of the OWNERSHIP_SLOT_STATE partition
#define OTP_CTRL_PARAM_OWNERSHIP_SLOT_STATE_OFFSET 1016
 
// Size of the OWNERSHIP_SLOT_STATE partition
#define OTP_CTRL_PARAM_OWNERSHIP_SLOT_STATE_SIZE 48
 
// Offset of OWNERSHIP_SLOT_STATE_ROT_OWNER_AUTH
#define OTP_CTRL_PARAM_OWNERSHIP_SLOT_STATE_ROT_OWNER_AUTH_OFFSET 1016
 
// Size of OWNERSHIP_SLOT_STATE_ROT_OWNER_AUTH
#define OTP_CTRL_PARAM_OWNERSHIP_SLOT_STATE_ROT_OWNER_AUTH_SIZE 16
 
// Offset of OWNERSHIP_SLOT_STATE_PLAT_INTEG_AUTH
#define OTP_CTRL_PARAM_OWNERSHIP_SLOT_STATE_PLAT_INTEG_AUTH_OFFSET 1032
 
// Size of OWNERSHIP_SLOT_STATE_PLAT_INTEG_AUTH
#define OTP_CTRL_PARAM_OWNERSHIP_SLOT_STATE_PLAT_INTEG_AUTH_SIZE 16
 
// Offset of OWNERSHIP_SLOT_STATE_PLAT_OWNER_AUTH
#define OTP_CTRL_PARAM_OWNERSHIP_SLOT_STATE_PLAT_OWNER_AUTH_OFFSET 1048
 
// Size of OWNERSHIP_SLOT_STATE_PLAT_OWNER_AUTH
#define OTP_CTRL_PARAM_OWNERSHIP_SLOT_STATE_PLAT_OWNER_AUTH_SIZE 16
 
// Offset of the ROT_CREATOR_AUTH partition
#define OTP_CTRL_PARAM_ROT_CREATOR_AUTH_OFFSET 1064
 
// Size of the ROT_CREATOR_AUTH partition
#define OTP_CTRL_PARAM_ROT_CREATOR_AUTH_SIZE 1424
 
// Offset of ROT_CREATOR_AUTH_NON_RAW_MFW_CODESIGN_KEY
#define OTP_CTRL_PARAM_ROT_CREATOR_AUTH_NON_RAW_MFW_CODESIGN_KEY_OFFSET 1064
 
// Size of ROT_CREATOR_AUTH_NON_RAW_MFW_CODESIGN_KEY
#define OTP_CTRL_PARAM_ROT_CREATOR_AUTH_NON_RAW_MFW_CODESIGN_KEY_SIZE 160
 
// Offset of ROT_CREATOR_AUTH_OWNERSHIP_STATE
#define OTP_CTRL_PARAM_ROT_CREATOR_AUTH_OWNERSHIP_STATE_OFFSET 1224
 
// Size of ROT_CREATOR_AUTH_OWNERSHIP_STATE
#define OTP_CTRL_PARAM_ROT_CREATOR_AUTH_OWNERSHIP_STATE_SIZE 4
 
// Offset of ROT_CREATOR_AUTH_ROM2_PATCH_SIGVERIFY_KEY
#define OTP_CTRL_PARAM_ROT_CREATOR_AUTH_ROM2_PATCH_SIGVERIFY_KEY_OFFSET 1228
 
// Size of ROT_CREATOR_AUTH_ROM2_PATCH_SIGVERIFY_KEY
#define OTP_CTRL_PARAM_ROT_CREATOR_AUTH_ROM2_PATCH_SIGVERIFY_KEY_SIZE 160
 
// Offset of ROT_CREATOR_AUTH_KEYMANIFEST_KEY
#define OTP_CTRL_PARAM_ROT_CREATOR_AUTH_KEYMANIFEST_KEY_OFFSET 1388
 
// Size of ROT_CREATOR_AUTH_KEYMANIFEST_KEY
#define OTP_CTRL_PARAM_ROT_CREATOR_AUTH_KEYMANIFEST_KEY_SIZE 160
 
// Offset of ROT_CREATOR_AUTH_UNLOCK4XFER_KEY
#define OTP_CTRL_PARAM_ROT_CREATOR_AUTH_UNLOCK4XFER_KEY_OFFSET 1548
 
// Size of ROT_CREATOR_AUTH_UNLOCK4XFER_KEY
#define OTP_CTRL_PARAM_ROT_CREATOR_AUTH_UNLOCK4XFER_KEY_SIZE 160
 
// Offset of ROT_CREATOR_AUTH_IDENTITY_CERT
#define OTP_CTRL_PARAM_ROT_CREATOR_AUTH_IDENTITY_CERT_OFFSET 1708
 
// Size of ROT_CREATOR_AUTH_IDENTITY_CERT
#define OTP_CTRL_PARAM_ROT_CREATOR_AUTH_IDENTITY_CERT_SIZE 768
 
// Offset of ROT_CREATOR_AUTH_DIGEST
#define OTP_CTRL_PARAM_ROT_CREATOR_AUTH_DIGEST_OFFSET 2480
 
// Size of ROT_CREATOR_AUTH_DIGEST
#define OTP_CTRL_PARAM_ROT_CREATOR_AUTH_DIGEST_SIZE 8
 
// Offset of the ROT_OWNER_AUTH_SLOT0 partition
#define OTP_CTRL_PARAM_ROT_OWNER_AUTH_SLOT0_OFFSET 2488
 
// Size of the ROT_OWNER_AUTH_SLOT0 partition
#define OTP_CTRL_PARAM_ROT_OWNER_AUTH_SLOT0_SIZE 328
 
// Offset of ROT_OWNER_AUTH_SLOT0_KEYMANIFEST_KEY
#define OTP_CTRL_PARAM_ROT_OWNER_AUTH_SLOT0_KEYMANIFEST_KEY_OFFSET 2488
 
// Size of ROT_OWNER_AUTH_SLOT0_KEYMANIFEST_KEY
#define OTP_CTRL_PARAM_ROT_OWNER_AUTH_SLOT0_KEYMANIFEST_KEY_SIZE 160
 
// Offset of ROT_OWNER_AUTH_SLOT0_UNLOCK4XFER_KEY
#define OTP_CTRL_PARAM_ROT_OWNER_AUTH_SLOT0_UNLOCK4XFER_KEY_OFFSET 2648
 
// Size of ROT_OWNER_AUTH_SLOT0_UNLOCK4XFER_KEY
#define OTP_CTRL_PARAM_ROT_OWNER_AUTH_SLOT0_UNLOCK4XFER_KEY_SIZE 160
 
// Offset of ROT_OWNER_AUTH_SLOT0_DIGEST
#define OTP_CTRL_PARAM_ROT_OWNER_AUTH_SLOT0_DIGEST_OFFSET 2808
 
// Size of ROT_OWNER_AUTH_SLOT0_DIGEST
#define OTP_CTRL_PARAM_ROT_OWNER_AUTH_SLOT0_DIGEST_SIZE 8
 
// Offset of the ROT_OWNER_AUTH_SLOT1 partition
#define OTP_CTRL_PARAM_ROT_OWNER_AUTH_SLOT1_OFFSET 2816
 
// Size of the ROT_OWNER_AUTH_SLOT1 partition
#define OTP_CTRL_PARAM_ROT_OWNER_AUTH_SLOT1_SIZE 328
 
// Offset of ROT_OWNER_AUTH_SLOT1_KEYMANIFEST_KEY
#define OTP_CTRL_PARAM_ROT_OWNER_AUTH_SLOT1_KEYMANIFEST_KEY_OFFSET 2816
 
// Size of ROT_OWNER_AUTH_SLOT1_KEYMANIFEST_KEY
#define OTP_CTRL_PARAM_ROT_OWNER_AUTH_SLOT1_KEYMANIFEST_KEY_SIZE 160
 
// Offset of ROT_OWNER_AUTH_SLOT1_UNLOCK4XFER_KEY
#define OTP_CTRL_PARAM_ROT_OWNER_AUTH_SLOT1_UNLOCK4XFER_KEY_OFFSET 2976
 
// Size of ROT_OWNER_AUTH_SLOT1_UNLOCK4XFER_KEY
#define OTP_CTRL_PARAM_ROT_OWNER_AUTH_SLOT1_UNLOCK4XFER_KEY_SIZE 160
 
// Offset of ROT_OWNER_AUTH_SLOT1_DIGEST
#define OTP_CTRL_PARAM_ROT_OWNER_AUTH_SLOT1_DIGEST_OFFSET 3136
 
// Size of ROT_OWNER_AUTH_SLOT1_DIGEST
#define OTP_CTRL_PARAM_ROT_OWNER_AUTH_SLOT1_DIGEST_SIZE 8
 
// Offset of the PLAT_INTEG_AUTH_SLOT0 partition
#define OTP_CTRL_PARAM_PLAT_INTEG_AUTH_SLOT0_OFFSET 3144
 
// Size of the PLAT_INTEG_AUTH_SLOT0 partition
#define OTP_CTRL_PARAM_PLAT_INTEG_AUTH_SLOT0_SIZE 328
 
// Offset of PLAT_INTEG_AUTH_SLOT0_KEYMANIFEST_KEY
#define OTP_CTRL_PARAM_PLAT_INTEG_AUTH_SLOT0_KEYMANIFEST_KEY_OFFSET 3144
 
// Size of PLAT_INTEG_AUTH_SLOT0_KEYMANIFEST_KEY
#define OTP_CTRL_PARAM_PLAT_INTEG_AUTH_SLOT0_KEYMANIFEST_KEY_SIZE 160
 
// Offset of PLAT_INTEG_AUTH_SLOT0_UNLOCK4XFER_KEY
#define OTP_CTRL_PARAM_PLAT_INTEG_AUTH_SLOT0_UNLOCK4XFER_KEY_OFFSET 3304
 
// Size of PLAT_INTEG_AUTH_SLOT0_UNLOCK4XFER_KEY
#define OTP_CTRL_PARAM_PLAT_INTEG_AUTH_SLOT0_UNLOCK4XFER_KEY_SIZE 160
 
// Offset of PLAT_INTEG_AUTH_SLOT0_DIGEST
#define OTP_CTRL_PARAM_PLAT_INTEG_AUTH_SLOT0_DIGEST_OFFSET 3464
 
// Size of PLAT_INTEG_AUTH_SLOT0_DIGEST
#define OTP_CTRL_PARAM_PLAT_INTEG_AUTH_SLOT0_DIGEST_SIZE 8
 
// Offset of the PLAT_INTEG_AUTH_SLOT1 partition
#define OTP_CTRL_PARAM_PLAT_INTEG_AUTH_SLOT1_OFFSET 3472
 
// Size of the PLAT_INTEG_AUTH_SLOT1 partition
#define OTP_CTRL_PARAM_PLAT_INTEG_AUTH_SLOT1_SIZE 328
 
// Offset of PLAT_INTEG_AUTH_SLOT1_KEYMANIFEST_KEY
#define OTP_CTRL_PARAM_PLAT_INTEG_AUTH_SLOT1_KEYMANIFEST_KEY_OFFSET 3472
 
// Size of PLAT_INTEG_AUTH_SLOT1_KEYMANIFEST_KEY
#define OTP_CTRL_PARAM_PLAT_INTEG_AUTH_SLOT1_KEYMANIFEST_KEY_SIZE 160
 
// Offset of PLAT_INTEG_AUTH_SLOT1_UNLOCK4XFER_KEY
#define OTP_CTRL_PARAM_PLAT_INTEG_AUTH_SLOT1_UNLOCK4XFER_KEY_OFFSET 3632
 
// Size of PLAT_INTEG_AUTH_SLOT1_UNLOCK4XFER_KEY
#define OTP_CTRL_PARAM_PLAT_INTEG_AUTH_SLOT1_UNLOCK4XFER_KEY_SIZE 160
 
// Offset of PLAT_INTEG_AUTH_SLOT1_DIGEST
#define OTP_CTRL_PARAM_PLAT_INTEG_AUTH_SLOT1_DIGEST_OFFSET 3792
 
// Size of PLAT_INTEG_AUTH_SLOT1_DIGEST
#define OTP_CTRL_PARAM_PLAT_INTEG_AUTH_SLOT1_DIGEST_SIZE 8
 
// Offset of the PLAT_OWNER_AUTH_SLOT0 partition
#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT0_OFFSET 3800
 
// Size of the PLAT_OWNER_AUTH_SLOT0 partition
#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT0_SIZE 328
 
// Offset of PLAT_OWNER_AUTH_SLOT0_KEYMANIFEST_KEY
#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT0_KEYMANIFEST_KEY_OFFSET 3800
 
// Size of PLAT_OWNER_AUTH_SLOT0_KEYMANIFEST_KEY
#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT0_KEYMANIFEST_KEY_SIZE 160
 
// Offset of PLAT_OWNER_AUTH_SLOT0_UNLOCK4XFER_KEY
#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT0_UNLOCK4XFER_KEY_OFFSET 3960
 
// Size of PLAT_OWNER_AUTH_SLOT0_UNLOCK4XFER_KEY
#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT0_UNLOCK4XFER_KEY_SIZE 160
 
// Offset of PLAT_OWNER_AUTH_SLOT0_DIGEST
#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT0_DIGEST_OFFSET 4120
 
// Size of PLAT_OWNER_AUTH_SLOT0_DIGEST
#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT0_DIGEST_SIZE 8
 
// Offset of the PLAT_OWNER_AUTH_SLOT1 partition
#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT1_OFFSET 4128
 
// Size of the PLAT_OWNER_AUTH_SLOT1 partition
#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT1_SIZE 328
 
// Offset of PLAT_OWNER_AUTH_SLOT1_KEYMANIFEST_KEY
#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT1_KEYMANIFEST_KEY_OFFSET 4128
 
// Size of PLAT_OWNER_AUTH_SLOT1_KEYMANIFEST_KEY
#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT1_KEYMANIFEST_KEY_SIZE 160
 
// Offset of PLAT_OWNER_AUTH_SLOT1_UNLOCK4XFER_KEY
#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT1_UNLOCK4XFER_KEY_OFFSET 4288
 
// Size of PLAT_OWNER_AUTH_SLOT1_UNLOCK4XFER_KEY
#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT1_UNLOCK4XFER_KEY_SIZE 160
 
// Offset of PLAT_OWNER_AUTH_SLOT1_DIGEST
#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT1_DIGEST_OFFSET 4448
 
// Size of PLAT_OWNER_AUTH_SLOT1_DIGEST
#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT1_DIGEST_SIZE 8
 
// Offset of the PLAT_OWNER_AUTH_SLOT2 partition
#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT2_OFFSET 4456
 
// Size of the PLAT_OWNER_AUTH_SLOT2 partition
#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT2_SIZE 328
 
// Offset of PLAT_OWNER_AUTH_SLOT2_KEYMANIFEST_KEY
#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT2_KEYMANIFEST_KEY_OFFSET 4456
 
// Size of PLAT_OWNER_AUTH_SLOT2_KEYMANIFEST_KEY
#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT2_KEYMANIFEST_KEY_SIZE 160
 
// Offset of PLAT_OWNER_AUTH_SLOT2_UNLOCK4XFER_KEY
#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT2_UNLOCK4XFER_KEY_OFFSET 4616
 
// Size of PLAT_OWNER_AUTH_SLOT2_UNLOCK4XFER_KEY
#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT2_UNLOCK4XFER_KEY_SIZE 160
 
// Offset of PLAT_OWNER_AUTH_SLOT2_DIGEST
#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT2_DIGEST_OFFSET 4776
 
// Size of PLAT_OWNER_AUTH_SLOT2_DIGEST
#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT2_DIGEST_SIZE 8
 
// Offset of the PLAT_OWNER_AUTH_SLOT3 partition
#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT3_OFFSET 4784
 
// Size of the PLAT_OWNER_AUTH_SLOT3 partition
#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT3_SIZE 328
 
// Offset of PLAT_OWNER_AUTH_SLOT3_KEYMANIFEST_KEY
#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT3_KEYMANIFEST_KEY_OFFSET 4784
 
// Size of PLAT_OWNER_AUTH_SLOT3_KEYMANIFEST_KEY
#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT3_KEYMANIFEST_KEY_SIZE 160
 
// Offset of PLAT_OWNER_AUTH_SLOT3_UNLOCK4XFER_KEY
#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT3_UNLOCK4XFER_KEY_OFFSET 4944
 
// Size of PLAT_OWNER_AUTH_SLOT3_UNLOCK4XFER_KEY
#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT3_UNLOCK4XFER_KEY_SIZE 160
 
// Offset of PLAT_OWNER_AUTH_SLOT3_DIGEST
#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT3_DIGEST_OFFSET 5104
 
// Size of PLAT_OWNER_AUTH_SLOT3_DIGEST
#define OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT3_DIGEST_SIZE 8
 
// Offset of the EXT_NVM partition
#define OTP_CTRL_PARAM_EXT_NVM_OFFSET 5112
 
// Size of the EXT_NVM partition
#define OTP_CTRL_PARAM_EXT_NVM_SIZE 1024
 
// Offset of EXT_NVM_ANTIREPLAY_FRESHNESS_CNT
#define OTP_CTRL_PARAM_EXT_NVM_ANTIREPLAY_FRESHNESS_CNT_OFFSET 5112
 
// Size of EXT_NVM_ANTIREPLAY_FRESHNESS_CNT
#define OTP_CTRL_PARAM_EXT_NVM_ANTIREPLAY_FRESHNESS_CNT_SIZE 1024
 
// Offset of the ROM_PATCH partition
#define OTP_CTRL_PARAM_ROM_PATCH_OFFSET 6136
 
// Size of the ROM_PATCH partition
#define OTP_CTRL_PARAM_ROM_PATCH_SIZE 9848
 
// Offset of ROM_PATCH_DATA
#define OTP_CTRL_PARAM_ROM_PATCH_DATA_OFFSET 6136
 
// Size of ROM_PATCH_DATA
#define OTP_CTRL_PARAM_ROM_PATCH_DATA_SIZE 9192
 
// Offset of ROM_PATCH_DIGEST
#define OTP_CTRL_PARAM_ROM_PATCH_DIGEST_OFFSET 15976
 
// Size of ROM_PATCH_DIGEST
#define OTP_CTRL_PARAM_ROM_PATCH_DIGEST_SIZE 8
 
// Offset of the HW_CFG0 partition
#define OTP_CTRL_PARAM_HW_CFG0_OFFSET 15984
 
// Size of the HW_CFG0 partition
#define OTP_CTRL_PARAM_HW_CFG0_SIZE 72
 
// Offset of DEVICE_ID
#define OTP_CTRL_PARAM_DEVICE_ID_OFFSET 15984
 
// Size of DEVICE_ID
#define OTP_CTRL_PARAM_DEVICE_ID_SIZE 32
 
// Offset of MANUF_STATE
#define OTP_CTRL_PARAM_MANUF_STATE_OFFSET 16016
 
// Size of MANUF_STATE
#define OTP_CTRL_PARAM_MANUF_STATE_SIZE 32
 
// Offset of HW_CFG0_DIGEST
#define OTP_CTRL_PARAM_HW_CFG0_DIGEST_OFFSET 16048
 
// Size of HW_CFG0_DIGEST
#define OTP_CTRL_PARAM_HW_CFG0_DIGEST_SIZE 8
 
// Offset of the HW_CFG1 partition
#define OTP_CTRL_PARAM_HW_CFG1_OFFSET 16056
 
// Size of the HW_CFG1 partition
#define OTP_CTRL_PARAM_HW_CFG1_SIZE 16
 
// Offset of SOC_DBG_STATE
#define OTP_CTRL_PARAM_SOC_DBG_STATE_OFFSET 16056
 
// Size of SOC_DBG_STATE
#define OTP_CTRL_PARAM_SOC_DBG_STATE_SIZE 4
 
// Offset of EN_CSRNG_SW_APP_READ
#define OTP_CTRL_PARAM_EN_CSRNG_SW_APP_READ_OFFSET 16060
 
// Size of EN_CSRNG_SW_APP_READ
#define OTP_CTRL_PARAM_EN_CSRNG_SW_APP_READ_SIZE 1
 
// Offset of EN_SRAM_IFETCH
#define OTP_CTRL_PARAM_EN_SRAM_IFETCH_OFFSET 16061
 
// Size of EN_SRAM_IFETCH
#define OTP_CTRL_PARAM_EN_SRAM_IFETCH_SIZE 1
 
// Offset of HW_CFG1_DIGEST
#define OTP_CTRL_PARAM_HW_CFG1_DIGEST_OFFSET 16064
 
// Size of HW_CFG1_DIGEST
#define OTP_CTRL_PARAM_HW_CFG1_DIGEST_SIZE 8
 
// Offset of the SECRET0 partition
#define OTP_CTRL_PARAM_SECRET0_OFFSET 16072
 
// Size of the SECRET0 partition
#define OTP_CTRL_PARAM_SECRET0_SIZE 40
 
// Offset of TEST_UNLOCK_TOKEN
#define OTP_CTRL_PARAM_TEST_UNLOCK_TOKEN_OFFSET 16072
 
// Size of TEST_UNLOCK_TOKEN
#define OTP_CTRL_PARAM_TEST_UNLOCK_TOKEN_SIZE 16
 
// Offset of TEST_EXIT_TOKEN
#define OTP_CTRL_PARAM_TEST_EXIT_TOKEN_OFFSET 16088
 
// Size of TEST_EXIT_TOKEN
#define OTP_CTRL_PARAM_TEST_EXIT_TOKEN_SIZE 16
 
// Offset of SECRET0_DIGEST
#define OTP_CTRL_PARAM_SECRET0_DIGEST_OFFSET 16104
 
// Size of SECRET0_DIGEST
#define OTP_CTRL_PARAM_SECRET0_DIGEST_SIZE 8
 
// Offset of the SECRET1 partition
#define OTP_CTRL_PARAM_SECRET1_OFFSET 16112
 
// Size of the SECRET1 partition
#define OTP_CTRL_PARAM_SECRET1_SIZE 24
 
// Offset of SRAM_DATA_KEY_SEED
#define OTP_CTRL_PARAM_SRAM_DATA_KEY_SEED_OFFSET 16112
 
// Size of SRAM_DATA_KEY_SEED
#define OTP_CTRL_PARAM_SRAM_DATA_KEY_SEED_SIZE 16
 
// Offset of SECRET1_DIGEST
#define OTP_CTRL_PARAM_SECRET1_DIGEST_OFFSET 16128
 
// Size of SECRET1_DIGEST
#define OTP_CTRL_PARAM_SECRET1_DIGEST_SIZE 8
 
// Offset of the SECRET2 partition
#define OTP_CTRL_PARAM_SECRET2_OFFSET 16136
 
// Size of the SECRET2 partition
#define OTP_CTRL_PARAM_SECRET2_SIZE 120
 
// Offset of RMA_TOKEN
#define OTP_CTRL_PARAM_RMA_TOKEN_OFFSET 16136
 
// Size of RMA_TOKEN
#define OTP_CTRL_PARAM_RMA_TOKEN_SIZE 16
 
// Offset of CREATOR_ROOT_KEY_SHARE0
#define OTP_CTRL_PARAM_CREATOR_ROOT_KEY_SHARE0_OFFSET 16152
 
// Size of CREATOR_ROOT_KEY_SHARE0
#define OTP_CTRL_PARAM_CREATOR_ROOT_KEY_SHARE0_SIZE 32
 
// Offset of CREATOR_ROOT_KEY_SHARE1
#define OTP_CTRL_PARAM_CREATOR_ROOT_KEY_SHARE1_OFFSET 16184
 
// Size of CREATOR_ROOT_KEY_SHARE1
#define OTP_CTRL_PARAM_CREATOR_ROOT_KEY_SHARE1_SIZE 32
 
// Offset of CREATOR_SEED
#define OTP_CTRL_PARAM_CREATOR_SEED_OFFSET 16216
 
// Size of CREATOR_SEED
#define OTP_CTRL_PARAM_CREATOR_SEED_SIZE 32
 
// Offset of SECRET2_DIGEST
#define OTP_CTRL_PARAM_SECRET2_DIGEST_OFFSET 16248
 
// Size of SECRET2_DIGEST
#define OTP_CTRL_PARAM_SECRET2_DIGEST_SIZE 8
 
// Offset of the SECRET3 partition
#define OTP_CTRL_PARAM_SECRET3_OFFSET 16256
 
// Size of the SECRET3 partition
#define OTP_CTRL_PARAM_SECRET3_SIZE 40
 
// Offset of OWNER_SEED
#define OTP_CTRL_PARAM_OWNER_SEED_OFFSET 16256
 
// Size of OWNER_SEED
#define OTP_CTRL_PARAM_OWNER_SEED_SIZE 32
 
// Offset of SECRET3_DIGEST
#define OTP_CTRL_PARAM_SECRET3_DIGEST_OFFSET 16288
 
// Size of SECRET3_DIGEST
#define OTP_CTRL_PARAM_SECRET3_DIGEST_SIZE 8
 
// Offset of the LIFE_CYCLE partition
#define OTP_CTRL_PARAM_LIFE_CYCLE_OFFSET 16296
 
// Size of the LIFE_CYCLE partition
#define OTP_CTRL_PARAM_LIFE_CYCLE_SIZE 88
 
// Offset of LC_TRANSITION_CNT
#define OTP_CTRL_PARAM_LC_TRANSITION_CNT_OFFSET 16296
 
// Size of LC_TRANSITION_CNT
#define OTP_CTRL_PARAM_LC_TRANSITION_CNT_SIZE 48
 
// Offset of LC_STATE
#define OTP_CTRL_PARAM_LC_STATE_OFFSET 16344
 
// Size of LC_STATE
#define OTP_CTRL_PARAM_LC_STATE_SIZE 40
 
// Number of alerts
#define OTP_CTRL_PARAM_NUM_ALERTS 5
 
// Register width
#define OTP_CTRL_PARAM_REG_WIDTH 32
 
// Common Interrupt Offsets
#define OTP_CTRL_INTR_COMMON_OTP_OPERATION_DONE_BIT 0
#define OTP_CTRL_INTR_COMMON_OTP_ERROR_BIT 1
 
// Interrupt State Register
#define OTP_CTRL_INTR_STATE_REG_OFFSET 0x0
#define OTP_CTRL_INTR_STATE_REG_RESVAL 0x0u
#define OTP_CTRL_INTR_STATE_OTP_OPERATION_DONE_BIT 0
#define OTP_CTRL_INTR_STATE_OTP_ERROR_BIT 1
 
// Interrupt Enable Register
#define OTP_CTRL_INTR_ENABLE_REG_OFFSET 0x4
#define OTP_CTRL_INTR_ENABLE_REG_RESVAL 0x0u
#define OTP_CTRL_INTR_ENABLE_OTP_OPERATION_DONE_BIT 0
#define OTP_CTRL_INTR_ENABLE_OTP_ERROR_BIT 1
 
// Interrupt Test Register
#define OTP_CTRL_INTR_TEST_REG_OFFSET 0x8
#define OTP_CTRL_INTR_TEST_REG_RESVAL 0x0u
#define OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_BIT 0
#define OTP_CTRL_INTR_TEST_OTP_ERROR_BIT 1
 
// Alert Test Register
#define OTP_CTRL_ALERT_TEST_REG_OFFSET 0xc
#define OTP_CTRL_ALERT_TEST_REG_RESVAL 0x0u
#define OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_BIT 0
#define OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_BIT 1
#define OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_BIT 2
#define OTP_CTRL_ALERT_TEST_FATAL_PRIM_OTP_ALERT_BIT 3
#define OTP_CTRL_ALERT_TEST_RECOV_PRIM_OTP_ALERT_BIT 4
 
// OTP status register.
#define OTP_CTRL_STATUS_REG_OFFSET 0x10
#define OTP_CTRL_STATUS_REG_RESVAL 0x0u
#define OTP_CTRL_STATUS_VENDOR_TEST_ERROR_BIT 0
#define OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_BIT 1
#define OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_BIT 2
#define OTP_CTRL_STATUS_OWNERSHIP_SLOT_STATE_ERROR_BIT 3
#define OTP_CTRL_STATUS_ROT_CREATOR_AUTH_ERROR_BIT 4
#define OTP_CTRL_STATUS_ROT_OWNER_AUTH_SLOT0_ERROR_BIT 5
#define OTP_CTRL_STATUS_ROT_OWNER_AUTH_SLOT1_ERROR_BIT 6
#define OTP_CTRL_STATUS_PLAT_INTEG_AUTH_SLOT0_ERROR_BIT 7
#define OTP_CTRL_STATUS_PLAT_INTEG_AUTH_SLOT1_ERROR_BIT 8
#define OTP_CTRL_STATUS_PLAT_OWNER_AUTH_SLOT0_ERROR_BIT 9
#define OTP_CTRL_STATUS_PLAT_OWNER_AUTH_SLOT1_ERROR_BIT 10
#define OTP_CTRL_STATUS_PLAT_OWNER_AUTH_SLOT2_ERROR_BIT 11
#define OTP_CTRL_STATUS_PLAT_OWNER_AUTH_SLOT3_ERROR_BIT 12
#define OTP_CTRL_STATUS_EXT_NVM_ERROR_BIT 13
#define OTP_CTRL_STATUS_ROM_PATCH_ERROR_BIT 14
#define OTP_CTRL_STATUS_HW_CFG0_ERROR_BIT 15
#define OTP_CTRL_STATUS_HW_CFG1_ERROR_BIT 16
#define OTP_CTRL_STATUS_SECRET0_ERROR_BIT 17
#define OTP_CTRL_STATUS_SECRET1_ERROR_BIT 18
#define OTP_CTRL_STATUS_SECRET2_ERROR_BIT 19
#define OTP_CTRL_STATUS_SECRET3_ERROR_BIT 20
#define OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_BIT 21
#define OTP_CTRL_STATUS_DAI_ERROR_BIT 22
#define OTP_CTRL_STATUS_LCI_ERROR_BIT 23
#define OTP_CTRL_STATUS_TIMEOUT_ERROR_BIT 24
#define OTP_CTRL_STATUS_LFSR_FSM_ERROR_BIT 25
#define OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_BIT 26
#define OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_BIT 27
#define OTP_CTRL_STATUS_BUS_INTEG_ERROR_BIT 28
#define OTP_CTRL_STATUS_DAI_IDLE_BIT 29
#define OTP_CTRL_STATUS_CHECK_PENDING_BIT 30
 
// This register holds information about error conditions that occurred in
// the agents
#define OTP_CTRL_ERR_CODE_ERR_CODE_FIELD_WIDTH 3
#define OTP_CTRL_ERR_CODE_MULTIREG_COUNT 24
 
// This register holds information about error conditions that occurred in
// the agents
#define OTP_CTRL_ERR_CODE_0_REG_OFFSET 0x14
#define OTP_CTRL_ERR_CODE_0_REG_RESVAL 0x0u
#define OTP_CTRL_ERR_CODE_0_ERR_CODE_0_MASK 0x7u
#define OTP_CTRL_ERR_CODE_0_ERR_CODE_0_OFFSET 0
#define OTP_CTRL_ERR_CODE_0_ERR_CODE_0_FIELD \
  ((bitfield_field32_t) { .mask = OTP_CTRL_ERR_CODE_0_ERR_CODE_0_MASK, .index = OTP_CTRL_ERR_CODE_0_ERR_CODE_0_OFFSET })
#define OTP_CTRL_ERR_CODE_0_ERR_CODE_0_VALUE_NO_ERROR 0x0
#define OTP_CTRL_ERR_CODE_0_ERR_CODE_0_VALUE_MACRO_ERROR 0x1
#define OTP_CTRL_ERR_CODE_0_ERR_CODE_0_VALUE_MACRO_ECC_CORR_ERROR 0x2
#define OTP_CTRL_ERR_CODE_0_ERR_CODE_0_VALUE_MACRO_ECC_UNCORR_ERROR 0x3
#define OTP_CTRL_ERR_CODE_0_ERR_CODE_0_VALUE_MACRO_WRITE_BLANK_ERROR 0x4
#define OTP_CTRL_ERR_CODE_0_ERR_CODE_0_VALUE_ACCESS_ERROR 0x5
#define OTP_CTRL_ERR_CODE_0_ERR_CODE_0_VALUE_CHECK_FAIL_ERROR 0x6
#define OTP_CTRL_ERR_CODE_0_ERR_CODE_0_VALUE_FSM_STATE_ERROR 0x7
 
// This register holds information about error conditions that occurred in
// the agents
#define OTP_CTRL_ERR_CODE_1_REG_OFFSET 0x18
#define OTP_CTRL_ERR_CODE_1_REG_RESVAL 0x0u
#define OTP_CTRL_ERR_CODE_1_ERR_CODE_1_MASK 0x7u
#define OTP_CTRL_ERR_CODE_1_ERR_CODE_1_OFFSET 0
#define OTP_CTRL_ERR_CODE_1_ERR_CODE_1_FIELD \
  ((bitfield_field32_t) { .mask = OTP_CTRL_ERR_CODE_1_ERR_CODE_1_MASK, .index = OTP_CTRL_ERR_CODE_1_ERR_CODE_1_OFFSET })
 
// This register holds information about error conditions that occurred in
// the agents
#define OTP_CTRL_ERR_CODE_2_REG_OFFSET 0x1c
#define OTP_CTRL_ERR_CODE_2_REG_RESVAL 0x0u
#define OTP_CTRL_ERR_CODE_2_ERR_CODE_2_MASK 0x7u
#define OTP_CTRL_ERR_CODE_2_ERR_CODE_2_OFFSET 0
#define OTP_CTRL_ERR_CODE_2_ERR_CODE_2_FIELD \
  ((bitfield_field32_t) { .mask = OTP_CTRL_ERR_CODE_2_ERR_CODE_2_MASK, .index = OTP_CTRL_ERR_CODE_2_ERR_CODE_2_OFFSET })
 
// This register holds information about error conditions that occurred in
// the agents
#define OTP_CTRL_ERR_CODE_3_REG_OFFSET 0x20
#define OTP_CTRL_ERR_CODE_3_REG_RESVAL 0x0u
#define OTP_CTRL_ERR_CODE_3_ERR_CODE_3_MASK 0x7u
#define OTP_CTRL_ERR_CODE_3_ERR_CODE_3_OFFSET 0
#define OTP_CTRL_ERR_CODE_3_ERR_CODE_3_FIELD \
  ((bitfield_field32_t) { .mask = OTP_CTRL_ERR_CODE_3_ERR_CODE_3_MASK, .index = OTP_CTRL_ERR_CODE_3_ERR_CODE_3_OFFSET })
 
// This register holds information about error conditions that occurred in
// the agents
#define OTP_CTRL_ERR_CODE_4_REG_OFFSET 0x24
#define OTP_CTRL_ERR_CODE_4_REG_RESVAL 0x0u
#define OTP_CTRL_ERR_CODE_4_ERR_CODE_4_MASK 0x7u
#define OTP_CTRL_ERR_CODE_4_ERR_CODE_4_OFFSET 0
#define OTP_CTRL_ERR_CODE_4_ERR_CODE_4_FIELD \
  ((bitfield_field32_t) { .mask = OTP_CTRL_ERR_CODE_4_ERR_CODE_4_MASK, .index = OTP_CTRL_ERR_CODE_4_ERR_CODE_4_OFFSET })
 
// This register holds information about error conditions that occurred in
// the agents
#define OTP_CTRL_ERR_CODE_5_REG_OFFSET 0x28
#define OTP_CTRL_ERR_CODE_5_REG_RESVAL 0x0u
#define OTP_CTRL_ERR_CODE_5_ERR_CODE_5_MASK 0x7u
#define OTP_CTRL_ERR_CODE_5_ERR_CODE_5_OFFSET 0
#define OTP_CTRL_ERR_CODE_5_ERR_CODE_5_FIELD \
  ((bitfield_field32_t) { .mask = OTP_CTRL_ERR_CODE_5_ERR_CODE_5_MASK, .index = OTP_CTRL_ERR_CODE_5_ERR_CODE_5_OFFSET })
 
// This register holds information about error conditions that occurred in
// the agents
#define OTP_CTRL_ERR_CODE_6_REG_OFFSET 0x2c
#define OTP_CTRL_ERR_CODE_6_REG_RESVAL 0x0u
#define OTP_CTRL_ERR_CODE_6_ERR_CODE_6_MASK 0x7u
#define OTP_CTRL_ERR_CODE_6_ERR_CODE_6_OFFSET 0
#define OTP_CTRL_ERR_CODE_6_ERR_CODE_6_FIELD \
  ((bitfield_field32_t) { .mask = OTP_CTRL_ERR_CODE_6_ERR_CODE_6_MASK, .index = OTP_CTRL_ERR_CODE_6_ERR_CODE_6_OFFSET })
 
// This register holds information about error conditions that occurred in
// the agents
#define OTP_CTRL_ERR_CODE_7_REG_OFFSET 0x30
#define OTP_CTRL_ERR_CODE_7_REG_RESVAL 0x0u
#define OTP_CTRL_ERR_CODE_7_ERR_CODE_7_MASK 0x7u
#define OTP_CTRL_ERR_CODE_7_ERR_CODE_7_OFFSET 0
#define OTP_CTRL_ERR_CODE_7_ERR_CODE_7_FIELD \
  ((bitfield_field32_t) { .mask = OTP_CTRL_ERR_CODE_7_ERR_CODE_7_MASK, .index = OTP_CTRL_ERR_CODE_7_ERR_CODE_7_OFFSET })
 
// This register holds information about error conditions that occurred in
// the agents
#define OTP_CTRL_ERR_CODE_8_REG_OFFSET 0x34
#define OTP_CTRL_ERR_CODE_8_REG_RESVAL 0x0u
#define OTP_CTRL_ERR_CODE_8_ERR_CODE_8_MASK 0x7u
#define OTP_CTRL_ERR_CODE_8_ERR_CODE_8_OFFSET 0
#define OTP_CTRL_ERR_CODE_8_ERR_CODE_8_FIELD \
  ((bitfield_field32_t) { .mask = OTP_CTRL_ERR_CODE_8_ERR_CODE_8_MASK, .index = OTP_CTRL_ERR_CODE_8_ERR_CODE_8_OFFSET })
 
// This register holds information about error conditions that occurred in
// the agents
#define OTP_CTRL_ERR_CODE_9_REG_OFFSET 0x38
#define OTP_CTRL_ERR_CODE_9_REG_RESVAL 0x0u
#define OTP_CTRL_ERR_CODE_9_ERR_CODE_9_MASK 0x7u
#define OTP_CTRL_ERR_CODE_9_ERR_CODE_9_OFFSET 0
#define OTP_CTRL_ERR_CODE_9_ERR_CODE_9_FIELD \
  ((bitfield_field32_t) { .mask = OTP_CTRL_ERR_CODE_9_ERR_CODE_9_MASK, .index = OTP_CTRL_ERR_CODE_9_ERR_CODE_9_OFFSET })
 
// This register holds information about error conditions that occurred in
// the agents
#define OTP_CTRL_ERR_CODE_10_REG_OFFSET 0x3c
#define OTP_CTRL_ERR_CODE_10_REG_RESVAL 0x0u
#define OTP_CTRL_ERR_CODE_10_ERR_CODE_10_MASK 0x7u
#define OTP_CTRL_ERR_CODE_10_ERR_CODE_10_OFFSET 0
#define OTP_CTRL_ERR_CODE_10_ERR_CODE_10_FIELD \
  ((bitfield_field32_t) { .mask = OTP_CTRL_ERR_CODE_10_ERR_CODE_10_MASK, .index = OTP_CTRL_ERR_CODE_10_ERR_CODE_10_OFFSET })
 
// This register holds information about error conditions that occurred in
// the agents
#define OTP_CTRL_ERR_CODE_11_REG_OFFSET 0x40
#define OTP_CTRL_ERR_CODE_11_REG_RESVAL 0x0u
#define OTP_CTRL_ERR_CODE_11_ERR_CODE_11_MASK 0x7u
#define OTP_CTRL_ERR_CODE_11_ERR_CODE_11_OFFSET 0
#define OTP_CTRL_ERR_CODE_11_ERR_CODE_11_FIELD \
  ((bitfield_field32_t) { .mask = OTP_CTRL_ERR_CODE_11_ERR_CODE_11_MASK, .index = OTP_CTRL_ERR_CODE_11_ERR_CODE_11_OFFSET })
 
// This register holds information about error conditions that occurred in
// the agents
#define OTP_CTRL_ERR_CODE_12_REG_OFFSET 0x44
#define OTP_CTRL_ERR_CODE_12_REG_RESVAL 0x0u
#define OTP_CTRL_ERR_CODE_12_ERR_CODE_12_MASK 0x7u
#define OTP_CTRL_ERR_CODE_12_ERR_CODE_12_OFFSET 0
#define OTP_CTRL_ERR_CODE_12_ERR_CODE_12_FIELD \
  ((bitfield_field32_t) { .mask = OTP_CTRL_ERR_CODE_12_ERR_CODE_12_MASK, .index = OTP_CTRL_ERR_CODE_12_ERR_CODE_12_OFFSET })
 
// This register holds information about error conditions that occurred in
// the agents
#define OTP_CTRL_ERR_CODE_13_REG_OFFSET 0x48
#define OTP_CTRL_ERR_CODE_13_REG_RESVAL 0x0u
#define OTP_CTRL_ERR_CODE_13_ERR_CODE_13_MASK 0x7u
#define OTP_CTRL_ERR_CODE_13_ERR_CODE_13_OFFSET 0
#define OTP_CTRL_ERR_CODE_13_ERR_CODE_13_FIELD \
  ((bitfield_field32_t) { .mask = OTP_CTRL_ERR_CODE_13_ERR_CODE_13_MASK, .index = OTP_CTRL_ERR_CODE_13_ERR_CODE_13_OFFSET })
 
// This register holds information about error conditions that occurred in
// the agents
#define OTP_CTRL_ERR_CODE_14_REG_OFFSET 0x4c
#define OTP_CTRL_ERR_CODE_14_REG_RESVAL 0x0u
#define OTP_CTRL_ERR_CODE_14_ERR_CODE_14_MASK 0x7u
#define OTP_CTRL_ERR_CODE_14_ERR_CODE_14_OFFSET 0
#define OTP_CTRL_ERR_CODE_14_ERR_CODE_14_FIELD \
  ((bitfield_field32_t) { .mask = OTP_CTRL_ERR_CODE_14_ERR_CODE_14_MASK, .index = OTP_CTRL_ERR_CODE_14_ERR_CODE_14_OFFSET })
 
// This register holds information about error conditions that occurred in
// the agents
#define OTP_CTRL_ERR_CODE_15_REG_OFFSET 0x50
#define OTP_CTRL_ERR_CODE_15_REG_RESVAL 0x0u
#define OTP_CTRL_ERR_CODE_15_ERR_CODE_15_MASK 0x7u
#define OTP_CTRL_ERR_CODE_15_ERR_CODE_15_OFFSET 0
#define OTP_CTRL_ERR_CODE_15_ERR_CODE_15_FIELD \
  ((bitfield_field32_t) { .mask = OTP_CTRL_ERR_CODE_15_ERR_CODE_15_MASK, .index = OTP_CTRL_ERR_CODE_15_ERR_CODE_15_OFFSET })
 
// This register holds information about error conditions that occurred in
// the agents
#define OTP_CTRL_ERR_CODE_16_REG_OFFSET 0x54
#define OTP_CTRL_ERR_CODE_16_REG_RESVAL 0x0u
#define OTP_CTRL_ERR_CODE_16_ERR_CODE_16_MASK 0x7u
#define OTP_CTRL_ERR_CODE_16_ERR_CODE_16_OFFSET 0
#define OTP_CTRL_ERR_CODE_16_ERR_CODE_16_FIELD \
  ((bitfield_field32_t) { .mask = OTP_CTRL_ERR_CODE_16_ERR_CODE_16_MASK, .index = OTP_CTRL_ERR_CODE_16_ERR_CODE_16_OFFSET })
 
// This register holds information about error conditions that occurred in
// the agents
#define OTP_CTRL_ERR_CODE_17_REG_OFFSET 0x58
#define OTP_CTRL_ERR_CODE_17_REG_RESVAL 0x0u
#define OTP_CTRL_ERR_CODE_17_ERR_CODE_17_MASK 0x7u
#define OTP_CTRL_ERR_CODE_17_ERR_CODE_17_OFFSET 0
#define OTP_CTRL_ERR_CODE_17_ERR_CODE_17_FIELD \
  ((bitfield_field32_t) { .mask = OTP_CTRL_ERR_CODE_17_ERR_CODE_17_MASK, .index = OTP_CTRL_ERR_CODE_17_ERR_CODE_17_OFFSET })
 
// This register holds information about error conditions that occurred in
// the agents
#define OTP_CTRL_ERR_CODE_18_REG_OFFSET 0x5c
#define OTP_CTRL_ERR_CODE_18_REG_RESVAL 0x0u
#define OTP_CTRL_ERR_CODE_18_ERR_CODE_18_MASK 0x7u
#define OTP_CTRL_ERR_CODE_18_ERR_CODE_18_OFFSET 0
#define OTP_CTRL_ERR_CODE_18_ERR_CODE_18_FIELD \
  ((bitfield_field32_t) { .mask = OTP_CTRL_ERR_CODE_18_ERR_CODE_18_MASK, .index = OTP_CTRL_ERR_CODE_18_ERR_CODE_18_OFFSET })
 
// This register holds information about error conditions that occurred in
// the agents
#define OTP_CTRL_ERR_CODE_19_REG_OFFSET 0x60
#define OTP_CTRL_ERR_CODE_19_REG_RESVAL 0x0u
#define OTP_CTRL_ERR_CODE_19_ERR_CODE_19_MASK 0x7u
#define OTP_CTRL_ERR_CODE_19_ERR_CODE_19_OFFSET 0
#define OTP_CTRL_ERR_CODE_19_ERR_CODE_19_FIELD \
  ((bitfield_field32_t) { .mask = OTP_CTRL_ERR_CODE_19_ERR_CODE_19_MASK, .index = OTP_CTRL_ERR_CODE_19_ERR_CODE_19_OFFSET })
 
// This register holds information about error conditions that occurred in
// the agents
#define OTP_CTRL_ERR_CODE_20_REG_OFFSET 0x64
#define OTP_CTRL_ERR_CODE_20_REG_RESVAL 0x0u
#define OTP_CTRL_ERR_CODE_20_ERR_CODE_20_MASK 0x7u
#define OTP_CTRL_ERR_CODE_20_ERR_CODE_20_OFFSET 0
#define OTP_CTRL_ERR_CODE_20_ERR_CODE_20_FIELD \
  ((bitfield_field32_t) { .mask = OTP_CTRL_ERR_CODE_20_ERR_CODE_20_MASK, .index = OTP_CTRL_ERR_CODE_20_ERR_CODE_20_OFFSET })
 
// This register holds information about error conditions that occurred in
// the agents
#define OTP_CTRL_ERR_CODE_21_REG_OFFSET 0x68
#define OTP_CTRL_ERR_CODE_21_REG_RESVAL 0x0u
#define OTP_CTRL_ERR_CODE_21_ERR_CODE_21_MASK 0x7u
#define OTP_CTRL_ERR_CODE_21_ERR_CODE_21_OFFSET 0
#define OTP_CTRL_ERR_CODE_21_ERR_CODE_21_FIELD \
  ((bitfield_field32_t) { .mask = OTP_CTRL_ERR_CODE_21_ERR_CODE_21_MASK, .index = OTP_CTRL_ERR_CODE_21_ERR_CODE_21_OFFSET })
 
// This register holds information about error conditions that occurred in
// the agents
#define OTP_CTRL_ERR_CODE_22_REG_OFFSET 0x6c
#define OTP_CTRL_ERR_CODE_22_REG_RESVAL 0x0u
#define OTP_CTRL_ERR_CODE_22_ERR_CODE_22_MASK 0x7u
#define OTP_CTRL_ERR_CODE_22_ERR_CODE_22_OFFSET 0
#define OTP_CTRL_ERR_CODE_22_ERR_CODE_22_FIELD \
  ((bitfield_field32_t) { .mask = OTP_CTRL_ERR_CODE_22_ERR_CODE_22_MASK, .index = OTP_CTRL_ERR_CODE_22_ERR_CODE_22_OFFSET })
 
// This register holds information about error conditions that occurred in
// the agents
#define OTP_CTRL_ERR_CODE_23_REG_OFFSET 0x70
#define OTP_CTRL_ERR_CODE_23_REG_RESVAL 0x0u
#define OTP_CTRL_ERR_CODE_23_ERR_CODE_23_MASK 0x7u
#define OTP_CTRL_ERR_CODE_23_ERR_CODE_23_OFFSET 0
#define OTP_CTRL_ERR_CODE_23_ERR_CODE_23_FIELD \
  ((bitfield_field32_t) { .mask = OTP_CTRL_ERR_CODE_23_ERR_CODE_23_MASK, .index = OTP_CTRL_ERR_CODE_23_ERR_CODE_23_OFFSET })
 
// Register write enable for all direct access interface registers.
#define OTP_CTRL_DIRECT_ACCESS_REGWEN_REG_OFFSET 0x74
#define OTP_CTRL_DIRECT_ACCESS_REGWEN_REG_RESVAL 0x1u
#define OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_BIT 0
 
// Command register for direct accesses.
#define OTP_CTRL_DIRECT_ACCESS_CMD_REG_OFFSET 0x78
#define OTP_CTRL_DIRECT_ACCESS_CMD_REG_RESVAL 0x0u
#define OTP_CTRL_DIRECT_ACCESS_CMD_RD_BIT 0
#define OTP_CTRL_DIRECT_ACCESS_CMD_WR_BIT 1
#define OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_BIT 2
 
// Address register for direct accesses.
#define OTP_CTRL_DIRECT_ACCESS_ADDRESS_REG_OFFSET 0x7c
#define OTP_CTRL_DIRECT_ACCESS_ADDRESS_REG_RESVAL 0x0u
#define OTP_CTRL_DIRECT_ACCESS_ADDRESS_DIRECT_ACCESS_ADDRESS_MASK 0x3fffu
#define OTP_CTRL_DIRECT_ACCESS_ADDRESS_DIRECT_ACCESS_ADDRESS_OFFSET 0
#define OTP_CTRL_DIRECT_ACCESS_ADDRESS_DIRECT_ACCESS_ADDRESS_FIELD \
  ((bitfield_field32_t) { .mask = OTP_CTRL_DIRECT_ACCESS_ADDRESS_DIRECT_ACCESS_ADDRESS_MASK, .index = OTP_CTRL_DIRECT_ACCESS_ADDRESS_DIRECT_ACCESS_ADDRESS_OFFSET })
 
// Write data for direct accesses.
#define OTP_CTRL_DIRECT_ACCESS_WDATA_DIRECT_ACCESS_WDATA_FIELD_WIDTH 32
#define OTP_CTRL_DIRECT_ACCESS_WDATA_MULTIREG_COUNT 2
 
// Write data for direct accesses.
#define OTP_CTRL_DIRECT_ACCESS_WDATA_0_REG_OFFSET 0x80
#define OTP_CTRL_DIRECT_ACCESS_WDATA_0_REG_RESVAL 0x0u
 
// Write data for direct accesses.
#define OTP_CTRL_DIRECT_ACCESS_WDATA_1_REG_OFFSET 0x84
#define OTP_CTRL_DIRECT_ACCESS_WDATA_1_REG_RESVAL 0x0u
 
// Read data for direct accesses.
#define OTP_CTRL_DIRECT_ACCESS_RDATA_DIRECT_ACCESS_RDATA_FIELD_WIDTH 32
#define OTP_CTRL_DIRECT_ACCESS_RDATA_MULTIREG_COUNT 2
 
// Read data for direct accesses.
#define OTP_CTRL_DIRECT_ACCESS_RDATA_0_REG_OFFSET 0x88
#define OTP_CTRL_DIRECT_ACCESS_RDATA_0_REG_RESVAL 0x0u
 
// Read data for direct accesses.
#define OTP_CTRL_DIRECT_ACCESS_RDATA_1_REG_OFFSET 0x8c
#define OTP_CTRL_DIRECT_ACCESS_RDATA_1_REG_RESVAL 0x0u
 
// Register write enable for !!CHECK_TRIGGER.
#define OTP_CTRL_CHECK_TRIGGER_REGWEN_REG_OFFSET 0x90
#define OTP_CTRL_CHECK_TRIGGER_REGWEN_REG_RESVAL 0x1u
#define OTP_CTRL_CHECK_TRIGGER_REGWEN_CHECK_TRIGGER_REGWEN_BIT 0
 
// Command register for direct accesses.
#define OTP_CTRL_CHECK_TRIGGER_REG_OFFSET 0x94
#define OTP_CTRL_CHECK_TRIGGER_REG_RESVAL 0x0u
#define OTP_CTRL_CHECK_TRIGGER_INTEGRITY_BIT 0
#define OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_BIT 1
 
// Register write enable for !!INTEGRITY_CHECK_PERIOD and
// !!CONSISTENCY_CHECK_PERIOD.
#define OTP_CTRL_CHECK_REGWEN_REG_OFFSET 0x98
#define OTP_CTRL_CHECK_REGWEN_REG_RESVAL 0x1u
#define OTP_CTRL_CHECK_REGWEN_CHECK_REGWEN_BIT 0
 
// Timeout value for the integrity and consistency checks.
#define OTP_CTRL_CHECK_TIMEOUT_REG_OFFSET 0x9c
#define OTP_CTRL_CHECK_TIMEOUT_REG_RESVAL 0x0u
 
// This value specifies the maximum period that can be generated pseudo-
// randomly.
#define OTP_CTRL_INTEGRITY_CHECK_PERIOD_REG_OFFSET 0xa0
#define OTP_CTRL_INTEGRITY_CHECK_PERIOD_REG_RESVAL 0x0u
 
// This value specifies the maximum period that can be generated pseudo-
// randomly.
#define OTP_CTRL_CONSISTENCY_CHECK_PERIOD_REG_OFFSET 0xa4
#define OTP_CTRL_CONSISTENCY_CHECK_PERIOD_REG_RESVAL 0x0u
 
// Runtime read lock for the VENDOR_TEST partition.
#define OTP_CTRL_VENDOR_TEST_READ_LOCK_REG_OFFSET 0xa8
#define OTP_CTRL_VENDOR_TEST_READ_LOCK_REG_RESVAL 0x1u
#define OTP_CTRL_VENDOR_TEST_READ_LOCK_VENDOR_TEST_READ_LOCK_BIT 0
 
// Runtime read lock for the CREATOR_SW_CFG partition.
#define OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_REG_OFFSET 0xac
#define OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_REG_RESVAL 0x1u
#define OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_CREATOR_SW_CFG_READ_LOCK_BIT 0
 
// Runtime read lock for the OWNER_SW_CFG partition.
#define OTP_CTRL_OWNER_SW_CFG_READ_LOCK_REG_OFFSET 0xb0
#define OTP_CTRL_OWNER_SW_CFG_READ_LOCK_REG_RESVAL 0x1u
#define OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OWNER_SW_CFG_READ_LOCK_BIT 0
 
// Runtime read lock for the OWNERSHIP_SLOT_STATE partition.
#define OTP_CTRL_OWNERSHIP_SLOT_STATE_READ_LOCK_REG_OFFSET 0xb4
#define OTP_CTRL_OWNERSHIP_SLOT_STATE_READ_LOCK_REG_RESVAL 0x1u
#define OTP_CTRL_OWNERSHIP_SLOT_STATE_READ_LOCK_OWNERSHIP_SLOT_STATE_READ_LOCK_BIT \
  0
 
// Runtime read lock for the ROT_CREATOR_AUTH partition.
#define OTP_CTRL_ROT_CREATOR_AUTH_READ_LOCK_REG_OFFSET 0xb8
#define OTP_CTRL_ROT_CREATOR_AUTH_READ_LOCK_REG_RESVAL 0x1u
#define OTP_CTRL_ROT_CREATOR_AUTH_READ_LOCK_ROT_CREATOR_AUTH_READ_LOCK_BIT 0
 
// Runtime read lock for the ROT_OWNER_AUTH_SLOT0 partition.
#define OTP_CTRL_ROT_OWNER_AUTH_SLOT0_READ_LOCK_REG_OFFSET 0xbc
#define OTP_CTRL_ROT_OWNER_AUTH_SLOT0_READ_LOCK_REG_RESVAL 0x1u
#define OTP_CTRL_ROT_OWNER_AUTH_SLOT0_READ_LOCK_ROT_OWNER_AUTH_SLOT0_READ_LOCK_BIT \
  0
 
// Runtime read lock for the ROT_OWNER_AUTH_SLOT1 partition.
#define OTP_CTRL_ROT_OWNER_AUTH_SLOT1_READ_LOCK_REG_OFFSET 0xc0
#define OTP_CTRL_ROT_OWNER_AUTH_SLOT1_READ_LOCK_REG_RESVAL 0x1u
#define OTP_CTRL_ROT_OWNER_AUTH_SLOT1_READ_LOCK_ROT_OWNER_AUTH_SLOT1_READ_LOCK_BIT \
  0
 
// Runtime read lock for the PLAT_INTEG_AUTH_SLOT0 partition.
#define OTP_CTRL_PLAT_INTEG_AUTH_SLOT0_READ_LOCK_REG_OFFSET 0xc4
#define OTP_CTRL_PLAT_INTEG_AUTH_SLOT0_READ_LOCK_REG_RESVAL 0x1u
#define OTP_CTRL_PLAT_INTEG_AUTH_SLOT0_READ_LOCK_PLAT_INTEG_AUTH_SLOT0_READ_LOCK_BIT \
  0
 
// Runtime read lock for the PLAT_INTEG_AUTH_SLOT1 partition.
#define OTP_CTRL_PLAT_INTEG_AUTH_SLOT1_READ_LOCK_REG_OFFSET 0xc8
#define OTP_CTRL_PLAT_INTEG_AUTH_SLOT1_READ_LOCK_REG_RESVAL 0x1u
#define OTP_CTRL_PLAT_INTEG_AUTH_SLOT1_READ_LOCK_PLAT_INTEG_AUTH_SLOT1_READ_LOCK_BIT \
  0
 
// Runtime read lock for the PLAT_OWNER_AUTH_SLOT0 partition.
#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT0_READ_LOCK_REG_OFFSET 0xcc
#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT0_READ_LOCK_REG_RESVAL 0x1u
#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT0_READ_LOCK_PLAT_OWNER_AUTH_SLOT0_READ_LOCK_BIT \
  0
 
// Runtime read lock for the PLAT_OWNER_AUTH_SLOT1 partition.
#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT1_READ_LOCK_REG_OFFSET 0xd0
#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT1_READ_LOCK_REG_RESVAL 0x1u
#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT1_READ_LOCK_PLAT_OWNER_AUTH_SLOT1_READ_LOCK_BIT \
  0
 
// Runtime read lock for the PLAT_OWNER_AUTH_SLOT2 partition.
#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT2_READ_LOCK_REG_OFFSET 0xd4
#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT2_READ_LOCK_REG_RESVAL 0x1u
#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT2_READ_LOCK_PLAT_OWNER_AUTH_SLOT2_READ_LOCK_BIT \
  0
 
// Runtime read lock for the PLAT_OWNER_AUTH_SLOT3 partition.
#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT3_READ_LOCK_REG_OFFSET 0xd8
#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT3_READ_LOCK_REG_RESVAL 0x1u
#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT3_READ_LOCK_PLAT_OWNER_AUTH_SLOT3_READ_LOCK_BIT \
  0
 
// Runtime read lock for the EXT_NVM partition.
#define OTP_CTRL_EXT_NVM_READ_LOCK_REG_OFFSET 0xdc
#define OTP_CTRL_EXT_NVM_READ_LOCK_REG_RESVAL 0x1u
#define OTP_CTRL_EXT_NVM_READ_LOCK_EXT_NVM_READ_LOCK_BIT 0
 
// Runtime read lock for the ROM_PATCH partition.
#define OTP_CTRL_ROM_PATCH_READ_LOCK_REG_OFFSET 0xe0
#define OTP_CTRL_ROM_PATCH_READ_LOCK_REG_RESVAL 0x1u
#define OTP_CTRL_ROM_PATCH_READ_LOCK_ROM_PATCH_READ_LOCK_BIT 0
 
// Integrity digest for the VENDOR_TEST partition.
#define OTP_CTRL_VENDOR_TEST_DIGEST_VENDOR_TEST_DIGEST_FIELD_WIDTH 32
#define OTP_CTRL_VENDOR_TEST_DIGEST_MULTIREG_COUNT 2
 
// Integrity digest for the VENDOR_TEST partition.
#define OTP_CTRL_VENDOR_TEST_DIGEST_0_REG_OFFSET 0xe4
#define OTP_CTRL_VENDOR_TEST_DIGEST_0_REG_RESVAL 0x0u
 
// Integrity digest for the VENDOR_TEST partition.
#define OTP_CTRL_VENDOR_TEST_DIGEST_1_REG_OFFSET 0xe8
#define OTP_CTRL_VENDOR_TEST_DIGEST_1_REG_RESVAL 0x0u
 
// Integrity digest for the CREATOR_SW_CFG partition.
#define OTP_CTRL_CREATOR_SW_CFG_DIGEST_CREATOR_SW_CFG_DIGEST_FIELD_WIDTH 32
#define OTP_CTRL_CREATOR_SW_CFG_DIGEST_MULTIREG_COUNT 2
 
// Integrity digest for the CREATOR_SW_CFG partition.
#define OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_REG_OFFSET 0xec
#define OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_REG_RESVAL 0x0u
 
// Integrity digest for the CREATOR_SW_CFG partition.
#define OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_REG_OFFSET 0xf0
#define OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_REG_RESVAL 0x0u
 
// Integrity digest for the OWNER_SW_CFG partition.
#define OTP_CTRL_OWNER_SW_CFG_DIGEST_OWNER_SW_CFG_DIGEST_FIELD_WIDTH 32
#define OTP_CTRL_OWNER_SW_CFG_DIGEST_MULTIREG_COUNT 2
 
// Integrity digest for the OWNER_SW_CFG partition.
#define OTP_CTRL_OWNER_SW_CFG_DIGEST_0_REG_OFFSET 0xf4
#define OTP_CTRL_OWNER_SW_CFG_DIGEST_0_REG_RESVAL 0x0u
 
// Integrity digest for the OWNER_SW_CFG partition.
#define OTP_CTRL_OWNER_SW_CFG_DIGEST_1_REG_OFFSET 0xf8
#define OTP_CTRL_OWNER_SW_CFG_DIGEST_1_REG_RESVAL 0x0u
 
// Integrity digest for the ROT_CREATOR_AUTH partition.
#define OTP_CTRL_ROT_CREATOR_AUTH_DIGEST_ROT_CREATOR_AUTH_DIGEST_FIELD_WIDTH 32
#define OTP_CTRL_ROT_CREATOR_AUTH_DIGEST_MULTIREG_COUNT 2
 
// Integrity digest for the ROT_CREATOR_AUTH partition.
#define OTP_CTRL_ROT_CREATOR_AUTH_DIGEST_0_REG_OFFSET 0xfc
#define OTP_CTRL_ROT_CREATOR_AUTH_DIGEST_0_REG_RESVAL 0x0u
 
// Integrity digest for the ROT_CREATOR_AUTH partition.
#define OTP_CTRL_ROT_CREATOR_AUTH_DIGEST_1_REG_OFFSET 0x100
#define OTP_CTRL_ROT_CREATOR_AUTH_DIGEST_1_REG_RESVAL 0x0u
 
// Integrity digest for the ROT_OWNER_AUTH_SLOT0 partition.
#define OTP_CTRL_ROT_OWNER_AUTH_SLOT0_DIGEST_ROT_OWNER_AUTH_SLOT0_DIGEST_FIELD_WIDTH \
  32
#define OTP_CTRL_ROT_OWNER_AUTH_SLOT0_DIGEST_MULTIREG_COUNT 2
 
// Integrity digest for the ROT_OWNER_AUTH_SLOT0 partition.
#define OTP_CTRL_ROT_OWNER_AUTH_SLOT0_DIGEST_0_REG_OFFSET 0x104
#define OTP_CTRL_ROT_OWNER_AUTH_SLOT0_DIGEST_0_REG_RESVAL 0x0u
 
// Integrity digest for the ROT_OWNER_AUTH_SLOT0 partition.
#define OTP_CTRL_ROT_OWNER_AUTH_SLOT0_DIGEST_1_REG_OFFSET 0x108
#define OTP_CTRL_ROT_OWNER_AUTH_SLOT0_DIGEST_1_REG_RESVAL 0x0u
 
// Integrity digest for the ROT_OWNER_AUTH_SLOT1 partition.
#define OTP_CTRL_ROT_OWNER_AUTH_SLOT1_DIGEST_ROT_OWNER_AUTH_SLOT1_DIGEST_FIELD_WIDTH \
  32
#define OTP_CTRL_ROT_OWNER_AUTH_SLOT1_DIGEST_MULTIREG_COUNT 2
 
// Integrity digest for the ROT_OWNER_AUTH_SLOT1 partition.
#define OTP_CTRL_ROT_OWNER_AUTH_SLOT1_DIGEST_0_REG_OFFSET 0x10c
#define OTP_CTRL_ROT_OWNER_AUTH_SLOT1_DIGEST_0_REG_RESVAL 0x0u
 
// Integrity digest for the ROT_OWNER_AUTH_SLOT1 partition.
#define OTP_CTRL_ROT_OWNER_AUTH_SLOT1_DIGEST_1_REG_OFFSET 0x110
#define OTP_CTRL_ROT_OWNER_AUTH_SLOT1_DIGEST_1_REG_RESVAL 0x0u
 
// Integrity digest for the PLAT_INTEG_AUTH_SLOT0 partition.
#define OTP_CTRL_PLAT_INTEG_AUTH_SLOT0_DIGEST_PLAT_INTEG_AUTH_SLOT0_DIGEST_FIELD_WIDTH \
  32
#define OTP_CTRL_PLAT_INTEG_AUTH_SLOT0_DIGEST_MULTIREG_COUNT 2
 
// Integrity digest for the PLAT_INTEG_AUTH_SLOT0 partition.
#define OTP_CTRL_PLAT_INTEG_AUTH_SLOT0_DIGEST_0_REG_OFFSET 0x114
#define OTP_CTRL_PLAT_INTEG_AUTH_SLOT0_DIGEST_0_REG_RESVAL 0x0u
 
// Integrity digest for the PLAT_INTEG_AUTH_SLOT0 partition.
#define OTP_CTRL_PLAT_INTEG_AUTH_SLOT0_DIGEST_1_REG_OFFSET 0x118
#define OTP_CTRL_PLAT_INTEG_AUTH_SLOT0_DIGEST_1_REG_RESVAL 0x0u
 
// Integrity digest for the PLAT_INTEG_AUTH_SLOT1 partition.
#define OTP_CTRL_PLAT_INTEG_AUTH_SLOT1_DIGEST_PLAT_INTEG_AUTH_SLOT1_DIGEST_FIELD_WIDTH \
  32
#define OTP_CTRL_PLAT_INTEG_AUTH_SLOT1_DIGEST_MULTIREG_COUNT 2
 
// Integrity digest for the PLAT_INTEG_AUTH_SLOT1 partition.
#define OTP_CTRL_PLAT_INTEG_AUTH_SLOT1_DIGEST_0_REG_OFFSET 0x11c
#define OTP_CTRL_PLAT_INTEG_AUTH_SLOT1_DIGEST_0_REG_RESVAL 0x0u
 
// Integrity digest for the PLAT_INTEG_AUTH_SLOT1 partition.
#define OTP_CTRL_PLAT_INTEG_AUTH_SLOT1_DIGEST_1_REG_OFFSET 0x120
#define OTP_CTRL_PLAT_INTEG_AUTH_SLOT1_DIGEST_1_REG_RESVAL 0x0u
 
// Integrity digest for the PLAT_OWNER_AUTH_SLOT0 partition.
#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT0_DIGEST_PLAT_OWNER_AUTH_SLOT0_DIGEST_FIELD_WIDTH \
  32
#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT0_DIGEST_MULTIREG_COUNT 2
 
// Integrity digest for the PLAT_OWNER_AUTH_SLOT0 partition.
#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT0_DIGEST_0_REG_OFFSET 0x124
#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT0_DIGEST_0_REG_RESVAL 0x0u
 
// Integrity digest for the PLAT_OWNER_AUTH_SLOT0 partition.
#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT0_DIGEST_1_REG_OFFSET 0x128
#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT0_DIGEST_1_REG_RESVAL 0x0u
 
// Integrity digest for the PLAT_OWNER_AUTH_SLOT1 partition.
#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT1_DIGEST_PLAT_OWNER_AUTH_SLOT1_DIGEST_FIELD_WIDTH \
  32
#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT1_DIGEST_MULTIREG_COUNT 2
 
// Integrity digest for the PLAT_OWNER_AUTH_SLOT1 partition.
#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT1_DIGEST_0_REG_OFFSET 0x12c
#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT1_DIGEST_0_REG_RESVAL 0x0u
 
// Integrity digest for the PLAT_OWNER_AUTH_SLOT1 partition.
#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT1_DIGEST_1_REG_OFFSET 0x130
#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT1_DIGEST_1_REG_RESVAL 0x0u
 
// Integrity digest for the PLAT_OWNER_AUTH_SLOT2 partition.
#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT2_DIGEST_PLAT_OWNER_AUTH_SLOT2_DIGEST_FIELD_WIDTH \
  32
#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT2_DIGEST_MULTIREG_COUNT 2
 
// Integrity digest for the PLAT_OWNER_AUTH_SLOT2 partition.
#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT2_DIGEST_0_REG_OFFSET 0x134
#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT2_DIGEST_0_REG_RESVAL 0x0u
 
// Integrity digest for the PLAT_OWNER_AUTH_SLOT2 partition.
#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT2_DIGEST_1_REG_OFFSET 0x138
#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT2_DIGEST_1_REG_RESVAL 0x0u
 
// Integrity digest for the PLAT_OWNER_AUTH_SLOT3 partition.
#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT3_DIGEST_PLAT_OWNER_AUTH_SLOT3_DIGEST_FIELD_WIDTH \
  32
#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT3_DIGEST_MULTIREG_COUNT 2
 
// Integrity digest for the PLAT_OWNER_AUTH_SLOT3 partition.
#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT3_DIGEST_0_REG_OFFSET 0x13c
#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT3_DIGEST_0_REG_RESVAL 0x0u
 
// Integrity digest for the PLAT_OWNER_AUTH_SLOT3 partition.
#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT3_DIGEST_1_REG_OFFSET 0x140
#define OTP_CTRL_PLAT_OWNER_AUTH_SLOT3_DIGEST_1_REG_RESVAL 0x0u
 
// Integrity digest for the ROM_PATCH partition.
#define OTP_CTRL_ROM_PATCH_DIGEST_ROM_PATCH_DIGEST_FIELD_WIDTH 32
#define OTP_CTRL_ROM_PATCH_DIGEST_MULTIREG_COUNT 2
 
// Integrity digest for the ROM_PATCH partition.
#define OTP_CTRL_ROM_PATCH_DIGEST_0_REG_OFFSET 0x144
#define OTP_CTRL_ROM_PATCH_DIGEST_0_REG_RESVAL 0x0u
 
// Integrity digest for the ROM_PATCH partition.
#define OTP_CTRL_ROM_PATCH_DIGEST_1_REG_OFFSET 0x148
#define OTP_CTRL_ROM_PATCH_DIGEST_1_REG_RESVAL 0x0u
 
// Integrity digest for the HW_CFG0 partition.
#define OTP_CTRL_HW_CFG0_DIGEST_HW_CFG0_DIGEST_FIELD_WIDTH 32
#define OTP_CTRL_HW_CFG0_DIGEST_MULTIREG_COUNT 2
 
// Integrity digest for the HW_CFG0 partition.
#define OTP_CTRL_HW_CFG0_DIGEST_0_REG_OFFSET 0x14c
#define OTP_CTRL_HW_CFG0_DIGEST_0_REG_RESVAL 0x0u
 
// Integrity digest for the HW_CFG0 partition.
#define OTP_CTRL_HW_CFG0_DIGEST_1_REG_OFFSET 0x150
#define OTP_CTRL_HW_CFG0_DIGEST_1_REG_RESVAL 0x0u
 
// Integrity digest for the HW_CFG1 partition.
#define OTP_CTRL_HW_CFG1_DIGEST_HW_CFG1_DIGEST_FIELD_WIDTH 32
#define OTP_CTRL_HW_CFG1_DIGEST_MULTIREG_COUNT 2
 
// Integrity digest for the HW_CFG1 partition.
#define OTP_CTRL_HW_CFG1_DIGEST_0_REG_OFFSET 0x154
#define OTP_CTRL_HW_CFG1_DIGEST_0_REG_RESVAL 0x0u
 
// Integrity digest for the HW_CFG1 partition.
#define OTP_CTRL_HW_CFG1_DIGEST_1_REG_OFFSET 0x158
#define OTP_CTRL_HW_CFG1_DIGEST_1_REG_RESVAL 0x0u
 
// Integrity digest for the SECRET0 partition.
#define OTP_CTRL_SECRET0_DIGEST_SECRET0_DIGEST_FIELD_WIDTH 32
#define OTP_CTRL_SECRET0_DIGEST_MULTIREG_COUNT 2
 
// Integrity digest for the SECRET0 partition.
#define OTP_CTRL_SECRET0_DIGEST_0_REG_OFFSET 0x15c
#define OTP_CTRL_SECRET0_DIGEST_0_REG_RESVAL 0x0u
 
// Integrity digest for the SECRET0 partition.
#define OTP_CTRL_SECRET0_DIGEST_1_REG_OFFSET 0x160
#define OTP_CTRL_SECRET0_DIGEST_1_REG_RESVAL 0x0u
 
// Integrity digest for the SECRET1 partition.
#define OTP_CTRL_SECRET1_DIGEST_SECRET1_DIGEST_FIELD_WIDTH 32
#define OTP_CTRL_SECRET1_DIGEST_MULTIREG_COUNT 2
 
// Integrity digest for the SECRET1 partition.
#define OTP_CTRL_SECRET1_DIGEST_0_REG_OFFSET 0x164
#define OTP_CTRL_SECRET1_DIGEST_0_REG_RESVAL 0x0u
 
// Integrity digest for the SECRET1 partition.
#define OTP_CTRL_SECRET1_DIGEST_1_REG_OFFSET 0x168
#define OTP_CTRL_SECRET1_DIGEST_1_REG_RESVAL 0x0u
 
// Integrity digest for the SECRET2 partition.
#define OTP_CTRL_SECRET2_DIGEST_SECRET2_DIGEST_FIELD_WIDTH 32
#define OTP_CTRL_SECRET2_DIGEST_MULTIREG_COUNT 2
 
// Integrity digest for the SECRET2 partition.
#define OTP_CTRL_SECRET2_DIGEST_0_REG_OFFSET 0x16c
#define OTP_CTRL_SECRET2_DIGEST_0_REG_RESVAL 0x0u
 
// Integrity digest for the SECRET2 partition.
#define OTP_CTRL_SECRET2_DIGEST_1_REG_OFFSET 0x170
#define OTP_CTRL_SECRET2_DIGEST_1_REG_RESVAL 0x0u
 
// Integrity digest for the SECRET3 partition.
#define OTP_CTRL_SECRET3_DIGEST_SECRET3_DIGEST_FIELD_WIDTH 32
#define OTP_CTRL_SECRET3_DIGEST_MULTIREG_COUNT 2
 
// Integrity digest for the SECRET3 partition.
#define OTP_CTRL_SECRET3_DIGEST_0_REG_OFFSET 0x174
#define OTP_CTRL_SECRET3_DIGEST_0_REG_RESVAL 0x0u
 
// Integrity digest for the SECRET3 partition.
#define OTP_CTRL_SECRET3_DIGEST_1_REG_OFFSET 0x178
#define OTP_CTRL_SECRET3_DIGEST_1_REG_RESVAL 0x0u
 
// Memory area: Any read to this window directly maps to the corresponding
// offset in the creator and owner software
#define OTP_CTRL_SW_CFG_WINDOW_REG_OFFSET 0x4000
#define OTP_CTRL_SW_CFG_WINDOW_SIZE_WORDS 4096
#define OTP_CTRL_SW_CFG_WINDOW_SIZE_BYTES 16384
#ifdef __cplusplus
}  // extern "C"
#endif
#endif  // _OTP_CTRL_REG_DEFS_
// End generated register defines for otp_ctrl