Software APIs
entropy_src_regs.h
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1/**
2 * @file
3 * @brief Generated register defines for entropy_src
4 */
5
6// Copyright information found in source file:
7// Copyright lowRISC contributors (OpenTitan project).
8
9// Licensing information found in source file:
10// Licensed under the Apache License, Version 2.0, see LICENSE for details.
11// SPDX-License-Identifier: Apache-2.0
12
13#ifndef _ENTROPY_SRC_REG_DEFS_
14#define _ENTROPY_SRC_REG_DEFS_
15
16#ifdef __cplusplus
17extern "C" {
18#endif
19// Number of 32-bit entries in the observe FIFO.
20#define ENTROPY_SRC_PARAM_OBSERVE_FIFO_DEPTH 32
21
22// Number of alerts
23#define ENTROPY_SRC_PARAM_NUM_ALERTS 2
24
25// Register width
26#define ENTROPY_SRC_PARAM_REG_WIDTH 32
27
28// Common Interrupt Offsets
29#define ENTROPY_SRC_INTR_COMMON_ES_ENTROPY_VALID_BIT 0
30#define ENTROPY_SRC_INTR_COMMON_ES_HEALTH_TEST_FAILED_BIT 1
31#define ENTROPY_SRC_INTR_COMMON_ES_OBSERVE_FIFO_READY_BIT 2
32#define ENTROPY_SRC_INTR_COMMON_ES_FATAL_ERR_BIT 3
33
34// Interrupt State Register
35#define ENTROPY_SRC_INTR_STATE_REG_OFFSET 0x0
36#define ENTROPY_SRC_INTR_STATE_REG_RESVAL 0x0u
37#define ENTROPY_SRC_INTR_STATE_ES_ENTROPY_VALID_BIT 0
38#define ENTROPY_SRC_INTR_STATE_ES_HEALTH_TEST_FAILED_BIT 1
39#define ENTROPY_SRC_INTR_STATE_ES_OBSERVE_FIFO_READY_BIT 2
40#define ENTROPY_SRC_INTR_STATE_ES_FATAL_ERR_BIT 3
41
42// Interrupt Enable Register
43#define ENTROPY_SRC_INTR_ENABLE_REG_OFFSET 0x4
44#define ENTROPY_SRC_INTR_ENABLE_REG_RESVAL 0x0u
45#define ENTROPY_SRC_INTR_ENABLE_ES_ENTROPY_VALID_BIT 0
46#define ENTROPY_SRC_INTR_ENABLE_ES_HEALTH_TEST_FAILED_BIT 1
47#define ENTROPY_SRC_INTR_ENABLE_ES_OBSERVE_FIFO_READY_BIT 2
48#define ENTROPY_SRC_INTR_ENABLE_ES_FATAL_ERR_BIT 3
49
50// Interrupt Test Register
51#define ENTROPY_SRC_INTR_TEST_REG_OFFSET 0x8
52#define ENTROPY_SRC_INTR_TEST_REG_RESVAL 0x0u
53#define ENTROPY_SRC_INTR_TEST_ES_ENTROPY_VALID_BIT 0
54#define ENTROPY_SRC_INTR_TEST_ES_HEALTH_TEST_FAILED_BIT 1
55#define ENTROPY_SRC_INTR_TEST_ES_OBSERVE_FIFO_READY_BIT 2
56#define ENTROPY_SRC_INTR_TEST_ES_FATAL_ERR_BIT 3
57
58// Alert Test Register
59#define ENTROPY_SRC_ALERT_TEST_REG_OFFSET 0xc
60#define ENTROPY_SRC_ALERT_TEST_REG_RESVAL 0x0u
61#define ENTROPY_SRC_ALERT_TEST_RECOV_ALERT_BIT 0
62#define ENTROPY_SRC_ALERT_TEST_FATAL_ALERT_BIT 1
63
64// Register write enable for module enable register
65#define ENTROPY_SRC_ME_REGWEN_REG_OFFSET 0x10
66#define ENTROPY_SRC_ME_REGWEN_REG_RESVAL 0x1u
67#define ENTROPY_SRC_ME_REGWEN_ME_REGWEN_BIT 0
68
69// Register write enable for control and threshold registers
70#define ENTROPY_SRC_SW_REGUPD_REG_OFFSET 0x14
71#define ENTROPY_SRC_SW_REGUPD_REG_RESVAL 0x1u
72#define ENTROPY_SRC_SW_REGUPD_SW_REGUPD_BIT 0
73
74// Register write enable for all control registers
75#define ENTROPY_SRC_REGWEN_REG_OFFSET 0x18
76#define ENTROPY_SRC_REGWEN_REG_RESVAL 0x1u
77#define ENTROPY_SRC_REGWEN_REGWEN_BIT 0
78
79// Module enable register
80#define ENTROPY_SRC_MODULE_ENABLE_REG_OFFSET 0x1c
81#define ENTROPY_SRC_MODULE_ENABLE_REG_RESVAL 0x9u
82#define ENTROPY_SRC_MODULE_ENABLE_MODULE_ENABLE_MASK 0xfu
83#define ENTROPY_SRC_MODULE_ENABLE_MODULE_ENABLE_OFFSET 0
84#define ENTROPY_SRC_MODULE_ENABLE_MODULE_ENABLE_FIELD \
85 ((bitfield_field32_t) { .mask = ENTROPY_SRC_MODULE_ENABLE_MODULE_ENABLE_MASK, .index = ENTROPY_SRC_MODULE_ENABLE_MODULE_ENABLE_OFFSET })
86
87// Configuration register
88#define ENTROPY_SRC_CONF_REG_OFFSET 0x20
89#define ENTROPY_SRC_CONF_REG_RESVAL 0x999999u
90#define ENTROPY_SRC_CONF_FIPS_ENABLE_MASK 0xfu
91#define ENTROPY_SRC_CONF_FIPS_ENABLE_OFFSET 0
92#define ENTROPY_SRC_CONF_FIPS_ENABLE_FIELD \
93 ((bitfield_field32_t) { .mask = ENTROPY_SRC_CONF_FIPS_ENABLE_MASK, .index = ENTROPY_SRC_CONF_FIPS_ENABLE_OFFSET })
94#define ENTROPY_SRC_CONF_FIPS_FLAG_MASK 0xfu
95#define ENTROPY_SRC_CONF_FIPS_FLAG_OFFSET 4
96#define ENTROPY_SRC_CONF_FIPS_FLAG_FIELD \
97 ((bitfield_field32_t) { .mask = ENTROPY_SRC_CONF_FIPS_FLAG_MASK, .index = ENTROPY_SRC_CONF_FIPS_FLAG_OFFSET })
98#define ENTROPY_SRC_CONF_RNG_FIPS_MASK 0xfu
99#define ENTROPY_SRC_CONF_RNG_FIPS_OFFSET 8
100#define ENTROPY_SRC_CONF_RNG_FIPS_FIELD \
101 ((bitfield_field32_t) { .mask = ENTROPY_SRC_CONF_RNG_FIPS_MASK, .index = ENTROPY_SRC_CONF_RNG_FIPS_OFFSET })
102#define ENTROPY_SRC_CONF_RNG_BIT_ENABLE_MASK 0xfu
103#define ENTROPY_SRC_CONF_RNG_BIT_ENABLE_OFFSET 12
104#define ENTROPY_SRC_CONF_RNG_BIT_ENABLE_FIELD \
105 ((bitfield_field32_t) { .mask = ENTROPY_SRC_CONF_RNG_BIT_ENABLE_MASK, .index = ENTROPY_SRC_CONF_RNG_BIT_ENABLE_OFFSET })
106#define ENTROPY_SRC_CONF_THRESHOLD_SCOPE_MASK 0xfu
107#define ENTROPY_SRC_CONF_THRESHOLD_SCOPE_OFFSET 16
108#define ENTROPY_SRC_CONF_THRESHOLD_SCOPE_FIELD \
109 ((bitfield_field32_t) { .mask = ENTROPY_SRC_CONF_THRESHOLD_SCOPE_MASK, .index = ENTROPY_SRC_CONF_THRESHOLD_SCOPE_OFFSET })
110#define ENTROPY_SRC_CONF_ENTROPY_DATA_REG_ENABLE_MASK 0xfu
111#define ENTROPY_SRC_CONF_ENTROPY_DATA_REG_ENABLE_OFFSET 20
112#define ENTROPY_SRC_CONF_ENTROPY_DATA_REG_ENABLE_FIELD \
113 ((bitfield_field32_t) { .mask = ENTROPY_SRC_CONF_ENTROPY_DATA_REG_ENABLE_MASK, .index = ENTROPY_SRC_CONF_ENTROPY_DATA_REG_ENABLE_OFFSET })
114#define ENTROPY_SRC_CONF_RNG_BIT_SEL_MASK 0xffu
115#define ENTROPY_SRC_CONF_RNG_BIT_SEL_OFFSET 24
116#define ENTROPY_SRC_CONF_RNG_BIT_SEL_FIELD \
117 ((bitfield_field32_t) { .mask = ENTROPY_SRC_CONF_RNG_BIT_SEL_MASK, .index = ENTROPY_SRC_CONF_RNG_BIT_SEL_OFFSET })
118
119// Entropy control register
120#define ENTROPY_SRC_ENTROPY_CONTROL_REG_OFFSET 0x24
121#define ENTROPY_SRC_ENTROPY_CONTROL_REG_RESVAL 0x99u
122#define ENTROPY_SRC_ENTROPY_CONTROL_ES_ROUTE_MASK 0xfu
123#define ENTROPY_SRC_ENTROPY_CONTROL_ES_ROUTE_OFFSET 0
124#define ENTROPY_SRC_ENTROPY_CONTROL_ES_ROUTE_FIELD \
125 ((bitfield_field32_t) { .mask = ENTROPY_SRC_ENTROPY_CONTROL_ES_ROUTE_MASK, .index = ENTROPY_SRC_ENTROPY_CONTROL_ES_ROUTE_OFFSET })
126#define ENTROPY_SRC_ENTROPY_CONTROL_ES_TYPE_MASK 0xfu
127#define ENTROPY_SRC_ENTROPY_CONTROL_ES_TYPE_OFFSET 4
128#define ENTROPY_SRC_ENTROPY_CONTROL_ES_TYPE_FIELD \
129 ((bitfield_field32_t) { .mask = ENTROPY_SRC_ENTROPY_CONTROL_ES_TYPE_MASK, .index = ENTROPY_SRC_ENTROPY_CONTROL_ES_TYPE_OFFSET })
130
131// Entropy data bits
132#define ENTROPY_SRC_ENTROPY_DATA_REG_OFFSET 0x28
133#define ENTROPY_SRC_ENTROPY_DATA_REG_RESVAL 0x0u
134
135// Health test windows register
136#define ENTROPY_SRC_HEALTH_TEST_WINDOWS_REG_OFFSET 0x2c
137#define ENTROPY_SRC_HEALTH_TEST_WINDOWS_REG_RESVAL 0x1800200u
138#define ENTROPY_SRC_HEALTH_TEST_WINDOWS_FIPS_WINDOW_MASK 0xffffu
139#define ENTROPY_SRC_HEALTH_TEST_WINDOWS_FIPS_WINDOW_OFFSET 0
140#define ENTROPY_SRC_HEALTH_TEST_WINDOWS_FIPS_WINDOW_FIELD \
141 ((bitfield_field32_t) { .mask = ENTROPY_SRC_HEALTH_TEST_WINDOWS_FIPS_WINDOW_MASK, .index = ENTROPY_SRC_HEALTH_TEST_WINDOWS_FIPS_WINDOW_OFFSET })
142#define ENTROPY_SRC_HEALTH_TEST_WINDOWS_BYPASS_WINDOW_MASK 0xffffu
143#define ENTROPY_SRC_HEALTH_TEST_WINDOWS_BYPASS_WINDOW_OFFSET 16
144#define ENTROPY_SRC_HEALTH_TEST_WINDOWS_BYPASS_WINDOW_FIELD \
145 ((bitfield_field32_t) { .mask = ENTROPY_SRC_HEALTH_TEST_WINDOWS_BYPASS_WINDOW_MASK, .index = ENTROPY_SRC_HEALTH_TEST_WINDOWS_BYPASS_WINDOW_OFFSET })
146
147// Repetition count test thresholds register
148#define ENTROPY_SRC_REPCNT_THRESHOLDS_REG_OFFSET 0x30
149#define ENTROPY_SRC_REPCNT_THRESHOLDS_REG_RESVAL 0xffffffffu
150#define ENTROPY_SRC_REPCNT_THRESHOLDS_FIPS_THRESH_MASK 0xffffu
151#define ENTROPY_SRC_REPCNT_THRESHOLDS_FIPS_THRESH_OFFSET 0
152#define ENTROPY_SRC_REPCNT_THRESHOLDS_FIPS_THRESH_FIELD \
153 ((bitfield_field32_t) { .mask = ENTROPY_SRC_REPCNT_THRESHOLDS_FIPS_THRESH_MASK, .index = ENTROPY_SRC_REPCNT_THRESHOLDS_FIPS_THRESH_OFFSET })
154#define ENTROPY_SRC_REPCNT_THRESHOLDS_BYPASS_THRESH_MASK 0xffffu
155#define ENTROPY_SRC_REPCNT_THRESHOLDS_BYPASS_THRESH_OFFSET 16
156#define ENTROPY_SRC_REPCNT_THRESHOLDS_BYPASS_THRESH_FIELD \
157 ((bitfield_field32_t) { .mask = ENTROPY_SRC_REPCNT_THRESHOLDS_BYPASS_THRESH_MASK, .index = ENTROPY_SRC_REPCNT_THRESHOLDS_BYPASS_THRESH_OFFSET })
158
159// Repetition count symbol test thresholds register
160#define ENTROPY_SRC_REPCNTS_THRESHOLDS_REG_OFFSET 0x34
161#define ENTROPY_SRC_REPCNTS_THRESHOLDS_REG_RESVAL 0xffffffffu
162#define ENTROPY_SRC_REPCNTS_THRESHOLDS_FIPS_THRESH_MASK 0xffffu
163#define ENTROPY_SRC_REPCNTS_THRESHOLDS_FIPS_THRESH_OFFSET 0
164#define ENTROPY_SRC_REPCNTS_THRESHOLDS_FIPS_THRESH_FIELD \
165 ((bitfield_field32_t) { .mask = ENTROPY_SRC_REPCNTS_THRESHOLDS_FIPS_THRESH_MASK, .index = ENTROPY_SRC_REPCNTS_THRESHOLDS_FIPS_THRESH_OFFSET })
166#define ENTROPY_SRC_REPCNTS_THRESHOLDS_BYPASS_THRESH_MASK 0xffffu
167#define ENTROPY_SRC_REPCNTS_THRESHOLDS_BYPASS_THRESH_OFFSET 16
168#define ENTROPY_SRC_REPCNTS_THRESHOLDS_BYPASS_THRESH_FIELD \
169 ((bitfield_field32_t) { .mask = ENTROPY_SRC_REPCNTS_THRESHOLDS_BYPASS_THRESH_MASK, .index = ENTROPY_SRC_REPCNTS_THRESHOLDS_BYPASS_THRESH_OFFSET })
170
171// Adaptive proportion test high thresholds register
172#define ENTROPY_SRC_ADAPTP_HI_THRESHOLDS_REG_OFFSET 0x38
173#define ENTROPY_SRC_ADAPTP_HI_THRESHOLDS_REG_RESVAL 0xffffffffu
174#define ENTROPY_SRC_ADAPTP_HI_THRESHOLDS_FIPS_THRESH_MASK 0xffffu
175#define ENTROPY_SRC_ADAPTP_HI_THRESHOLDS_FIPS_THRESH_OFFSET 0
176#define ENTROPY_SRC_ADAPTP_HI_THRESHOLDS_FIPS_THRESH_FIELD \
177 ((bitfield_field32_t) { .mask = ENTROPY_SRC_ADAPTP_HI_THRESHOLDS_FIPS_THRESH_MASK, .index = ENTROPY_SRC_ADAPTP_HI_THRESHOLDS_FIPS_THRESH_OFFSET })
178#define ENTROPY_SRC_ADAPTP_HI_THRESHOLDS_BYPASS_THRESH_MASK 0xffffu
179#define ENTROPY_SRC_ADAPTP_HI_THRESHOLDS_BYPASS_THRESH_OFFSET 16
180#define ENTROPY_SRC_ADAPTP_HI_THRESHOLDS_BYPASS_THRESH_FIELD \
181 ((bitfield_field32_t) { .mask = ENTROPY_SRC_ADAPTP_HI_THRESHOLDS_BYPASS_THRESH_MASK, .index = ENTROPY_SRC_ADAPTP_HI_THRESHOLDS_BYPASS_THRESH_OFFSET })
182
183// Adaptive proportion test low thresholds register
184#define ENTROPY_SRC_ADAPTP_LO_THRESHOLDS_REG_OFFSET 0x3c
185#define ENTROPY_SRC_ADAPTP_LO_THRESHOLDS_REG_RESVAL 0x0u
186#define ENTROPY_SRC_ADAPTP_LO_THRESHOLDS_FIPS_THRESH_MASK 0xffffu
187#define ENTROPY_SRC_ADAPTP_LO_THRESHOLDS_FIPS_THRESH_OFFSET 0
188#define ENTROPY_SRC_ADAPTP_LO_THRESHOLDS_FIPS_THRESH_FIELD \
189 ((bitfield_field32_t) { .mask = ENTROPY_SRC_ADAPTP_LO_THRESHOLDS_FIPS_THRESH_MASK, .index = ENTROPY_SRC_ADAPTP_LO_THRESHOLDS_FIPS_THRESH_OFFSET })
190#define ENTROPY_SRC_ADAPTP_LO_THRESHOLDS_BYPASS_THRESH_MASK 0xffffu
191#define ENTROPY_SRC_ADAPTP_LO_THRESHOLDS_BYPASS_THRESH_OFFSET 16
192#define ENTROPY_SRC_ADAPTP_LO_THRESHOLDS_BYPASS_THRESH_FIELD \
193 ((bitfield_field32_t) { .mask = ENTROPY_SRC_ADAPTP_LO_THRESHOLDS_BYPASS_THRESH_MASK, .index = ENTROPY_SRC_ADAPTP_LO_THRESHOLDS_BYPASS_THRESH_OFFSET })
194
195// Bucket test thresholds register
196#define ENTROPY_SRC_BUCKET_THRESHOLDS_REG_OFFSET 0x40
197#define ENTROPY_SRC_BUCKET_THRESHOLDS_REG_RESVAL 0xffffffffu
198#define ENTROPY_SRC_BUCKET_THRESHOLDS_FIPS_THRESH_MASK 0xffffu
199#define ENTROPY_SRC_BUCKET_THRESHOLDS_FIPS_THRESH_OFFSET 0
200#define ENTROPY_SRC_BUCKET_THRESHOLDS_FIPS_THRESH_FIELD \
201 ((bitfield_field32_t) { .mask = ENTROPY_SRC_BUCKET_THRESHOLDS_FIPS_THRESH_MASK, .index = ENTROPY_SRC_BUCKET_THRESHOLDS_FIPS_THRESH_OFFSET })
202#define ENTROPY_SRC_BUCKET_THRESHOLDS_BYPASS_THRESH_MASK 0xffffu
203#define ENTROPY_SRC_BUCKET_THRESHOLDS_BYPASS_THRESH_OFFSET 16
204#define ENTROPY_SRC_BUCKET_THRESHOLDS_BYPASS_THRESH_FIELD \
205 ((bitfield_field32_t) { .mask = ENTROPY_SRC_BUCKET_THRESHOLDS_BYPASS_THRESH_MASK, .index = ENTROPY_SRC_BUCKET_THRESHOLDS_BYPASS_THRESH_OFFSET })
206
207// Markov test high thresholds register
208#define ENTROPY_SRC_MARKOV_HI_THRESHOLDS_REG_OFFSET 0x44
209#define ENTROPY_SRC_MARKOV_HI_THRESHOLDS_REG_RESVAL 0xffffffffu
210#define ENTROPY_SRC_MARKOV_HI_THRESHOLDS_FIPS_THRESH_MASK 0xffffu
211#define ENTROPY_SRC_MARKOV_HI_THRESHOLDS_FIPS_THRESH_OFFSET 0
212#define ENTROPY_SRC_MARKOV_HI_THRESHOLDS_FIPS_THRESH_FIELD \
213 ((bitfield_field32_t) { .mask = ENTROPY_SRC_MARKOV_HI_THRESHOLDS_FIPS_THRESH_MASK, .index = ENTROPY_SRC_MARKOV_HI_THRESHOLDS_FIPS_THRESH_OFFSET })
214#define ENTROPY_SRC_MARKOV_HI_THRESHOLDS_BYPASS_THRESH_MASK 0xffffu
215#define ENTROPY_SRC_MARKOV_HI_THRESHOLDS_BYPASS_THRESH_OFFSET 16
216#define ENTROPY_SRC_MARKOV_HI_THRESHOLDS_BYPASS_THRESH_FIELD \
217 ((bitfield_field32_t) { .mask = ENTROPY_SRC_MARKOV_HI_THRESHOLDS_BYPASS_THRESH_MASK, .index = ENTROPY_SRC_MARKOV_HI_THRESHOLDS_BYPASS_THRESH_OFFSET })
218
219// Markov test low thresholds register
220#define ENTROPY_SRC_MARKOV_LO_THRESHOLDS_REG_OFFSET 0x48
221#define ENTROPY_SRC_MARKOV_LO_THRESHOLDS_REG_RESVAL 0x0u
222#define ENTROPY_SRC_MARKOV_LO_THRESHOLDS_FIPS_THRESH_MASK 0xffffu
223#define ENTROPY_SRC_MARKOV_LO_THRESHOLDS_FIPS_THRESH_OFFSET 0
224#define ENTROPY_SRC_MARKOV_LO_THRESHOLDS_FIPS_THRESH_FIELD \
225 ((bitfield_field32_t) { .mask = ENTROPY_SRC_MARKOV_LO_THRESHOLDS_FIPS_THRESH_MASK, .index = ENTROPY_SRC_MARKOV_LO_THRESHOLDS_FIPS_THRESH_OFFSET })
226#define ENTROPY_SRC_MARKOV_LO_THRESHOLDS_BYPASS_THRESH_MASK 0xffffu
227#define ENTROPY_SRC_MARKOV_LO_THRESHOLDS_BYPASS_THRESH_OFFSET 16
228#define ENTROPY_SRC_MARKOV_LO_THRESHOLDS_BYPASS_THRESH_FIELD \
229 ((bitfield_field32_t) { .mask = ENTROPY_SRC_MARKOV_LO_THRESHOLDS_BYPASS_THRESH_MASK, .index = ENTROPY_SRC_MARKOV_LO_THRESHOLDS_BYPASS_THRESH_OFFSET })
230
231// External health test high thresholds register
232#define ENTROPY_SRC_EXTHT_HI_THRESHOLDS_REG_OFFSET 0x4c
233#define ENTROPY_SRC_EXTHT_HI_THRESHOLDS_REG_RESVAL 0xffffffffu
234#define ENTROPY_SRC_EXTHT_HI_THRESHOLDS_FIPS_THRESH_MASK 0xffffu
235#define ENTROPY_SRC_EXTHT_HI_THRESHOLDS_FIPS_THRESH_OFFSET 0
236#define ENTROPY_SRC_EXTHT_HI_THRESHOLDS_FIPS_THRESH_FIELD \
237 ((bitfield_field32_t) { .mask = ENTROPY_SRC_EXTHT_HI_THRESHOLDS_FIPS_THRESH_MASK, .index = ENTROPY_SRC_EXTHT_HI_THRESHOLDS_FIPS_THRESH_OFFSET })
238#define ENTROPY_SRC_EXTHT_HI_THRESHOLDS_BYPASS_THRESH_MASK 0xffffu
239#define ENTROPY_SRC_EXTHT_HI_THRESHOLDS_BYPASS_THRESH_OFFSET 16
240#define ENTROPY_SRC_EXTHT_HI_THRESHOLDS_BYPASS_THRESH_FIELD \
241 ((bitfield_field32_t) { .mask = ENTROPY_SRC_EXTHT_HI_THRESHOLDS_BYPASS_THRESH_MASK, .index = ENTROPY_SRC_EXTHT_HI_THRESHOLDS_BYPASS_THRESH_OFFSET })
242
243// External health test low thresholds register
244#define ENTROPY_SRC_EXTHT_LO_THRESHOLDS_REG_OFFSET 0x50
245#define ENTROPY_SRC_EXTHT_LO_THRESHOLDS_REG_RESVAL 0x0u
246#define ENTROPY_SRC_EXTHT_LO_THRESHOLDS_FIPS_THRESH_MASK 0xffffu
247#define ENTROPY_SRC_EXTHT_LO_THRESHOLDS_FIPS_THRESH_OFFSET 0
248#define ENTROPY_SRC_EXTHT_LO_THRESHOLDS_FIPS_THRESH_FIELD \
249 ((bitfield_field32_t) { .mask = ENTROPY_SRC_EXTHT_LO_THRESHOLDS_FIPS_THRESH_MASK, .index = ENTROPY_SRC_EXTHT_LO_THRESHOLDS_FIPS_THRESH_OFFSET })
250#define ENTROPY_SRC_EXTHT_LO_THRESHOLDS_BYPASS_THRESH_MASK 0xffffu
251#define ENTROPY_SRC_EXTHT_LO_THRESHOLDS_BYPASS_THRESH_OFFSET 16
252#define ENTROPY_SRC_EXTHT_LO_THRESHOLDS_BYPASS_THRESH_FIELD \
253 ((bitfield_field32_t) { .mask = ENTROPY_SRC_EXTHT_LO_THRESHOLDS_BYPASS_THRESH_MASK, .index = ENTROPY_SRC_EXTHT_LO_THRESHOLDS_BYPASS_THRESH_OFFSET })
254
255// Repetition count test high watermarks register
256#define ENTROPY_SRC_REPCNT_HI_WATERMARKS_REG_OFFSET 0x54
257#define ENTROPY_SRC_REPCNT_HI_WATERMARKS_REG_RESVAL 0x0u
258#define ENTROPY_SRC_REPCNT_HI_WATERMARKS_FIPS_WATERMARK_MASK 0xffffu
259#define ENTROPY_SRC_REPCNT_HI_WATERMARKS_FIPS_WATERMARK_OFFSET 0
260#define ENTROPY_SRC_REPCNT_HI_WATERMARKS_FIPS_WATERMARK_FIELD \
261 ((bitfield_field32_t) { .mask = ENTROPY_SRC_REPCNT_HI_WATERMARKS_FIPS_WATERMARK_MASK, .index = ENTROPY_SRC_REPCNT_HI_WATERMARKS_FIPS_WATERMARK_OFFSET })
262#define ENTROPY_SRC_REPCNT_HI_WATERMARKS_BYPASS_WATERMARK_MASK 0xffffu
263#define ENTROPY_SRC_REPCNT_HI_WATERMARKS_BYPASS_WATERMARK_OFFSET 16
264#define ENTROPY_SRC_REPCNT_HI_WATERMARKS_BYPASS_WATERMARK_FIELD \
265 ((bitfield_field32_t) { .mask = ENTROPY_SRC_REPCNT_HI_WATERMARKS_BYPASS_WATERMARK_MASK, .index = ENTROPY_SRC_REPCNT_HI_WATERMARKS_BYPASS_WATERMARK_OFFSET })
266
267// Repetition count symbol test high watermarks register
268#define ENTROPY_SRC_REPCNTS_HI_WATERMARKS_REG_OFFSET 0x58
269#define ENTROPY_SRC_REPCNTS_HI_WATERMARKS_REG_RESVAL 0x0u
270#define ENTROPY_SRC_REPCNTS_HI_WATERMARKS_FIPS_WATERMARK_MASK 0xffffu
271#define ENTROPY_SRC_REPCNTS_HI_WATERMARKS_FIPS_WATERMARK_OFFSET 0
272#define ENTROPY_SRC_REPCNTS_HI_WATERMARKS_FIPS_WATERMARK_FIELD \
273 ((bitfield_field32_t) { .mask = ENTROPY_SRC_REPCNTS_HI_WATERMARKS_FIPS_WATERMARK_MASK, .index = ENTROPY_SRC_REPCNTS_HI_WATERMARKS_FIPS_WATERMARK_OFFSET })
274#define ENTROPY_SRC_REPCNTS_HI_WATERMARKS_BYPASS_WATERMARK_MASK 0xffffu
275#define ENTROPY_SRC_REPCNTS_HI_WATERMARKS_BYPASS_WATERMARK_OFFSET 16
276#define ENTROPY_SRC_REPCNTS_HI_WATERMARKS_BYPASS_WATERMARK_FIELD \
277 ((bitfield_field32_t) { .mask = ENTROPY_SRC_REPCNTS_HI_WATERMARKS_BYPASS_WATERMARK_MASK, .index = ENTROPY_SRC_REPCNTS_HI_WATERMARKS_BYPASS_WATERMARK_OFFSET })
278
279// Adaptive proportion test high watermarks register
280#define ENTROPY_SRC_ADAPTP_HI_WATERMARKS_REG_OFFSET 0x5c
281#define ENTROPY_SRC_ADAPTP_HI_WATERMARKS_REG_RESVAL 0x0u
282#define ENTROPY_SRC_ADAPTP_HI_WATERMARKS_FIPS_WATERMARK_MASK 0xffffu
283#define ENTROPY_SRC_ADAPTP_HI_WATERMARKS_FIPS_WATERMARK_OFFSET 0
284#define ENTROPY_SRC_ADAPTP_HI_WATERMARKS_FIPS_WATERMARK_FIELD \
285 ((bitfield_field32_t) { .mask = ENTROPY_SRC_ADAPTP_HI_WATERMARKS_FIPS_WATERMARK_MASK, .index = ENTROPY_SRC_ADAPTP_HI_WATERMARKS_FIPS_WATERMARK_OFFSET })
286#define ENTROPY_SRC_ADAPTP_HI_WATERMARKS_BYPASS_WATERMARK_MASK 0xffffu
287#define ENTROPY_SRC_ADAPTP_HI_WATERMARKS_BYPASS_WATERMARK_OFFSET 16
288#define ENTROPY_SRC_ADAPTP_HI_WATERMARKS_BYPASS_WATERMARK_FIELD \
289 ((bitfield_field32_t) { .mask = ENTROPY_SRC_ADAPTP_HI_WATERMARKS_BYPASS_WATERMARK_MASK, .index = ENTROPY_SRC_ADAPTP_HI_WATERMARKS_BYPASS_WATERMARK_OFFSET })
290
291// Adaptive proportion test low watermarks register
292#define ENTROPY_SRC_ADAPTP_LO_WATERMARKS_REG_OFFSET 0x60
293#define ENTROPY_SRC_ADAPTP_LO_WATERMARKS_REG_RESVAL 0xffffffffu
294#define ENTROPY_SRC_ADAPTP_LO_WATERMARKS_FIPS_WATERMARK_MASK 0xffffu
295#define ENTROPY_SRC_ADAPTP_LO_WATERMARKS_FIPS_WATERMARK_OFFSET 0
296#define ENTROPY_SRC_ADAPTP_LO_WATERMARKS_FIPS_WATERMARK_FIELD \
297 ((bitfield_field32_t) { .mask = ENTROPY_SRC_ADAPTP_LO_WATERMARKS_FIPS_WATERMARK_MASK, .index = ENTROPY_SRC_ADAPTP_LO_WATERMARKS_FIPS_WATERMARK_OFFSET })
298#define ENTROPY_SRC_ADAPTP_LO_WATERMARKS_BYPASS_WATERMARK_MASK 0xffffu
299#define ENTROPY_SRC_ADAPTP_LO_WATERMARKS_BYPASS_WATERMARK_OFFSET 16
300#define ENTROPY_SRC_ADAPTP_LO_WATERMARKS_BYPASS_WATERMARK_FIELD \
301 ((bitfield_field32_t) { .mask = ENTROPY_SRC_ADAPTP_LO_WATERMARKS_BYPASS_WATERMARK_MASK, .index = ENTROPY_SRC_ADAPTP_LO_WATERMARKS_BYPASS_WATERMARK_OFFSET })
302
303// External health test high watermarks register
304#define ENTROPY_SRC_EXTHT_HI_WATERMARKS_REG_OFFSET 0x64
305#define ENTROPY_SRC_EXTHT_HI_WATERMARKS_REG_RESVAL 0x0u
306#define ENTROPY_SRC_EXTHT_HI_WATERMARKS_FIPS_WATERMARK_MASK 0xffffu
307#define ENTROPY_SRC_EXTHT_HI_WATERMARKS_FIPS_WATERMARK_OFFSET 0
308#define ENTROPY_SRC_EXTHT_HI_WATERMARKS_FIPS_WATERMARK_FIELD \
309 ((bitfield_field32_t) { .mask = ENTROPY_SRC_EXTHT_HI_WATERMARKS_FIPS_WATERMARK_MASK, .index = ENTROPY_SRC_EXTHT_HI_WATERMARKS_FIPS_WATERMARK_OFFSET })
310#define ENTROPY_SRC_EXTHT_HI_WATERMARKS_BYPASS_WATERMARK_MASK 0xffffu
311#define ENTROPY_SRC_EXTHT_HI_WATERMARKS_BYPASS_WATERMARK_OFFSET 16
312#define ENTROPY_SRC_EXTHT_HI_WATERMARKS_BYPASS_WATERMARK_FIELD \
313 ((bitfield_field32_t) { .mask = ENTROPY_SRC_EXTHT_HI_WATERMARKS_BYPASS_WATERMARK_MASK, .index = ENTROPY_SRC_EXTHT_HI_WATERMARKS_BYPASS_WATERMARK_OFFSET })
314
315// External health test low watermarks register
316#define ENTROPY_SRC_EXTHT_LO_WATERMARKS_REG_OFFSET 0x68
317#define ENTROPY_SRC_EXTHT_LO_WATERMARKS_REG_RESVAL 0xffffffffu
318#define ENTROPY_SRC_EXTHT_LO_WATERMARKS_FIPS_WATERMARK_MASK 0xffffu
319#define ENTROPY_SRC_EXTHT_LO_WATERMARKS_FIPS_WATERMARK_OFFSET 0
320#define ENTROPY_SRC_EXTHT_LO_WATERMARKS_FIPS_WATERMARK_FIELD \
321 ((bitfield_field32_t) { .mask = ENTROPY_SRC_EXTHT_LO_WATERMARKS_FIPS_WATERMARK_MASK, .index = ENTROPY_SRC_EXTHT_LO_WATERMARKS_FIPS_WATERMARK_OFFSET })
322#define ENTROPY_SRC_EXTHT_LO_WATERMARKS_BYPASS_WATERMARK_MASK 0xffffu
323#define ENTROPY_SRC_EXTHT_LO_WATERMARKS_BYPASS_WATERMARK_OFFSET 16
324#define ENTROPY_SRC_EXTHT_LO_WATERMARKS_BYPASS_WATERMARK_FIELD \
325 ((bitfield_field32_t) { .mask = ENTROPY_SRC_EXTHT_LO_WATERMARKS_BYPASS_WATERMARK_MASK, .index = ENTROPY_SRC_EXTHT_LO_WATERMARKS_BYPASS_WATERMARK_OFFSET })
326
327// Bucket test high watermarks register
328#define ENTROPY_SRC_BUCKET_HI_WATERMARKS_REG_OFFSET 0x6c
329#define ENTROPY_SRC_BUCKET_HI_WATERMARKS_REG_RESVAL 0x0u
330#define ENTROPY_SRC_BUCKET_HI_WATERMARKS_FIPS_WATERMARK_MASK 0xffffu
331#define ENTROPY_SRC_BUCKET_HI_WATERMARKS_FIPS_WATERMARK_OFFSET 0
332#define ENTROPY_SRC_BUCKET_HI_WATERMARKS_FIPS_WATERMARK_FIELD \
333 ((bitfield_field32_t) { .mask = ENTROPY_SRC_BUCKET_HI_WATERMARKS_FIPS_WATERMARK_MASK, .index = ENTROPY_SRC_BUCKET_HI_WATERMARKS_FIPS_WATERMARK_OFFSET })
334#define ENTROPY_SRC_BUCKET_HI_WATERMARKS_BYPASS_WATERMARK_MASK 0xffffu
335#define ENTROPY_SRC_BUCKET_HI_WATERMARKS_BYPASS_WATERMARK_OFFSET 16
336#define ENTROPY_SRC_BUCKET_HI_WATERMARKS_BYPASS_WATERMARK_FIELD \
337 ((bitfield_field32_t) { .mask = ENTROPY_SRC_BUCKET_HI_WATERMARKS_BYPASS_WATERMARK_MASK, .index = ENTROPY_SRC_BUCKET_HI_WATERMARKS_BYPASS_WATERMARK_OFFSET })
338
339// Markov test high watermarks register
340#define ENTROPY_SRC_MARKOV_HI_WATERMARKS_REG_OFFSET 0x70
341#define ENTROPY_SRC_MARKOV_HI_WATERMARKS_REG_RESVAL 0x0u
342#define ENTROPY_SRC_MARKOV_HI_WATERMARKS_FIPS_WATERMARK_MASK 0xffffu
343#define ENTROPY_SRC_MARKOV_HI_WATERMARKS_FIPS_WATERMARK_OFFSET 0
344#define ENTROPY_SRC_MARKOV_HI_WATERMARKS_FIPS_WATERMARK_FIELD \
345 ((bitfield_field32_t) { .mask = ENTROPY_SRC_MARKOV_HI_WATERMARKS_FIPS_WATERMARK_MASK, .index = ENTROPY_SRC_MARKOV_HI_WATERMARKS_FIPS_WATERMARK_OFFSET })
346#define ENTROPY_SRC_MARKOV_HI_WATERMARKS_BYPASS_WATERMARK_MASK 0xffffu
347#define ENTROPY_SRC_MARKOV_HI_WATERMARKS_BYPASS_WATERMARK_OFFSET 16
348#define ENTROPY_SRC_MARKOV_HI_WATERMARKS_BYPASS_WATERMARK_FIELD \
349 ((bitfield_field32_t) { .mask = ENTROPY_SRC_MARKOV_HI_WATERMARKS_BYPASS_WATERMARK_MASK, .index = ENTROPY_SRC_MARKOV_HI_WATERMARKS_BYPASS_WATERMARK_OFFSET })
350
351// Markov test low watermarks register
352#define ENTROPY_SRC_MARKOV_LO_WATERMARKS_REG_OFFSET 0x74
353#define ENTROPY_SRC_MARKOV_LO_WATERMARKS_REG_RESVAL 0xffffffffu
354#define ENTROPY_SRC_MARKOV_LO_WATERMARKS_FIPS_WATERMARK_MASK 0xffffu
355#define ENTROPY_SRC_MARKOV_LO_WATERMARKS_FIPS_WATERMARK_OFFSET 0
356#define ENTROPY_SRC_MARKOV_LO_WATERMARKS_FIPS_WATERMARK_FIELD \
357 ((bitfield_field32_t) { .mask = ENTROPY_SRC_MARKOV_LO_WATERMARKS_FIPS_WATERMARK_MASK, .index = ENTROPY_SRC_MARKOV_LO_WATERMARKS_FIPS_WATERMARK_OFFSET })
358#define ENTROPY_SRC_MARKOV_LO_WATERMARKS_BYPASS_WATERMARK_MASK 0xffffu
359#define ENTROPY_SRC_MARKOV_LO_WATERMARKS_BYPASS_WATERMARK_OFFSET 16
360#define ENTROPY_SRC_MARKOV_LO_WATERMARKS_BYPASS_WATERMARK_FIELD \
361 ((bitfield_field32_t) { .mask = ENTROPY_SRC_MARKOV_LO_WATERMARKS_BYPASS_WATERMARK_MASK, .index = ENTROPY_SRC_MARKOV_LO_WATERMARKS_BYPASS_WATERMARK_OFFSET })
362
363// Repetition count test failure counter register
364#define ENTROPY_SRC_REPCNT_TOTAL_FAILS_REG_OFFSET 0x78
365#define ENTROPY_SRC_REPCNT_TOTAL_FAILS_REG_RESVAL 0x0u
366
367// Repetition count symbol test failure counter register
368#define ENTROPY_SRC_REPCNTS_TOTAL_FAILS_REG_OFFSET 0x7c
369#define ENTROPY_SRC_REPCNTS_TOTAL_FAILS_REG_RESVAL 0x0u
370
371// Adaptive proportion high test failure counter register
372#define ENTROPY_SRC_ADAPTP_HI_TOTAL_FAILS_REG_OFFSET 0x80
373#define ENTROPY_SRC_ADAPTP_HI_TOTAL_FAILS_REG_RESVAL 0x0u
374
375// Adaptive proportion low test failure counter register
376#define ENTROPY_SRC_ADAPTP_LO_TOTAL_FAILS_REG_OFFSET 0x84
377#define ENTROPY_SRC_ADAPTP_LO_TOTAL_FAILS_REG_RESVAL 0x0u
378
379// Bucket test failure counter register
380#define ENTROPY_SRC_BUCKET_TOTAL_FAILS_REG_OFFSET 0x88
381#define ENTROPY_SRC_BUCKET_TOTAL_FAILS_REG_RESVAL 0x0u
382
383// Markov high test failure counter register
384#define ENTROPY_SRC_MARKOV_HI_TOTAL_FAILS_REG_OFFSET 0x8c
385#define ENTROPY_SRC_MARKOV_HI_TOTAL_FAILS_REG_RESVAL 0x0u
386
387// Markov low test failure counter register
388#define ENTROPY_SRC_MARKOV_LO_TOTAL_FAILS_REG_OFFSET 0x90
389#define ENTROPY_SRC_MARKOV_LO_TOTAL_FAILS_REG_RESVAL 0x0u
390
391// External health test high threshold failure counter register
392#define ENTROPY_SRC_EXTHT_HI_TOTAL_FAILS_REG_OFFSET 0x94
393#define ENTROPY_SRC_EXTHT_HI_TOTAL_FAILS_REG_RESVAL 0x0u
394
395// External health test low threshold failure counter register
396#define ENTROPY_SRC_EXTHT_LO_TOTAL_FAILS_REG_OFFSET 0x98
397#define ENTROPY_SRC_EXTHT_LO_TOTAL_FAILS_REG_RESVAL 0x0u
398
399// Alert threshold register
400#define ENTROPY_SRC_ALERT_THRESHOLD_REG_OFFSET 0x9c
401#define ENTROPY_SRC_ALERT_THRESHOLD_REG_RESVAL 0xfffd0002u
402#define ENTROPY_SRC_ALERT_THRESHOLD_ALERT_THRESHOLD_MASK 0xffffu
403#define ENTROPY_SRC_ALERT_THRESHOLD_ALERT_THRESHOLD_OFFSET 0
404#define ENTROPY_SRC_ALERT_THRESHOLD_ALERT_THRESHOLD_FIELD \
405 ((bitfield_field32_t) { .mask = ENTROPY_SRC_ALERT_THRESHOLD_ALERT_THRESHOLD_MASK, .index = ENTROPY_SRC_ALERT_THRESHOLD_ALERT_THRESHOLD_OFFSET })
406#define ENTROPY_SRC_ALERT_THRESHOLD_ALERT_THRESHOLD_INV_MASK 0xffffu
407#define ENTROPY_SRC_ALERT_THRESHOLD_ALERT_THRESHOLD_INV_OFFSET 16
408#define ENTROPY_SRC_ALERT_THRESHOLD_ALERT_THRESHOLD_INV_FIELD \
409 ((bitfield_field32_t) { .mask = ENTROPY_SRC_ALERT_THRESHOLD_ALERT_THRESHOLD_INV_MASK, .index = ENTROPY_SRC_ALERT_THRESHOLD_ALERT_THRESHOLD_INV_OFFSET })
410
411// Alert summary failure counts register
412#define ENTROPY_SRC_ALERT_SUMMARY_FAIL_COUNTS_REG_OFFSET 0xa0
413#define ENTROPY_SRC_ALERT_SUMMARY_FAIL_COUNTS_REG_RESVAL 0x0u
414#define ENTROPY_SRC_ALERT_SUMMARY_FAIL_COUNTS_ANY_FAIL_COUNT_MASK 0xffffu
415#define ENTROPY_SRC_ALERT_SUMMARY_FAIL_COUNTS_ANY_FAIL_COUNT_OFFSET 0
416#define ENTROPY_SRC_ALERT_SUMMARY_FAIL_COUNTS_ANY_FAIL_COUNT_FIELD \
417 ((bitfield_field32_t) { .mask = ENTROPY_SRC_ALERT_SUMMARY_FAIL_COUNTS_ANY_FAIL_COUNT_MASK, .index = ENTROPY_SRC_ALERT_SUMMARY_FAIL_COUNTS_ANY_FAIL_COUNT_OFFSET })
418
419// Alert failure counts register
420#define ENTROPY_SRC_ALERT_FAIL_COUNTS_REG_OFFSET 0xa4
421#define ENTROPY_SRC_ALERT_FAIL_COUNTS_REG_RESVAL 0x0u
422#define ENTROPY_SRC_ALERT_FAIL_COUNTS_REPCNT_FAIL_COUNT_MASK 0xfu
423#define ENTROPY_SRC_ALERT_FAIL_COUNTS_REPCNT_FAIL_COUNT_OFFSET 4
424#define ENTROPY_SRC_ALERT_FAIL_COUNTS_REPCNT_FAIL_COUNT_FIELD \
425 ((bitfield_field32_t) { .mask = ENTROPY_SRC_ALERT_FAIL_COUNTS_REPCNT_FAIL_COUNT_MASK, .index = ENTROPY_SRC_ALERT_FAIL_COUNTS_REPCNT_FAIL_COUNT_OFFSET })
426#define ENTROPY_SRC_ALERT_FAIL_COUNTS_ADAPTP_HI_FAIL_COUNT_MASK 0xfu
427#define ENTROPY_SRC_ALERT_FAIL_COUNTS_ADAPTP_HI_FAIL_COUNT_OFFSET 8
428#define ENTROPY_SRC_ALERT_FAIL_COUNTS_ADAPTP_HI_FAIL_COUNT_FIELD \
429 ((bitfield_field32_t) { .mask = ENTROPY_SRC_ALERT_FAIL_COUNTS_ADAPTP_HI_FAIL_COUNT_MASK, .index = ENTROPY_SRC_ALERT_FAIL_COUNTS_ADAPTP_HI_FAIL_COUNT_OFFSET })
430#define ENTROPY_SRC_ALERT_FAIL_COUNTS_ADAPTP_LO_FAIL_COUNT_MASK 0xfu
431#define ENTROPY_SRC_ALERT_FAIL_COUNTS_ADAPTP_LO_FAIL_COUNT_OFFSET 12
432#define ENTROPY_SRC_ALERT_FAIL_COUNTS_ADAPTP_LO_FAIL_COUNT_FIELD \
433 ((bitfield_field32_t) { .mask = ENTROPY_SRC_ALERT_FAIL_COUNTS_ADAPTP_LO_FAIL_COUNT_MASK, .index = ENTROPY_SRC_ALERT_FAIL_COUNTS_ADAPTP_LO_FAIL_COUNT_OFFSET })
434#define ENTROPY_SRC_ALERT_FAIL_COUNTS_BUCKET_FAIL_COUNT_MASK 0xfu
435#define ENTROPY_SRC_ALERT_FAIL_COUNTS_BUCKET_FAIL_COUNT_OFFSET 16
436#define ENTROPY_SRC_ALERT_FAIL_COUNTS_BUCKET_FAIL_COUNT_FIELD \
437 ((bitfield_field32_t) { .mask = ENTROPY_SRC_ALERT_FAIL_COUNTS_BUCKET_FAIL_COUNT_MASK, .index = ENTROPY_SRC_ALERT_FAIL_COUNTS_BUCKET_FAIL_COUNT_OFFSET })
438#define ENTROPY_SRC_ALERT_FAIL_COUNTS_MARKOV_HI_FAIL_COUNT_MASK 0xfu
439#define ENTROPY_SRC_ALERT_FAIL_COUNTS_MARKOV_HI_FAIL_COUNT_OFFSET 20
440#define ENTROPY_SRC_ALERT_FAIL_COUNTS_MARKOV_HI_FAIL_COUNT_FIELD \
441 ((bitfield_field32_t) { .mask = ENTROPY_SRC_ALERT_FAIL_COUNTS_MARKOV_HI_FAIL_COUNT_MASK, .index = ENTROPY_SRC_ALERT_FAIL_COUNTS_MARKOV_HI_FAIL_COUNT_OFFSET })
442#define ENTROPY_SRC_ALERT_FAIL_COUNTS_MARKOV_LO_FAIL_COUNT_MASK 0xfu
443#define ENTROPY_SRC_ALERT_FAIL_COUNTS_MARKOV_LO_FAIL_COUNT_OFFSET 24
444#define ENTROPY_SRC_ALERT_FAIL_COUNTS_MARKOV_LO_FAIL_COUNT_FIELD \
445 ((bitfield_field32_t) { .mask = ENTROPY_SRC_ALERT_FAIL_COUNTS_MARKOV_LO_FAIL_COUNT_MASK, .index = ENTROPY_SRC_ALERT_FAIL_COUNTS_MARKOV_LO_FAIL_COUNT_OFFSET })
446#define ENTROPY_SRC_ALERT_FAIL_COUNTS_REPCNTS_FAIL_COUNT_MASK 0xfu
447#define ENTROPY_SRC_ALERT_FAIL_COUNTS_REPCNTS_FAIL_COUNT_OFFSET 28
448#define ENTROPY_SRC_ALERT_FAIL_COUNTS_REPCNTS_FAIL_COUNT_FIELD \
449 ((bitfield_field32_t) { .mask = ENTROPY_SRC_ALERT_FAIL_COUNTS_REPCNTS_FAIL_COUNT_MASK, .index = ENTROPY_SRC_ALERT_FAIL_COUNTS_REPCNTS_FAIL_COUNT_OFFSET })
450
451// External health test alert failure counts register
452#define ENTROPY_SRC_EXTHT_FAIL_COUNTS_REG_OFFSET 0xa8
453#define ENTROPY_SRC_EXTHT_FAIL_COUNTS_REG_RESVAL 0x0u
454#define ENTROPY_SRC_EXTHT_FAIL_COUNTS_EXTHT_HI_FAIL_COUNT_MASK 0xfu
455#define ENTROPY_SRC_EXTHT_FAIL_COUNTS_EXTHT_HI_FAIL_COUNT_OFFSET 0
456#define ENTROPY_SRC_EXTHT_FAIL_COUNTS_EXTHT_HI_FAIL_COUNT_FIELD \
457 ((bitfield_field32_t) { .mask = ENTROPY_SRC_EXTHT_FAIL_COUNTS_EXTHT_HI_FAIL_COUNT_MASK, .index = ENTROPY_SRC_EXTHT_FAIL_COUNTS_EXTHT_HI_FAIL_COUNT_OFFSET })
458#define ENTROPY_SRC_EXTHT_FAIL_COUNTS_EXTHT_LO_FAIL_COUNT_MASK 0xfu
459#define ENTROPY_SRC_EXTHT_FAIL_COUNTS_EXTHT_LO_FAIL_COUNT_OFFSET 4
460#define ENTROPY_SRC_EXTHT_FAIL_COUNTS_EXTHT_LO_FAIL_COUNT_FIELD \
461 ((bitfield_field32_t) { .mask = ENTROPY_SRC_EXTHT_FAIL_COUNTS_EXTHT_LO_FAIL_COUNT_MASK, .index = ENTROPY_SRC_EXTHT_FAIL_COUNTS_EXTHT_LO_FAIL_COUNT_OFFSET })
462
463// Firmware override control register
464#define ENTROPY_SRC_FW_OV_CONTROL_REG_OFFSET 0xac
465#define ENTROPY_SRC_FW_OV_CONTROL_REG_RESVAL 0x99u
466#define ENTROPY_SRC_FW_OV_CONTROL_FW_OV_MODE_MASK 0xfu
467#define ENTROPY_SRC_FW_OV_CONTROL_FW_OV_MODE_OFFSET 0
468#define ENTROPY_SRC_FW_OV_CONTROL_FW_OV_MODE_FIELD \
469 ((bitfield_field32_t) { .mask = ENTROPY_SRC_FW_OV_CONTROL_FW_OV_MODE_MASK, .index = ENTROPY_SRC_FW_OV_CONTROL_FW_OV_MODE_OFFSET })
470#define ENTROPY_SRC_FW_OV_CONTROL_FW_OV_ENTROPY_INSERT_MASK 0xfu
471#define ENTROPY_SRC_FW_OV_CONTROL_FW_OV_ENTROPY_INSERT_OFFSET 4
472#define ENTROPY_SRC_FW_OV_CONTROL_FW_OV_ENTROPY_INSERT_FIELD \
473 ((bitfield_field32_t) { .mask = ENTROPY_SRC_FW_OV_CONTROL_FW_OV_ENTROPY_INSERT_MASK, .index = ENTROPY_SRC_FW_OV_CONTROL_FW_OV_ENTROPY_INSERT_OFFSET })
474
475// Firmware override sha3 block start control register
476#define ENTROPY_SRC_FW_OV_SHA3_START_REG_OFFSET 0xb0
477#define ENTROPY_SRC_FW_OV_SHA3_START_REG_RESVAL 0x9u
478#define ENTROPY_SRC_FW_OV_SHA3_START_FW_OV_INSERT_START_MASK 0xfu
479#define ENTROPY_SRC_FW_OV_SHA3_START_FW_OV_INSERT_START_OFFSET 0
480#define ENTROPY_SRC_FW_OV_SHA3_START_FW_OV_INSERT_START_FIELD \
481 ((bitfield_field32_t) { .mask = ENTROPY_SRC_FW_OV_SHA3_START_FW_OV_INSERT_START_MASK, .index = ENTROPY_SRC_FW_OV_SHA3_START_FW_OV_INSERT_START_OFFSET })
482
483// Firmware override FIFO write full status register
484#define ENTROPY_SRC_FW_OV_WR_FIFO_FULL_REG_OFFSET 0xb4
485#define ENTROPY_SRC_FW_OV_WR_FIFO_FULL_REG_RESVAL 0x0u
486#define ENTROPY_SRC_FW_OV_WR_FIFO_FULL_FW_OV_WR_FIFO_FULL_BIT 0
487
488// Firmware override observe FIFO overflow status
489#define ENTROPY_SRC_FW_OV_RD_FIFO_OVERFLOW_REG_OFFSET 0xb8
490#define ENTROPY_SRC_FW_OV_RD_FIFO_OVERFLOW_REG_RESVAL 0x0u
491#define ENTROPY_SRC_FW_OV_RD_FIFO_OVERFLOW_FW_OV_RD_FIFO_OVERFLOW_BIT 0
492
493// Firmware override observe FIFO read register
494#define ENTROPY_SRC_FW_OV_RD_DATA_REG_OFFSET 0xbc
495#define ENTROPY_SRC_FW_OV_RD_DATA_REG_RESVAL 0x0u
496
497// Firmware override FIFO write register
498#define ENTROPY_SRC_FW_OV_WR_DATA_REG_OFFSET 0xc0
499#define ENTROPY_SRC_FW_OV_WR_DATA_REG_RESVAL 0x0u
500
501// Observe FIFO threshold register
502#define ENTROPY_SRC_OBSERVE_FIFO_THRESH_REG_OFFSET 0xc4
503#define ENTROPY_SRC_OBSERVE_FIFO_THRESH_REG_RESVAL 0x10u
504#define ENTROPY_SRC_OBSERVE_FIFO_THRESH_OBSERVE_FIFO_THRESH_MASK 0x3fu
505#define ENTROPY_SRC_OBSERVE_FIFO_THRESH_OBSERVE_FIFO_THRESH_OFFSET 0
506#define ENTROPY_SRC_OBSERVE_FIFO_THRESH_OBSERVE_FIFO_THRESH_FIELD \
507 ((bitfield_field32_t) { .mask = ENTROPY_SRC_OBSERVE_FIFO_THRESH_OBSERVE_FIFO_THRESH_MASK, .index = ENTROPY_SRC_OBSERVE_FIFO_THRESH_OBSERVE_FIFO_THRESH_OFFSET })
508
509// Observe FIFO depth register
510#define ENTROPY_SRC_OBSERVE_FIFO_DEPTH_REG_OFFSET 0xc8
511#define ENTROPY_SRC_OBSERVE_FIFO_DEPTH_REG_RESVAL 0x0u
512#define ENTROPY_SRC_OBSERVE_FIFO_DEPTH_OBSERVE_FIFO_DEPTH_MASK 0x3fu
513#define ENTROPY_SRC_OBSERVE_FIFO_DEPTH_OBSERVE_FIFO_DEPTH_OFFSET 0
514#define ENTROPY_SRC_OBSERVE_FIFO_DEPTH_OBSERVE_FIFO_DEPTH_FIELD \
515 ((bitfield_field32_t) { .mask = ENTROPY_SRC_OBSERVE_FIFO_DEPTH_OBSERVE_FIFO_DEPTH_MASK, .index = ENTROPY_SRC_OBSERVE_FIFO_DEPTH_OBSERVE_FIFO_DEPTH_OFFSET })
516
517// Debug status register
518#define ENTROPY_SRC_DEBUG_STATUS_REG_OFFSET 0xcc
519#define ENTROPY_SRC_DEBUG_STATUS_REG_RESVAL 0x10000u
520#define ENTROPY_SRC_DEBUG_STATUS_ENTROPY_FIFO_DEPTH_MASK 0x3u
521#define ENTROPY_SRC_DEBUG_STATUS_ENTROPY_FIFO_DEPTH_OFFSET 0
522#define ENTROPY_SRC_DEBUG_STATUS_ENTROPY_FIFO_DEPTH_FIELD \
523 ((bitfield_field32_t) { .mask = ENTROPY_SRC_DEBUG_STATUS_ENTROPY_FIFO_DEPTH_MASK, .index = ENTROPY_SRC_DEBUG_STATUS_ENTROPY_FIFO_DEPTH_OFFSET })
524#define ENTROPY_SRC_DEBUG_STATUS_SHA3_FSM_MASK 0x7u
525#define ENTROPY_SRC_DEBUG_STATUS_SHA3_FSM_OFFSET 3
526#define ENTROPY_SRC_DEBUG_STATUS_SHA3_FSM_FIELD \
527 ((bitfield_field32_t) { .mask = ENTROPY_SRC_DEBUG_STATUS_SHA3_FSM_MASK, .index = ENTROPY_SRC_DEBUG_STATUS_SHA3_FSM_OFFSET })
528#define ENTROPY_SRC_DEBUG_STATUS_SHA3_BLOCK_PR_BIT 6
529#define ENTROPY_SRC_DEBUG_STATUS_SHA3_SQUEEZING_BIT 7
530#define ENTROPY_SRC_DEBUG_STATUS_SHA3_ABSORBED_BIT 8
531#define ENTROPY_SRC_DEBUG_STATUS_SHA3_ERR_BIT 9
532#define ENTROPY_SRC_DEBUG_STATUS_MAIN_SM_IDLE_BIT 16
533#define ENTROPY_SRC_DEBUG_STATUS_MAIN_SM_BOOT_DONE_BIT 17
534
535// Recoverable alert status register
536#define ENTROPY_SRC_RECOV_ALERT_STS_REG_OFFSET 0xd0
537#define ENTROPY_SRC_RECOV_ALERT_STS_REG_RESVAL 0x0u
538#define ENTROPY_SRC_RECOV_ALERT_STS_FIPS_ENABLE_FIELD_ALERT_BIT 0
539#define ENTROPY_SRC_RECOV_ALERT_STS_ENTROPY_DATA_REG_EN_FIELD_ALERT_BIT 1
540#define ENTROPY_SRC_RECOV_ALERT_STS_MODULE_ENABLE_FIELD_ALERT_BIT 2
541#define ENTROPY_SRC_RECOV_ALERT_STS_THRESHOLD_SCOPE_FIELD_ALERT_BIT 3
542#define ENTROPY_SRC_RECOV_ALERT_STS_RNG_BIT_ENABLE_FIELD_ALERT_BIT 5
543#define ENTROPY_SRC_RECOV_ALERT_STS_FW_OV_SHA3_START_FIELD_ALERT_BIT 7
544#define ENTROPY_SRC_RECOV_ALERT_STS_FW_OV_MODE_FIELD_ALERT_BIT 8
545#define ENTROPY_SRC_RECOV_ALERT_STS_FW_OV_ENTROPY_INSERT_FIELD_ALERT_BIT 9
546#define ENTROPY_SRC_RECOV_ALERT_STS_ES_ROUTE_FIELD_ALERT_BIT 10
547#define ENTROPY_SRC_RECOV_ALERT_STS_ES_TYPE_FIELD_ALERT_BIT 11
548#define ENTROPY_SRC_RECOV_ALERT_STS_ES_MAIN_SM_ALERT_BIT 12
549#define ENTROPY_SRC_RECOV_ALERT_STS_ES_BUS_CMP_ALERT_BIT 13
550#define ENTROPY_SRC_RECOV_ALERT_STS_ES_THRESH_CFG_ALERT_BIT 14
551#define ENTROPY_SRC_RECOV_ALERT_STS_ES_FW_OV_WR_ALERT_BIT 15
552#define ENTROPY_SRC_RECOV_ALERT_STS_ES_FW_OV_DISABLE_ALERT_BIT 16
553#define ENTROPY_SRC_RECOV_ALERT_STS_FIPS_FLAG_FIELD_ALERT_BIT 17
554#define ENTROPY_SRC_RECOV_ALERT_STS_RNG_FIPS_FIELD_ALERT_BIT 18
555#define ENTROPY_SRC_RECOV_ALERT_STS_POSTHT_ENTROPY_DROP_ALERT_BIT 31
556
557// Hardware detection of error conditions status register
558#define ENTROPY_SRC_ERR_CODE_REG_OFFSET 0xd4
559#define ENTROPY_SRC_ERR_CODE_REG_RESVAL 0x0u
560#define ENTROPY_SRC_ERR_CODE_SFIFO_ESRNG_ERR_BIT 0
561#define ENTROPY_SRC_ERR_CODE_SFIFO_DISTR_ERR_BIT 1
562#define ENTROPY_SRC_ERR_CODE_SFIFO_OBSERVE_ERR_BIT 2
563#define ENTROPY_SRC_ERR_CODE_SFIFO_ESFINAL_ERR_BIT 3
564#define ENTROPY_SRC_ERR_CODE_ES_ACK_SM_ERR_BIT 20
565#define ENTROPY_SRC_ERR_CODE_ES_MAIN_SM_ERR_BIT 21
566#define ENTROPY_SRC_ERR_CODE_ES_CNTR_ERR_BIT 22
567#define ENTROPY_SRC_ERR_CODE_SHA3_STATE_ERR_BIT 23
568#define ENTROPY_SRC_ERR_CODE_SHA3_RST_STORAGE_ERR_BIT 24
569#define ENTROPY_SRC_ERR_CODE_FIFO_WRITE_ERR_BIT 28
570#define ENTROPY_SRC_ERR_CODE_FIFO_READ_ERR_BIT 29
571#define ENTROPY_SRC_ERR_CODE_FIFO_STATE_ERR_BIT 30
572
573// Test error conditions register
574#define ENTROPY_SRC_ERR_CODE_TEST_REG_OFFSET 0xd8
575#define ENTROPY_SRC_ERR_CODE_TEST_REG_RESVAL 0x0u
576#define ENTROPY_SRC_ERR_CODE_TEST_ERR_CODE_TEST_MASK 0x1fu
577#define ENTROPY_SRC_ERR_CODE_TEST_ERR_CODE_TEST_OFFSET 0
578#define ENTROPY_SRC_ERR_CODE_TEST_ERR_CODE_TEST_FIELD \
579 ((bitfield_field32_t) { .mask = ENTROPY_SRC_ERR_CODE_TEST_ERR_CODE_TEST_MASK, .index = ENTROPY_SRC_ERR_CODE_TEST_ERR_CODE_TEST_OFFSET })
580
581// Main state machine state debug register
582#define ENTROPY_SRC_MAIN_SM_STATE_REG_OFFSET 0xdc
583#define ENTROPY_SRC_MAIN_SM_STATE_REG_RESVAL 0xf5u
584#define ENTROPY_SRC_MAIN_SM_STATE_MAIN_SM_STATE_MASK 0x1ffu
585#define ENTROPY_SRC_MAIN_SM_STATE_MAIN_SM_STATE_OFFSET 0
586#define ENTROPY_SRC_MAIN_SM_STATE_MAIN_SM_STATE_FIELD \
587 ((bitfield_field32_t) { .mask = ENTROPY_SRC_MAIN_SM_STATE_MAIN_SM_STATE_MASK, .index = ENTROPY_SRC_MAIN_SM_STATE_MAIN_SM_STATE_OFFSET })
588
589#ifdef __cplusplus
590} // extern "C"
591#endif
592#endif // _ENTROPY_SRC_REG_DEFS_
593// End generated register defines for entropy_src