Software APIs
dt_sram_ctrl.h
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1// Copyright lowRISC contributors (OpenTitan project).
2// Licensed under the Apache License, Version 2.0, see LICENSE for details.
3// SPDX-License-Identifier: Apache-2.0
4//
5// Device table API auto-generated by `dtgen`
6
7#ifndef OPENTITAN_DT_SRAM_CTRL_H_
8#define OPENTITAN_DT_SRAM_CTRL_H_
9
10#ifdef __cplusplus
11extern "C" {
12#endif // __cplusplus
13
14/**
15 * @file
16 * @brief Device Tables (DT) for IP sram_ctrl and top darjeeling.
17 *
18 * This file contains the type definitions and global functions of the sram_ctrl.
19 */
20
21#include "hw/top/dt/dt_api.h"
22#include <stdint.h>
23
24
25
26/**
27 * List of instances.
28 */
29typedef enum dt_sram_ctrl {
30 kDtSramCtrlRetAon = 0, /**< sram_ctrl_ret_aon */
31 kDtSramCtrlMain = 1, /**< sram_ctrl_main */
32 kDtSramCtrlMbox = 2, /**< sram_ctrl_mbox */
33 kDtSramCtrlFirst = 0, /**< \internal First instance */
34 kDtSramCtrlCount = 3, /**< \internal Number of instances */
36
37/**
38 * List of register blocks.
39 *
40 * Register blocks are guaranteed to start at 0 and to be consecutively numbered.
41 */
43 kDtSramCtrlRegBlockRegs = 0, /**< */
44 kDtSramCtrlRegBlockCount = 1, /**< \internal Number of register blocks */
46
47/**
48 * List of memories.
49 *
50 * Memories are guaranteed to start at 0 and to be consecutively numbered.
51 */
52typedef enum dt_sram_ctrl_memory {
53 kDtSramCtrlMemoryRam = 0, /**< */
54 kDtSramCtrlMemoryCount = 1, /**< \internal Number of memories */
56
57/** Primary register block (associated with the "primary" set of registers that control the IP). */
58static const dt_sram_ctrl_reg_block_t kDtSramCtrlRegBlockPrimary = kDtSramCtrlRegBlockRegs;
59
60/**
61 * List of Alerts.
62 *
63 * Alerts are guaranteed to be numbered consecutively from 0.
64 */
65typedef enum dt_sram_ctrl_alert {
66 kDtSramCtrlAlertFatalError = 0, /**< This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected,
67or if the initialization mechanism has reached an invalid state. */
68 kDtSramCtrlAlertCount = 1, /**< \internal Number of Alerts */
70
71/**
72 * List of clock ports.
73 *
74 * Clock ports are guaranteed to be numbered consecutively from 0.
75 */
76typedef enum dt_sram_ctrl_clock {
77 kDtSramCtrlClockClk = 0, /**< Clock port clk_i */
78 kDtSramCtrlClockOtp = 1, /**< Clock port clk_otp_i */
79 kDtSramCtrlClockCount = 2, /**< \internal Number of clock ports */
81
82/**
83 * List of reset ports.
84 *
85 * Reset ports are guaranteed to be numbered consecutively from 0.
86 */
87typedef enum dt_sram_ctrl_reset {
88 kDtSramCtrlResetRst = 0, /**< Reset port rst_ni */
89 kDtSramCtrlResetOtp = 1, /**< Reset port rst_otp_ni */
90 kDtSramCtrlResetCount = 2, /**< \internal Number of reset ports */
92
93/**
94 * List of supported hardware features.
95 */
96#define OPENTITAN_SRAM_CTRL_HAS_INTEGRITY 1
97#define OPENTITAN_SRAM_CTRL_HAS_SCRAMBLED 1
98#define OPENTITAN_SRAM_CTRL_HAS_LOCK_ON_ERROR 1
99#define OPENTITAN_SRAM_CTRL_HAS_MEMSET 1
100#define OPENTITAN_SRAM_CTRL_HAS_FETCH_ALLOW 1
101#define OPENTITAN_SRAM_CTRL_HAS_SUBWORD_ACCESS 1
102#define OPENTITAN_SRAM_CTRL_HAS_REGWEN 1
103
104
105
106/**
107 * Get the sram_ctrl instance from an instance ID
108 *
109 * For example, `dt_uart_from_instance_id(kDtInstanceIdUart3) == kDtUart3`.
110 *
111 * @param inst_id Instance ID.
112 * @return A sram_ctrl instance.
113 *
114 * **Note:** This function only makes sense if the instance ID has device type sram_ctrl,
115 * otherwise the returned value is unspecified.
116 */
118
119/**
120 * Get the instance ID of an instance.
121 *
122 * @param dt Instance of sram_ctrl.
123 * @return The instance ID of that instance.
124 */
126
127/**
128 * Get the register base address of an instance.
129 *
130 * @param dt Instance of sram_ctrl.
131 * @param reg_block The register block requested.
132 * @return The register base address of the requested block.
133 */
136 dt_sram_ctrl_reg_block_t reg_block);
137
138/**
139 * Get the primary register base address of an instance.
140 *
141 * This is just a convenience function, equivalent to
142 * `dt_sram_ctrl_reg_block(dt, kDtSramCtrlRegBlockRegs)`
143 *
144 * @param dt Instance of sram_ctrl.
145 * @return The register base address of the primary register block.
146 */
147static inline uint32_t dt_sram_ctrl_primary_reg_block(
148 dt_sram_ctrl_t dt) {
149 return dt_sram_ctrl_reg_block(dt, kDtSramCtrlRegBlockRegs);
150}
151
152/**
153 * Get the base address of a memory.
154 *
155 * @param dt Instance of sram_ctrl.
156 * @param mem The memory requested.
157 * @return The base address of the requested memory.
158 */
162
163/**
164 * Get the size of a memory.
165 *
166 * @param dt Instance of sram_ctrl.
167 * @param mem The memory requested.
168 * @return The size of the requested memory.
169 */
173
174
175/**
176 * Get the alert ID of a sram_ctrl alert for a given instance.
177 *
178 * **Note:** This function only makes sense if the instance is connected to the Alert Handler. For any
179 * instances where the instance is not connected, the return value is unspecified.
180 *
181 * @param dt Instance of sram_ctrl.
182 * @param alert A sram_ctrl alert.
183 * @return The Alert Handler alert ID of the alert of this instance.
184 */
188
189/**
190 * Convert a global alert ID to a local sram_ctrl alert type.
191 *
192 * @param dt Instance of sram_ctrl.
193 * @param alert A global alert ID that belongs to this instance.
194 * @return The sram_ctrl alert, or `kDtSramCtrlAlertCount`.
195 *
196 * **Note:** This function assumes that the global alert ID belongs to the
197 * instance of sram_ctrl passed in parameter. In other words, it must be the case
198 * that `dt_sram_ctrl_instance_id(dt) == dt_alert_id_to_instance_id(alert)`. Otherwise,
199 * this function will return `kDtSramCtrlAlertCount`.
200 */
203 dt_alert_id_t alert);
204
205
206
207/**
208 * Get the clock signal connected to a clock port of an instance.
209 *
210 * @param dt Instance of sram_ctrl.
211 * @param clk Clock port.
212 * @return Clock signal.
213 */
217
218/**
219 * Get the reset signal connected to a reset port of an instance.
220 *
221 * @param dt Instance of sram_ctrl.
222 * @param rst Reset port.
223 * @return Reset signal.
224 */
228
229
230
231#ifdef __cplusplus
232} // extern "C"
233#endif // __cplusplus
234
235#endif // OPENTITAN_DT_SRAM_CTRL_H_