Software APIs
dt_sram_ctrl.h
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1// Copyright lowRISC contributors (OpenTitan project).
2// Licensed under the Apache License, Version 2.0, see LICENSE for details.
3// SPDX-License-Identifier: Apache-2.0
4//
5// Device table API auto-generated by `dtgen`
6
7#ifndef OPENTITAN_DT_SRAM_CTRL_H_
8#define OPENTITAN_DT_SRAM_CTRL_H_
9
10/**
11 * @file
12 * @brief Device Tables (DT) for IP sram_ctrl and top darjeeling.
13 *
14 * This file contains the type definitions and global functions of the sram_ctrl.
15 */
16
17#include "dt_api.h"
18#include <stdint.h>
19
20
21
22/**
23 * List of instances.
24 */
25typedef enum dt_sram_ctrl {
26 kDtSramCtrlRetAon = 0, /**< sram_ctrl_ret_aon */
27 kDtSramCtrlMain = 1, /**< sram_ctrl_main */
28 kDtSramCtrlMbox = 2, /**< sram_ctrl_mbox */
29 kDtSramCtrlFirst = 0, /**< \internal First instance */
30 kDtSramCtrlCount = 3, /**< \internal Number of instances */
32
33/**
34 * List of register blocks.
35 *
36 * Register blocks are guaranteed to start at 0 and to be consecutively numbered.
37 */
39 kDtSramCtrlRegBlockRegs = 0, /**< */
40 kDtSramCtrlRegBlockRam = 1, /**< */
41 kDtSramCtrlRegBlockCount = 2, /**< \internal Number of register blocks */
43
44/** Primary register block (associated with the "primary" set of registers that control the IP). */
45static const dt_sram_ctrl_reg_block_t kDtSramCtrlRegBlockPrimary = kDtSramCtrlRegBlockRegs;
46
47/**
48 * List of Alerts.
49 *
50 * Alerts are guaranteed to be numbered consecutively from 0.
51 */
52typedef enum dt_sram_ctrl_alert {
53 kDtSramCtrlAlertFatalError = 0, /**< This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected,
54or if the initialization mechanism has reached an invalid state. */
55 kDtSramCtrlAlertCount = 1, /**< \internal Number of Alerts */
57
58/**
59 * List of clock ports.
60 *
61 * Clock ports are guaranteed to be numbered consecutively from 0.
62 */
63typedef enum dt_sram_ctrl_clock {
64 kDtSramCtrlClockClk = 0, /**< Clock port clk_i */
65 kDtSramCtrlClockOtp = 1, /**< Clock port clk_otp_i */
66 kDtSramCtrlClockCount = 2, /**< \internal Number of clock ports */
68
69/**
70 * List of reset ports.
71 *
72 * Reset ports are guaranteed to be numbered consecutively from 0.
73 */
74typedef enum dt_sram_ctrl_reset {
75 kDtSramCtrlResetRst = 0, /**< Reset port rst_ni */
76 kDtSramCtrlResetOtp = 1, /**< Reset port rst_otp_ni */
77 kDtSramCtrlResetCount = 2, /**< \internal Number of reset ports */
79
80/**
81 * List of supported hardware features.
82 */
83#define OPENTITAN_SRAM_CTRL_HAS_INTEGRITY 1
84#define OPENTITAN_SRAM_CTRL_HAS_SCRAMBLED 1
85#define OPENTITAN_SRAM_CTRL_HAS_LOCK_ON_ERROR 1
86#define OPENTITAN_SRAM_CTRL_HAS_MEMSET 1
87#define OPENTITAN_SRAM_CTRL_HAS_FETCH_ALLOW 1
88#define OPENTITAN_SRAM_CTRL_HAS_SUBWORD_ACCESS 1
89#define OPENTITAN_SRAM_CTRL_HAS_REGWEN 1
90
91
92
93/**
94 * Get the sram_ctrl instance from an instance ID
95 *
96 * For example, `dt_uart_from_instance_id(kDtInstanceIdUart3) == kDtUart3`.
97 *
98 * @param inst_id Instance ID.
99 * @return A sram_ctrl instance.
100 *
101 * **Note:** This function only makes sense if the instance ID has device type sram_ctrl,
102 * otherwise the returned value is unspecified.
103 */
105
106/**
107 * Get the instance ID of an instance.
108 *
109 * @param dt Instance of sram_ctrl.
110 * @return The instance ID of that instance.
111 */
113
114/**
115 * Get the register base address of an instance.
116 *
117 * @param dt Instance of sram_ctrl.
118 * @param reg_block The register block requested.
119 * @return The register base address of the requested block.
120 */
123 dt_sram_ctrl_reg_block_t reg_block);
124
125/**
126 * Get the primary register base address of an instance.
127 *
128 * This is just a convenience function, equivalent to
129 * `dt_sram_ctrl_reg_block(dt, kDtSramCtrlRegBlockRegs)`
130 *
131 * @param dt Instance of sram_ctrl.
132 * @return The register base address of the primary register block.
133 */
134static inline uint32_t dt_sram_ctrl_primary_reg_block(
135 dt_sram_ctrl_t dt) {
136 return dt_sram_ctrl_reg_block(dt, kDtSramCtrlRegBlockRegs);
137}
138
139
140/**
141 * Get the alert ID of a sram_ctrl alert for a given instance.
142 *
143 * **Note:** This function only makes sense if the instance is connected to the Alert Handler. For any
144 * instances where the instance is not connected, the return value is unspecified.
145 *
146 * @param dt Instance of sram_ctrl.
147 * @param alert A sram_ctrl alert.
148 * @return The Alert Handler alert ID of the alert of this instance.
149 */
153
154/**
155 * Convert a global alert ID to a local sram_ctrl alert type.
156 *
157 * @param dt Instance of sram_ctrl.
158 * @param alert A global alert ID that belongs to this instance.
159 * @return The sram_ctrl alert, or `kDtSramCtrlAlertCount`.
160 *
161 * **Note:** This function assumes that the global alert ID belongs to the
162 * instance of sram_ctrl passed in parameter. In other words, it must be the case
163 * that `dt_sram_ctrl_instance_id(dt) == dt_alert_id_to_instance_id(alert)`. Otherwise,
164 * this function will return `kDtSramCtrlAlertCount`.
165 */
168 dt_alert_id_t alert);
169
170
171
172/**
173 * Get the clock signal connected to a clock port of an instance.
174 *
175 * @param dt Instance of sram_ctrl.
176 * @param clk Clock port.
177 * @return Clock signal.
178 */
182
183/**
184 * Get the reset signal connected to a reset port of an instance.
185 *
186 * @param dt Instance of sram_ctrl.
187 * @param rst Reset port.
188 * @return Reset signal.
189 */
193
194
195
196#endif // OPENTITAN_DT_SRAM_CTRL_H_