Software APIs
dt_rom_ctrl.h
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1// Copyright lowRISC contributors (OpenTitan project).
2// Licensed under the Apache License, Version 2.0, see LICENSE for details.
3// SPDX-License-Identifier: Apache-2.0
4//
5// Device table API auto-generated by `dtgen`
6
7#ifndef OPENTITAN_DT_ROM_CTRL_H_
8#define OPENTITAN_DT_ROM_CTRL_H_
9
10#ifdef __cplusplus
11extern "C" {
12#endif // __cplusplus
13
14/**
15 * @file
16 * @brief Device Tables (DT) for IP rom_ctrl and top darjeeling.
17 *
18 * This file contains the type definitions and global functions of the rom_ctrl.
19 */
20
21#include "hw/top/dt/dt_api.h"
22#include <stdint.h>
23
24
25
26/**
27 * List of instances.
28 */
29typedef enum dt_rom_ctrl {
30 kDtRomCtrl0 = 0, /**< rom_ctrl0 */
31 kDtRomCtrl1 = 1, /**< rom_ctrl1 */
32 kDtRomCtrlFirst = 0, /**< \internal First instance */
33 kDtRomCtrlCount = 2, /**< \internal Number of instances */
35
36/**
37 * List of register blocks.
38 *
39 * Register blocks are guaranteed to start at 0 and to be consecutively numbered.
40 */
42 kDtRomCtrlRegBlockRegs = 0, /**< */
43 kDtRomCtrlRegBlockCount = 1, /**< \internal Number of register blocks */
45
46/**
47 * List of memories.
48 *
49 * Memories are guaranteed to start at 0 and to be consecutively numbered.
50 */
51typedef enum dt_rom_ctrl_memory {
52 kDtRomCtrlMemoryRom = 0, /**< */
53 kDtRomCtrlMemoryCount = 1, /**< \internal Number of memories */
55
56/** Primary register block (associated with the "primary" set of registers that control the IP). */
57static const dt_rom_ctrl_reg_block_t kDtRomCtrlRegBlockPrimary = kDtRomCtrlRegBlockRegs;
58
59/**
60 * List of Alerts.
61 *
62 * Alerts are guaranteed to be numbered consecutively from 0.
63 */
64typedef enum dt_rom_ctrl_alert {
65 kDtRomCtrlAlertFatal = 0, /**< A fatal error. Fatal alerts are non-recoverable and will be asserted until a hard reset. */
66 kDtRomCtrlAlertCount = 1, /**< \internal Number of Alerts */
68
69/**
70 * List of clock ports.
71 *
72 * Clock ports are guaranteed to be numbered consecutively from 0.
73 */
74typedef enum dt_rom_ctrl_clock {
75 kDtRomCtrlClockClk = 0, /**< Clock port clk_i */
76 kDtRomCtrlClockCount = 1, /**< \internal Number of clock ports */
78
79/**
80 * List of reset ports.
81 *
82 * Reset ports are guaranteed to be numbered consecutively from 0.
83 */
84typedef enum dt_rom_ctrl_reset {
85 kDtRomCtrlResetRst = 0, /**< Reset port rst_ni */
86 kDtRomCtrlResetCount = 1, /**< \internal Number of reset ports */
88
89/**
90 * List of supported hardware features.
91 */
92#define OPENTITAN_ROM_CTRL_HAS_SCRAMBLED 1
93#define OPENTITAN_ROM_CTRL_HAS_DIGESTS 1
94#define OPENTITAN_ROM_CTRL_HAS_EXP_DIGESTS 1
95
96
97
98/**
99 * Get the rom_ctrl instance from an instance ID
100 *
101 * For example, `dt_uart_from_instance_id(kDtInstanceIdUart3) == kDtUart3`.
102 *
103 * @param inst_id Instance ID.
104 * @return A rom_ctrl instance.
105 *
106 * **Note:** This function only makes sense if the instance ID has device type rom_ctrl,
107 * otherwise the returned value is unspecified.
108 */
110
111/**
112 * Get the instance ID of an instance.
113 *
114 * @param dt Instance of rom_ctrl.
115 * @return The instance ID of that instance.
116 */
118
119/**
120 * Get the register base address of an instance.
121 *
122 * @param dt Instance of rom_ctrl.
123 * @param reg_block The register block requested.
124 * @return The register base address of the requested block.
125 */
126uint32_t dt_rom_ctrl_reg_block(
127 dt_rom_ctrl_t dt,
128 dt_rom_ctrl_reg_block_t reg_block);
129
130/**
131 * Get the primary register base address of an instance.
132 *
133 * This is just a convenience function, equivalent to
134 * `dt_rom_ctrl_reg_block(dt, kDtRomCtrlRegBlockRegs)`
135 *
136 * @param dt Instance of rom_ctrl.
137 * @return The register base address of the primary register block.
138 */
139static inline uint32_t dt_rom_ctrl_primary_reg_block(
140 dt_rom_ctrl_t dt) {
141 return dt_rom_ctrl_reg_block(dt, kDtRomCtrlRegBlockRegs);
142}
143
144/**
145 * Get the base address of a memory.
146 *
147 * @param dt Instance of rom_ctrl.
148 * @param mem The memory requested.
149 * @return The base address of the requested memory.
150 */
152 dt_rom_ctrl_t dt,
154
155/**
156 * Get the size of a memory.
157 *
158 * @param dt Instance of rom_ctrl.
159 * @param mem The memory requested.
160 * @return The size of the requested memory.
161 */
163 dt_rom_ctrl_t dt,
165
166
167/**
168 * Get the alert ID of a rom_ctrl alert for a given instance.
169 *
170 * **Note:** This function only makes sense if the instance is connected to the Alert Handler. For any
171 * instances where the instance is not connected, the return value is unspecified.
172 *
173 * @param dt Instance of rom_ctrl.
174 * @param alert A rom_ctrl alert.
175 * @return The Alert Handler alert ID of the alert of this instance.
176 */
178 dt_rom_ctrl_t dt,
179 dt_rom_ctrl_alert_t alert);
180
181/**
182 * Convert a global alert ID to a local rom_ctrl alert type.
183 *
184 * @param dt Instance of rom_ctrl.
185 * @param alert A global alert ID that belongs to this instance.
186 * @return The rom_ctrl alert, or `kDtRomCtrlAlertCount`.
187 *
188 * **Note:** This function assumes that the global alert ID belongs to the
189 * instance of rom_ctrl passed in parameter. In other words, it must be the case
190 * that `dt_rom_ctrl_instance_id(dt) == dt_alert_id_to_instance_id(alert)`. Otherwise,
191 * this function will return `kDtRomCtrlAlertCount`.
192 */
194 dt_rom_ctrl_t dt,
195 dt_alert_id_t alert);
196
197
198
199/**
200 * Get the clock signal connected to a clock port of an instance.
201 *
202 * @param dt Instance of rom_ctrl.
203 * @param clk Clock port.
204 * @return Clock signal.
205 */
207 dt_rom_ctrl_t dt,
209
210/**
211 * Get the reset signal connected to a reset port of an instance.
212 *
213 * @param dt Instance of rom_ctrl.
214 * @param rst Reset port.
215 * @return Reset signal.
216 */
218 dt_rom_ctrl_t dt,
220
221
222
223#ifdef __cplusplus
224} // extern "C"
225#endif // __cplusplus
226
227#endif // OPENTITAN_DT_ROM_CTRL_H_