clkmgr_regs.h

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/**
 * @file
 * @brief Generated register defines for clkmgr
 */
 
// Copyright information found in source file:
// Copyright lowRISC contributors (OpenTitan project).
 
// Licensing information found in source file:
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
 
#ifndef _CLKMGR_REG_DEFS_
#define _CLKMGR_REG_DEFS_
 
#ifdef __cplusplus
extern "C" {
#endif
// Number of clock groups
#define CLKMGR_PARAM_NUM_GROUPS 7
 
// Number of SW gateable clocks
#define CLKMGR_PARAM_NUM_SW_GATEABLE_CLOCKS 1
 
// Number of hintable clocks
#define CLKMGR_PARAM_NUM_HINTABLE_CLOCKS 4
 
// Number of alerts
#define CLKMGR_PARAM_NUM_ALERTS 2
 
// Register width
#define CLKMGR_PARAM_REG_WIDTH 32
 
// Alert Test Register
#define CLKMGR_ALERT_TEST_REG_OFFSET 0x0
#define CLKMGR_ALERT_TEST_REG_RESVAL 0x80000000u
#define CLKMGR_ALERT_TEST_RECOV_FAULT_BIT 0
#define CLKMGR_ALERT_TEST_FATAL_FAULT_BIT 1
#define CLKMGR_ALERT_TEST_REGWEN_BIT 31
 
// Jitter write enable
#define CLKMGR_JITTER_REGWEN_REG_OFFSET 0x10
#define CLKMGR_JITTER_REGWEN_REG_RESVAL 0x1u
#define CLKMGR_JITTER_REGWEN_EN_BIT 0
 
// Enable jittery clock
#define CLKMGR_JITTER_ENABLE_REG_OFFSET 0x14
#define CLKMGR_JITTER_ENABLE_REG_RESVAL 0x9u
#define CLKMGR_JITTER_ENABLE_VAL_MASK 0xfu
#define CLKMGR_JITTER_ENABLE_VAL_OFFSET 0
#define CLKMGR_JITTER_ENABLE_VAL_FIELD \
  ((bitfield_field32_t) { .mask = CLKMGR_JITTER_ENABLE_VAL_MASK, .index = CLKMGR_JITTER_ENABLE_VAL_OFFSET })
 
// Clock enable for software gateable clocks.
#define CLKMGR_CLK_ENABLES_REG_OFFSET 0x18
#define CLKMGR_CLK_ENABLES_REG_RESVAL 0x1u
#define CLKMGR_CLK_ENABLES_CLK_IO_PERI_EN_BIT 0
 
// Clock hint for software gateable transactional clocks during active mode.
#define CLKMGR_CLK_HINTS_REG_OFFSET 0x1c
#define CLKMGR_CLK_HINTS_REG_RESVAL 0xfu
#define CLKMGR_CLK_HINTS_CLK_MAIN_AES_HINT_BIT 0
#define CLKMGR_CLK_HINTS_CLK_MAIN_HMAC_HINT_BIT 1
#define CLKMGR_CLK_HINTS_CLK_MAIN_KMAC_HINT_BIT 2
#define CLKMGR_CLK_HINTS_CLK_MAIN_OTBN_HINT_BIT 3
 
// Since the final state of !!CLK_HINTS is not always determined by software,
#define CLKMGR_CLK_HINTS_STATUS_REG_OFFSET 0x20
#define CLKMGR_CLK_HINTS_STATUS_REG_RESVAL 0xfu
#define CLKMGR_CLK_HINTS_STATUS_CLK_MAIN_AES_VAL_BIT 0
#define CLKMGR_CLK_HINTS_STATUS_CLK_MAIN_HMAC_VAL_BIT 1
#define CLKMGR_CLK_HINTS_STATUS_CLK_MAIN_KMAC_VAL_BIT 2
#define CLKMGR_CLK_HINTS_STATUS_CLK_MAIN_OTBN_VAL_BIT 3
 
// Measurement control write enable
#define CLKMGR_MEASURE_CTRL_REGWEN_REG_OFFSET 0x24
#define CLKMGR_MEASURE_CTRL_REGWEN_REG_RESVAL 0x1u
#define CLKMGR_MEASURE_CTRL_REGWEN_EN_BIT 0
 
// Enable for measurement control
#define CLKMGR_IO_MEAS_CTRL_EN_REG_OFFSET 0x28
#define CLKMGR_IO_MEAS_CTRL_EN_REG_RESVAL 0x9u
#define CLKMGR_IO_MEAS_CTRL_EN_EN_MASK 0xfu
#define CLKMGR_IO_MEAS_CTRL_EN_EN_OFFSET 0
#define CLKMGR_IO_MEAS_CTRL_EN_EN_FIELD \
  ((bitfield_field32_t) { .mask = CLKMGR_IO_MEAS_CTRL_EN_EN_MASK, .index = CLKMGR_IO_MEAS_CTRL_EN_EN_OFFSET })
 
// Configuration controls for io measurement.
#define CLKMGR_IO_MEAS_CTRL_SHADOWED_REG_OFFSET 0x2c
#define CLKMGR_IO_MEAS_CTRL_SHADOWED_REG_RESVAL 0xec8au
#define CLKMGR_IO_MEAS_CTRL_SHADOWED_HI_MASK 0x1ffu
#define CLKMGR_IO_MEAS_CTRL_SHADOWED_HI_OFFSET 0
#define CLKMGR_IO_MEAS_CTRL_SHADOWED_HI_FIELD \
  ((bitfield_field32_t) { .mask = CLKMGR_IO_MEAS_CTRL_SHADOWED_HI_MASK, .index = CLKMGR_IO_MEAS_CTRL_SHADOWED_HI_OFFSET })
#define CLKMGR_IO_MEAS_CTRL_SHADOWED_LO_MASK 0x1ffu
#define CLKMGR_IO_MEAS_CTRL_SHADOWED_LO_OFFSET 9
#define CLKMGR_IO_MEAS_CTRL_SHADOWED_LO_FIELD \
  ((bitfield_field32_t) { .mask = CLKMGR_IO_MEAS_CTRL_SHADOWED_LO_MASK, .index = CLKMGR_IO_MEAS_CTRL_SHADOWED_LO_OFFSET })
 
// Enable for measurement control
#define CLKMGR_MAIN_MEAS_CTRL_EN_REG_OFFSET 0x30
#define CLKMGR_MAIN_MEAS_CTRL_EN_REG_RESVAL 0x9u
#define CLKMGR_MAIN_MEAS_CTRL_EN_EN_MASK 0xfu
#define CLKMGR_MAIN_MEAS_CTRL_EN_EN_OFFSET 0
#define CLKMGR_MAIN_MEAS_CTRL_EN_EN_FIELD \
  ((bitfield_field32_t) { .mask = CLKMGR_MAIN_MEAS_CTRL_EN_EN_MASK, .index = CLKMGR_MAIN_MEAS_CTRL_EN_EN_OFFSET })
 
// Configuration controls for main measurement.
#define CLKMGR_MAIN_MEAS_CTRL_SHADOWED_REG_OFFSET 0x34
#define CLKMGR_MAIN_MEAS_CTRL_SHADOWED_REG_RESVAL 0xec8au
#define CLKMGR_MAIN_MEAS_CTRL_SHADOWED_HI_MASK 0x1ffu
#define CLKMGR_MAIN_MEAS_CTRL_SHADOWED_HI_OFFSET 0
#define CLKMGR_MAIN_MEAS_CTRL_SHADOWED_HI_FIELD \
  ((bitfield_field32_t) { .mask = CLKMGR_MAIN_MEAS_CTRL_SHADOWED_HI_MASK, .index = CLKMGR_MAIN_MEAS_CTRL_SHADOWED_HI_OFFSET })
#define CLKMGR_MAIN_MEAS_CTRL_SHADOWED_LO_MASK 0x1ffu
#define CLKMGR_MAIN_MEAS_CTRL_SHADOWED_LO_OFFSET 9
#define CLKMGR_MAIN_MEAS_CTRL_SHADOWED_LO_FIELD \
  ((bitfield_field32_t) { .mask = CLKMGR_MAIN_MEAS_CTRL_SHADOWED_LO_MASK, .index = CLKMGR_MAIN_MEAS_CTRL_SHADOWED_LO_OFFSET })
 
// Recoverable Error code
#define CLKMGR_RECOV_ERR_CODE_REG_OFFSET 0x38
#define CLKMGR_RECOV_ERR_CODE_REG_RESVAL 0x0u
#define CLKMGR_RECOV_ERR_CODE_SHADOW_UPDATE_ERR_BIT 0
#define CLKMGR_RECOV_ERR_CODE_IO_MEASURE_ERR_BIT 1
#define CLKMGR_RECOV_ERR_CODE_MAIN_MEASURE_ERR_BIT 2
#define CLKMGR_RECOV_ERR_CODE_IO_TIMEOUT_ERR_BIT 3
#define CLKMGR_RECOV_ERR_CODE_MAIN_TIMEOUT_ERR_BIT 4
 
// Error code
#define CLKMGR_FATAL_ERR_CODE_REG_OFFSET 0x3c
#define CLKMGR_FATAL_ERR_CODE_REG_RESVAL 0x0u
#define CLKMGR_FATAL_ERR_CODE_REG_INTG_BIT 0
#define CLKMGR_FATAL_ERR_CODE_IDLE_CNT_BIT 1
#define CLKMGR_FATAL_ERR_CODE_SHADOW_STORAGE_ERR_BIT 2
 
#ifdef __cplusplus
}  // extern "C"
#endif
#endif  // _CLKMGR_REG_DEFS_
// End generated register defines for clkmgr