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13#ifndef _ALERT_HANDLER_REG_DEFS_
14#define _ALERT_HANDLER_REG_DEFS_
20#define ALERT_HANDLER_PARAM_N_ALERTS 105
23#define ALERT_HANDLER_PARAM_N_LPG 18
26#define ALERT_HANDLER_PARAM_N_LPG_WIDTH 5
29#define ALERT_HANDLER_PARAM_ESC_CNT_DW 32
32#define ALERT_HANDLER_PARAM_ACCU_CNT_DW 16
35#define ALERT_HANDLER_PARAM_N_CLASSES 4
38#define ALERT_HANDLER_PARAM_N_ESC_SEV 4
41#define ALERT_HANDLER_PARAM_N_PHASES 4
44#define ALERT_HANDLER_PARAM_N_LOC_ALERT 7
47#define ALERT_HANDLER_PARAM_PING_CNT_DW 16
50#define ALERT_HANDLER_PARAM_PHASE_DW 2
53#define ALERT_HANDLER_PARAM_CLASS_DW 2
56#define ALERT_HANDLER_PARAM_LOCAL_ALERT_ID_ALERT_PINGFAIL 0
59#define ALERT_HANDLER_PARAM_LOCAL_ALERT_ID_ESC_PINGFAIL 1
62#define ALERT_HANDLER_PARAM_LOCAL_ALERT_ID_ALERT_INTEGFAIL 2
65#define ALERT_HANDLER_PARAM_LOCAL_ALERT_ID_ESC_INTEGFAIL 3
68#define ALERT_HANDLER_PARAM_LOCAL_ALERT_ID_BUS_INTEGFAIL 4
71#define ALERT_HANDLER_PARAM_LOCAL_ALERT_ID_SHADOW_REG_UPDATE_ERROR 5
74#define ALERT_HANDLER_PARAM_LOCAL_ALERT_ID_SHADOW_REG_STORAGE_ERROR 6
77#define ALERT_HANDLER_PARAM_LOCAL_ALERT_ID_LAST 6
80#define ALERT_HANDLER_PARAM_REG_WIDTH 32
83#define ALERT_HANDLER_INTR_COMMON_CLASSA_BIT 0
84#define ALERT_HANDLER_INTR_COMMON_CLASSB_BIT 1
85#define ALERT_HANDLER_INTR_COMMON_CLASSC_BIT 2
86#define ALERT_HANDLER_INTR_COMMON_CLASSD_BIT 3
89#define ALERT_HANDLER_INTR_STATE_REG_OFFSET 0x0
90#define ALERT_HANDLER_INTR_STATE_REG_RESVAL 0x0u
91#define ALERT_HANDLER_INTR_STATE_CLASSA_BIT 0
92#define ALERT_HANDLER_INTR_STATE_CLASSB_BIT 1
93#define ALERT_HANDLER_INTR_STATE_CLASSC_BIT 2
94#define ALERT_HANDLER_INTR_STATE_CLASSD_BIT 3
97#define ALERT_HANDLER_INTR_ENABLE_REG_OFFSET 0x4
98#define ALERT_HANDLER_INTR_ENABLE_REG_RESVAL 0x0u
99#define ALERT_HANDLER_INTR_ENABLE_CLASSA_BIT 0
100#define ALERT_HANDLER_INTR_ENABLE_CLASSB_BIT 1
101#define ALERT_HANDLER_INTR_ENABLE_CLASSC_BIT 2
102#define ALERT_HANDLER_INTR_ENABLE_CLASSD_BIT 3
105#define ALERT_HANDLER_INTR_TEST_REG_OFFSET 0x8
106#define ALERT_HANDLER_INTR_TEST_REG_RESVAL 0x0u
107#define ALERT_HANDLER_INTR_TEST_CLASSA_BIT 0
108#define ALERT_HANDLER_INTR_TEST_CLASSB_BIT 1
109#define ALERT_HANDLER_INTR_TEST_CLASSC_BIT 2
110#define ALERT_HANDLER_INTR_TEST_CLASSD_BIT 3
114#define ALERT_HANDLER_PING_TIMER_REGWEN_REG_OFFSET 0xc
115#define ALERT_HANDLER_PING_TIMER_REGWEN_REG_RESVAL 0x1u
116#define ALERT_HANDLER_PING_TIMER_REGWEN_PING_TIMER_REGWEN_BIT 0
119#define ALERT_HANDLER_PING_TIMEOUT_CYC_SHADOWED_REG_OFFSET 0x10
120#define ALERT_HANDLER_PING_TIMEOUT_CYC_SHADOWED_REG_RESVAL 0x100u
121#define ALERT_HANDLER_PING_TIMEOUT_CYC_SHADOWED_PING_TIMEOUT_CYC_SHADOWED_MASK \
123#define ALERT_HANDLER_PING_TIMEOUT_CYC_SHADOWED_PING_TIMEOUT_CYC_SHADOWED_OFFSET \
125#define ALERT_HANDLER_PING_TIMEOUT_CYC_SHADOWED_PING_TIMEOUT_CYC_SHADOWED_FIELD \
126 ((bitfield_field32_t) { .mask = ALERT_HANDLER_PING_TIMEOUT_CYC_SHADOWED_PING_TIMEOUT_CYC_SHADOWED_MASK, .index = ALERT_HANDLER_PING_TIMEOUT_CYC_SHADOWED_PING_TIMEOUT_CYC_SHADOWED_OFFSET })
129#define ALERT_HANDLER_PING_TIMER_EN_SHADOWED_REG_OFFSET 0x14
130#define ALERT_HANDLER_PING_TIMER_EN_SHADOWED_REG_RESVAL 0x0u
131#define ALERT_HANDLER_PING_TIMER_EN_SHADOWED_PING_TIMER_EN_SHADOWED_BIT 0
134#define ALERT_HANDLER_ALERT_REGWEN_EN_FIELD_WIDTH 1
135#define ALERT_HANDLER_ALERT_REGWEN_MULTIREG_COUNT 105
138#define ALERT_HANDLER_ALERT_REGWEN_0_REG_OFFSET 0x18
139#define ALERT_HANDLER_ALERT_REGWEN_0_REG_RESVAL 0x1u
140#define ALERT_HANDLER_ALERT_REGWEN_0_EN_0_BIT 0
143#define ALERT_HANDLER_ALERT_REGWEN_1_REG_OFFSET 0x1c
144#define ALERT_HANDLER_ALERT_REGWEN_1_REG_RESVAL 0x1u
145#define ALERT_HANDLER_ALERT_REGWEN_1_EN_1_BIT 0
148#define ALERT_HANDLER_ALERT_REGWEN_2_REG_OFFSET 0x20
149#define ALERT_HANDLER_ALERT_REGWEN_2_REG_RESVAL 0x1u
150#define ALERT_HANDLER_ALERT_REGWEN_2_EN_2_BIT 0
153#define ALERT_HANDLER_ALERT_REGWEN_3_REG_OFFSET 0x24
154#define ALERT_HANDLER_ALERT_REGWEN_3_REG_RESVAL 0x1u
155#define ALERT_HANDLER_ALERT_REGWEN_3_EN_3_BIT 0
158#define ALERT_HANDLER_ALERT_REGWEN_4_REG_OFFSET 0x28
159#define ALERT_HANDLER_ALERT_REGWEN_4_REG_RESVAL 0x1u
160#define ALERT_HANDLER_ALERT_REGWEN_4_EN_4_BIT 0
163#define ALERT_HANDLER_ALERT_REGWEN_5_REG_OFFSET 0x2c
164#define ALERT_HANDLER_ALERT_REGWEN_5_REG_RESVAL 0x1u
165#define ALERT_HANDLER_ALERT_REGWEN_5_EN_5_BIT 0
168#define ALERT_HANDLER_ALERT_REGWEN_6_REG_OFFSET 0x30
169#define ALERT_HANDLER_ALERT_REGWEN_6_REG_RESVAL 0x1u
170#define ALERT_HANDLER_ALERT_REGWEN_6_EN_6_BIT 0
173#define ALERT_HANDLER_ALERT_REGWEN_7_REG_OFFSET 0x34
174#define ALERT_HANDLER_ALERT_REGWEN_7_REG_RESVAL 0x1u
175#define ALERT_HANDLER_ALERT_REGWEN_7_EN_7_BIT 0
178#define ALERT_HANDLER_ALERT_REGWEN_8_REG_OFFSET 0x38
179#define ALERT_HANDLER_ALERT_REGWEN_8_REG_RESVAL 0x1u
180#define ALERT_HANDLER_ALERT_REGWEN_8_EN_8_BIT 0
183#define ALERT_HANDLER_ALERT_REGWEN_9_REG_OFFSET 0x3c
184#define ALERT_HANDLER_ALERT_REGWEN_9_REG_RESVAL 0x1u
185#define ALERT_HANDLER_ALERT_REGWEN_9_EN_9_BIT 0
188#define ALERT_HANDLER_ALERT_REGWEN_10_REG_OFFSET 0x40
189#define ALERT_HANDLER_ALERT_REGWEN_10_REG_RESVAL 0x1u
190#define ALERT_HANDLER_ALERT_REGWEN_10_EN_10_BIT 0
193#define ALERT_HANDLER_ALERT_REGWEN_11_REG_OFFSET 0x44
194#define ALERT_HANDLER_ALERT_REGWEN_11_REG_RESVAL 0x1u
195#define ALERT_HANDLER_ALERT_REGWEN_11_EN_11_BIT 0
198#define ALERT_HANDLER_ALERT_REGWEN_12_REG_OFFSET 0x48
199#define ALERT_HANDLER_ALERT_REGWEN_12_REG_RESVAL 0x1u
200#define ALERT_HANDLER_ALERT_REGWEN_12_EN_12_BIT 0
203#define ALERT_HANDLER_ALERT_REGWEN_13_REG_OFFSET 0x4c
204#define ALERT_HANDLER_ALERT_REGWEN_13_REG_RESVAL 0x1u
205#define ALERT_HANDLER_ALERT_REGWEN_13_EN_13_BIT 0
208#define ALERT_HANDLER_ALERT_REGWEN_14_REG_OFFSET 0x50
209#define ALERT_HANDLER_ALERT_REGWEN_14_REG_RESVAL 0x1u
210#define ALERT_HANDLER_ALERT_REGWEN_14_EN_14_BIT 0
213#define ALERT_HANDLER_ALERT_REGWEN_15_REG_OFFSET 0x54
214#define ALERT_HANDLER_ALERT_REGWEN_15_REG_RESVAL 0x1u
215#define ALERT_HANDLER_ALERT_REGWEN_15_EN_15_BIT 0
218#define ALERT_HANDLER_ALERT_REGWEN_16_REG_OFFSET 0x58
219#define ALERT_HANDLER_ALERT_REGWEN_16_REG_RESVAL 0x1u
220#define ALERT_HANDLER_ALERT_REGWEN_16_EN_16_BIT 0
223#define ALERT_HANDLER_ALERT_REGWEN_17_REG_OFFSET 0x5c
224#define ALERT_HANDLER_ALERT_REGWEN_17_REG_RESVAL 0x1u
225#define ALERT_HANDLER_ALERT_REGWEN_17_EN_17_BIT 0
228#define ALERT_HANDLER_ALERT_REGWEN_18_REG_OFFSET 0x60
229#define ALERT_HANDLER_ALERT_REGWEN_18_REG_RESVAL 0x1u
230#define ALERT_HANDLER_ALERT_REGWEN_18_EN_18_BIT 0
233#define ALERT_HANDLER_ALERT_REGWEN_19_REG_OFFSET 0x64
234#define ALERT_HANDLER_ALERT_REGWEN_19_REG_RESVAL 0x1u
235#define ALERT_HANDLER_ALERT_REGWEN_19_EN_19_BIT 0
238#define ALERT_HANDLER_ALERT_REGWEN_20_REG_OFFSET 0x68
239#define ALERT_HANDLER_ALERT_REGWEN_20_REG_RESVAL 0x1u
240#define ALERT_HANDLER_ALERT_REGWEN_20_EN_20_BIT 0
243#define ALERT_HANDLER_ALERT_REGWEN_21_REG_OFFSET 0x6c
244#define ALERT_HANDLER_ALERT_REGWEN_21_REG_RESVAL 0x1u
245#define ALERT_HANDLER_ALERT_REGWEN_21_EN_21_BIT 0
248#define ALERT_HANDLER_ALERT_REGWEN_22_REG_OFFSET 0x70
249#define ALERT_HANDLER_ALERT_REGWEN_22_REG_RESVAL 0x1u
250#define ALERT_HANDLER_ALERT_REGWEN_22_EN_22_BIT 0
253#define ALERT_HANDLER_ALERT_REGWEN_23_REG_OFFSET 0x74
254#define ALERT_HANDLER_ALERT_REGWEN_23_REG_RESVAL 0x1u
255#define ALERT_HANDLER_ALERT_REGWEN_23_EN_23_BIT 0
258#define ALERT_HANDLER_ALERT_REGWEN_24_REG_OFFSET 0x78
259#define ALERT_HANDLER_ALERT_REGWEN_24_REG_RESVAL 0x1u
260#define ALERT_HANDLER_ALERT_REGWEN_24_EN_24_BIT 0
263#define ALERT_HANDLER_ALERT_REGWEN_25_REG_OFFSET 0x7c
264#define ALERT_HANDLER_ALERT_REGWEN_25_REG_RESVAL 0x1u
265#define ALERT_HANDLER_ALERT_REGWEN_25_EN_25_BIT 0
268#define ALERT_HANDLER_ALERT_REGWEN_26_REG_OFFSET 0x80
269#define ALERT_HANDLER_ALERT_REGWEN_26_REG_RESVAL 0x1u
270#define ALERT_HANDLER_ALERT_REGWEN_26_EN_26_BIT 0
273#define ALERT_HANDLER_ALERT_REGWEN_27_REG_OFFSET 0x84
274#define ALERT_HANDLER_ALERT_REGWEN_27_REG_RESVAL 0x1u
275#define ALERT_HANDLER_ALERT_REGWEN_27_EN_27_BIT 0
278#define ALERT_HANDLER_ALERT_REGWEN_28_REG_OFFSET 0x88
279#define ALERT_HANDLER_ALERT_REGWEN_28_REG_RESVAL 0x1u
280#define ALERT_HANDLER_ALERT_REGWEN_28_EN_28_BIT 0
283#define ALERT_HANDLER_ALERT_REGWEN_29_REG_OFFSET 0x8c
284#define ALERT_HANDLER_ALERT_REGWEN_29_REG_RESVAL 0x1u
285#define ALERT_HANDLER_ALERT_REGWEN_29_EN_29_BIT 0
288#define ALERT_HANDLER_ALERT_REGWEN_30_REG_OFFSET 0x90
289#define ALERT_HANDLER_ALERT_REGWEN_30_REG_RESVAL 0x1u
290#define ALERT_HANDLER_ALERT_REGWEN_30_EN_30_BIT 0
293#define ALERT_HANDLER_ALERT_REGWEN_31_REG_OFFSET 0x94
294#define ALERT_HANDLER_ALERT_REGWEN_31_REG_RESVAL 0x1u
295#define ALERT_HANDLER_ALERT_REGWEN_31_EN_31_BIT 0
298#define ALERT_HANDLER_ALERT_REGWEN_32_REG_OFFSET 0x98
299#define ALERT_HANDLER_ALERT_REGWEN_32_REG_RESVAL 0x1u
300#define ALERT_HANDLER_ALERT_REGWEN_32_EN_32_BIT 0
303#define ALERT_HANDLER_ALERT_REGWEN_33_REG_OFFSET 0x9c
304#define ALERT_HANDLER_ALERT_REGWEN_33_REG_RESVAL 0x1u
305#define ALERT_HANDLER_ALERT_REGWEN_33_EN_33_BIT 0
308#define ALERT_HANDLER_ALERT_REGWEN_34_REG_OFFSET 0xa0
309#define ALERT_HANDLER_ALERT_REGWEN_34_REG_RESVAL 0x1u
310#define ALERT_HANDLER_ALERT_REGWEN_34_EN_34_BIT 0
313#define ALERT_HANDLER_ALERT_REGWEN_35_REG_OFFSET 0xa4
314#define ALERT_HANDLER_ALERT_REGWEN_35_REG_RESVAL 0x1u
315#define ALERT_HANDLER_ALERT_REGWEN_35_EN_35_BIT 0
318#define ALERT_HANDLER_ALERT_REGWEN_36_REG_OFFSET 0xa8
319#define ALERT_HANDLER_ALERT_REGWEN_36_REG_RESVAL 0x1u
320#define ALERT_HANDLER_ALERT_REGWEN_36_EN_36_BIT 0
323#define ALERT_HANDLER_ALERT_REGWEN_37_REG_OFFSET 0xac
324#define ALERT_HANDLER_ALERT_REGWEN_37_REG_RESVAL 0x1u
325#define ALERT_HANDLER_ALERT_REGWEN_37_EN_37_BIT 0
328#define ALERT_HANDLER_ALERT_REGWEN_38_REG_OFFSET 0xb0
329#define ALERT_HANDLER_ALERT_REGWEN_38_REG_RESVAL 0x1u
330#define ALERT_HANDLER_ALERT_REGWEN_38_EN_38_BIT 0
333#define ALERT_HANDLER_ALERT_REGWEN_39_REG_OFFSET 0xb4
334#define ALERT_HANDLER_ALERT_REGWEN_39_REG_RESVAL 0x1u
335#define ALERT_HANDLER_ALERT_REGWEN_39_EN_39_BIT 0
338#define ALERT_HANDLER_ALERT_REGWEN_40_REG_OFFSET 0xb8
339#define ALERT_HANDLER_ALERT_REGWEN_40_REG_RESVAL 0x1u
340#define ALERT_HANDLER_ALERT_REGWEN_40_EN_40_BIT 0
343#define ALERT_HANDLER_ALERT_REGWEN_41_REG_OFFSET 0xbc
344#define ALERT_HANDLER_ALERT_REGWEN_41_REG_RESVAL 0x1u
345#define ALERT_HANDLER_ALERT_REGWEN_41_EN_41_BIT 0
348#define ALERT_HANDLER_ALERT_REGWEN_42_REG_OFFSET 0xc0
349#define ALERT_HANDLER_ALERT_REGWEN_42_REG_RESVAL 0x1u
350#define ALERT_HANDLER_ALERT_REGWEN_42_EN_42_BIT 0
353#define ALERT_HANDLER_ALERT_REGWEN_43_REG_OFFSET 0xc4
354#define ALERT_HANDLER_ALERT_REGWEN_43_REG_RESVAL 0x1u
355#define ALERT_HANDLER_ALERT_REGWEN_43_EN_43_BIT 0
358#define ALERT_HANDLER_ALERT_REGWEN_44_REG_OFFSET 0xc8
359#define ALERT_HANDLER_ALERT_REGWEN_44_REG_RESVAL 0x1u
360#define ALERT_HANDLER_ALERT_REGWEN_44_EN_44_BIT 0
363#define ALERT_HANDLER_ALERT_REGWEN_45_REG_OFFSET 0xcc
364#define ALERT_HANDLER_ALERT_REGWEN_45_REG_RESVAL 0x1u
365#define ALERT_HANDLER_ALERT_REGWEN_45_EN_45_BIT 0
368#define ALERT_HANDLER_ALERT_REGWEN_46_REG_OFFSET 0xd0
369#define ALERT_HANDLER_ALERT_REGWEN_46_REG_RESVAL 0x1u
370#define ALERT_HANDLER_ALERT_REGWEN_46_EN_46_BIT 0
373#define ALERT_HANDLER_ALERT_REGWEN_47_REG_OFFSET 0xd4
374#define ALERT_HANDLER_ALERT_REGWEN_47_REG_RESVAL 0x1u
375#define ALERT_HANDLER_ALERT_REGWEN_47_EN_47_BIT 0
378#define ALERT_HANDLER_ALERT_REGWEN_48_REG_OFFSET 0xd8
379#define ALERT_HANDLER_ALERT_REGWEN_48_REG_RESVAL 0x1u
380#define ALERT_HANDLER_ALERT_REGWEN_48_EN_48_BIT 0
383#define ALERT_HANDLER_ALERT_REGWEN_49_REG_OFFSET 0xdc
384#define ALERT_HANDLER_ALERT_REGWEN_49_REG_RESVAL 0x1u
385#define ALERT_HANDLER_ALERT_REGWEN_49_EN_49_BIT 0
388#define ALERT_HANDLER_ALERT_REGWEN_50_REG_OFFSET 0xe0
389#define ALERT_HANDLER_ALERT_REGWEN_50_REG_RESVAL 0x1u
390#define ALERT_HANDLER_ALERT_REGWEN_50_EN_50_BIT 0
393#define ALERT_HANDLER_ALERT_REGWEN_51_REG_OFFSET 0xe4
394#define ALERT_HANDLER_ALERT_REGWEN_51_REG_RESVAL 0x1u
395#define ALERT_HANDLER_ALERT_REGWEN_51_EN_51_BIT 0
398#define ALERT_HANDLER_ALERT_REGWEN_52_REG_OFFSET 0xe8
399#define ALERT_HANDLER_ALERT_REGWEN_52_REG_RESVAL 0x1u
400#define ALERT_HANDLER_ALERT_REGWEN_52_EN_52_BIT 0
403#define ALERT_HANDLER_ALERT_REGWEN_53_REG_OFFSET 0xec
404#define ALERT_HANDLER_ALERT_REGWEN_53_REG_RESVAL 0x1u
405#define ALERT_HANDLER_ALERT_REGWEN_53_EN_53_BIT 0
408#define ALERT_HANDLER_ALERT_REGWEN_54_REG_OFFSET 0xf0
409#define ALERT_HANDLER_ALERT_REGWEN_54_REG_RESVAL 0x1u
410#define ALERT_HANDLER_ALERT_REGWEN_54_EN_54_BIT 0
413#define ALERT_HANDLER_ALERT_REGWEN_55_REG_OFFSET 0xf4
414#define ALERT_HANDLER_ALERT_REGWEN_55_REG_RESVAL 0x1u
415#define ALERT_HANDLER_ALERT_REGWEN_55_EN_55_BIT 0
418#define ALERT_HANDLER_ALERT_REGWEN_56_REG_OFFSET 0xf8
419#define ALERT_HANDLER_ALERT_REGWEN_56_REG_RESVAL 0x1u
420#define ALERT_HANDLER_ALERT_REGWEN_56_EN_56_BIT 0
423#define ALERT_HANDLER_ALERT_REGWEN_57_REG_OFFSET 0xfc
424#define ALERT_HANDLER_ALERT_REGWEN_57_REG_RESVAL 0x1u
425#define ALERT_HANDLER_ALERT_REGWEN_57_EN_57_BIT 0
428#define ALERT_HANDLER_ALERT_REGWEN_58_REG_OFFSET 0x100
429#define ALERT_HANDLER_ALERT_REGWEN_58_REG_RESVAL 0x1u
430#define ALERT_HANDLER_ALERT_REGWEN_58_EN_58_BIT 0
433#define ALERT_HANDLER_ALERT_REGWEN_59_REG_OFFSET 0x104
434#define ALERT_HANDLER_ALERT_REGWEN_59_REG_RESVAL 0x1u
435#define ALERT_HANDLER_ALERT_REGWEN_59_EN_59_BIT 0
438#define ALERT_HANDLER_ALERT_REGWEN_60_REG_OFFSET 0x108
439#define ALERT_HANDLER_ALERT_REGWEN_60_REG_RESVAL 0x1u
440#define ALERT_HANDLER_ALERT_REGWEN_60_EN_60_BIT 0
443#define ALERT_HANDLER_ALERT_REGWEN_61_REG_OFFSET 0x10c
444#define ALERT_HANDLER_ALERT_REGWEN_61_REG_RESVAL 0x1u
445#define ALERT_HANDLER_ALERT_REGWEN_61_EN_61_BIT 0
448#define ALERT_HANDLER_ALERT_REGWEN_62_REG_OFFSET 0x110
449#define ALERT_HANDLER_ALERT_REGWEN_62_REG_RESVAL 0x1u
450#define ALERT_HANDLER_ALERT_REGWEN_62_EN_62_BIT 0
453#define ALERT_HANDLER_ALERT_REGWEN_63_REG_OFFSET 0x114
454#define ALERT_HANDLER_ALERT_REGWEN_63_REG_RESVAL 0x1u
455#define ALERT_HANDLER_ALERT_REGWEN_63_EN_63_BIT 0
458#define ALERT_HANDLER_ALERT_REGWEN_64_REG_OFFSET 0x118
459#define ALERT_HANDLER_ALERT_REGWEN_64_REG_RESVAL 0x1u
460#define ALERT_HANDLER_ALERT_REGWEN_64_EN_64_BIT 0
463#define ALERT_HANDLER_ALERT_REGWEN_65_REG_OFFSET 0x11c
464#define ALERT_HANDLER_ALERT_REGWEN_65_REG_RESVAL 0x1u
465#define ALERT_HANDLER_ALERT_REGWEN_65_EN_65_BIT 0
468#define ALERT_HANDLER_ALERT_REGWEN_66_REG_OFFSET 0x120
469#define ALERT_HANDLER_ALERT_REGWEN_66_REG_RESVAL 0x1u
470#define ALERT_HANDLER_ALERT_REGWEN_66_EN_66_BIT 0
473#define ALERT_HANDLER_ALERT_REGWEN_67_REG_OFFSET 0x124
474#define ALERT_HANDLER_ALERT_REGWEN_67_REG_RESVAL 0x1u
475#define ALERT_HANDLER_ALERT_REGWEN_67_EN_67_BIT 0
478#define ALERT_HANDLER_ALERT_REGWEN_68_REG_OFFSET 0x128
479#define ALERT_HANDLER_ALERT_REGWEN_68_REG_RESVAL 0x1u
480#define ALERT_HANDLER_ALERT_REGWEN_68_EN_68_BIT 0
483#define ALERT_HANDLER_ALERT_REGWEN_69_REG_OFFSET 0x12c
484#define ALERT_HANDLER_ALERT_REGWEN_69_REG_RESVAL 0x1u
485#define ALERT_HANDLER_ALERT_REGWEN_69_EN_69_BIT 0
488#define ALERT_HANDLER_ALERT_REGWEN_70_REG_OFFSET 0x130
489#define ALERT_HANDLER_ALERT_REGWEN_70_REG_RESVAL 0x1u
490#define ALERT_HANDLER_ALERT_REGWEN_70_EN_70_BIT 0
493#define ALERT_HANDLER_ALERT_REGWEN_71_REG_OFFSET 0x134
494#define ALERT_HANDLER_ALERT_REGWEN_71_REG_RESVAL 0x1u
495#define ALERT_HANDLER_ALERT_REGWEN_71_EN_71_BIT 0
498#define ALERT_HANDLER_ALERT_REGWEN_72_REG_OFFSET 0x138
499#define ALERT_HANDLER_ALERT_REGWEN_72_REG_RESVAL 0x1u
500#define ALERT_HANDLER_ALERT_REGWEN_72_EN_72_BIT 0
503#define ALERT_HANDLER_ALERT_REGWEN_73_REG_OFFSET 0x13c
504#define ALERT_HANDLER_ALERT_REGWEN_73_REG_RESVAL 0x1u
505#define ALERT_HANDLER_ALERT_REGWEN_73_EN_73_BIT 0
508#define ALERT_HANDLER_ALERT_REGWEN_74_REG_OFFSET 0x140
509#define ALERT_HANDLER_ALERT_REGWEN_74_REG_RESVAL 0x1u
510#define ALERT_HANDLER_ALERT_REGWEN_74_EN_74_BIT 0
513#define ALERT_HANDLER_ALERT_REGWEN_75_REG_OFFSET 0x144
514#define ALERT_HANDLER_ALERT_REGWEN_75_REG_RESVAL 0x1u
515#define ALERT_HANDLER_ALERT_REGWEN_75_EN_75_BIT 0
518#define ALERT_HANDLER_ALERT_REGWEN_76_REG_OFFSET 0x148
519#define ALERT_HANDLER_ALERT_REGWEN_76_REG_RESVAL 0x1u
520#define ALERT_HANDLER_ALERT_REGWEN_76_EN_76_BIT 0
523#define ALERT_HANDLER_ALERT_REGWEN_77_REG_OFFSET 0x14c
524#define ALERT_HANDLER_ALERT_REGWEN_77_REG_RESVAL 0x1u
525#define ALERT_HANDLER_ALERT_REGWEN_77_EN_77_BIT 0
528#define ALERT_HANDLER_ALERT_REGWEN_78_REG_OFFSET 0x150
529#define ALERT_HANDLER_ALERT_REGWEN_78_REG_RESVAL 0x1u
530#define ALERT_HANDLER_ALERT_REGWEN_78_EN_78_BIT 0
533#define ALERT_HANDLER_ALERT_REGWEN_79_REG_OFFSET 0x154
534#define ALERT_HANDLER_ALERT_REGWEN_79_REG_RESVAL 0x1u
535#define ALERT_HANDLER_ALERT_REGWEN_79_EN_79_BIT 0
538#define ALERT_HANDLER_ALERT_REGWEN_80_REG_OFFSET 0x158
539#define ALERT_HANDLER_ALERT_REGWEN_80_REG_RESVAL 0x1u
540#define ALERT_HANDLER_ALERT_REGWEN_80_EN_80_BIT 0
543#define ALERT_HANDLER_ALERT_REGWEN_81_REG_OFFSET 0x15c
544#define ALERT_HANDLER_ALERT_REGWEN_81_REG_RESVAL 0x1u
545#define ALERT_HANDLER_ALERT_REGWEN_81_EN_81_BIT 0
548#define ALERT_HANDLER_ALERT_REGWEN_82_REG_OFFSET 0x160
549#define ALERT_HANDLER_ALERT_REGWEN_82_REG_RESVAL 0x1u
550#define ALERT_HANDLER_ALERT_REGWEN_82_EN_82_BIT 0
553#define ALERT_HANDLER_ALERT_REGWEN_83_REG_OFFSET 0x164
554#define ALERT_HANDLER_ALERT_REGWEN_83_REG_RESVAL 0x1u
555#define ALERT_HANDLER_ALERT_REGWEN_83_EN_83_BIT 0
558#define ALERT_HANDLER_ALERT_REGWEN_84_REG_OFFSET 0x168
559#define ALERT_HANDLER_ALERT_REGWEN_84_REG_RESVAL 0x1u
560#define ALERT_HANDLER_ALERT_REGWEN_84_EN_84_BIT 0
563#define ALERT_HANDLER_ALERT_REGWEN_85_REG_OFFSET 0x16c
564#define ALERT_HANDLER_ALERT_REGWEN_85_REG_RESVAL 0x1u
565#define ALERT_HANDLER_ALERT_REGWEN_85_EN_85_BIT 0
568#define ALERT_HANDLER_ALERT_REGWEN_86_REG_OFFSET 0x170
569#define ALERT_HANDLER_ALERT_REGWEN_86_REG_RESVAL 0x1u
570#define ALERT_HANDLER_ALERT_REGWEN_86_EN_86_BIT 0
573#define ALERT_HANDLER_ALERT_REGWEN_87_REG_OFFSET 0x174
574#define ALERT_HANDLER_ALERT_REGWEN_87_REG_RESVAL 0x1u
575#define ALERT_HANDLER_ALERT_REGWEN_87_EN_87_BIT 0
578#define ALERT_HANDLER_ALERT_REGWEN_88_REG_OFFSET 0x178
579#define ALERT_HANDLER_ALERT_REGWEN_88_REG_RESVAL 0x1u
580#define ALERT_HANDLER_ALERT_REGWEN_88_EN_88_BIT 0
583#define ALERT_HANDLER_ALERT_REGWEN_89_REG_OFFSET 0x17c
584#define ALERT_HANDLER_ALERT_REGWEN_89_REG_RESVAL 0x1u
585#define ALERT_HANDLER_ALERT_REGWEN_89_EN_89_BIT 0
588#define ALERT_HANDLER_ALERT_REGWEN_90_REG_OFFSET 0x180
589#define ALERT_HANDLER_ALERT_REGWEN_90_REG_RESVAL 0x1u
590#define ALERT_HANDLER_ALERT_REGWEN_90_EN_90_BIT 0
593#define ALERT_HANDLER_ALERT_REGWEN_91_REG_OFFSET 0x184
594#define ALERT_HANDLER_ALERT_REGWEN_91_REG_RESVAL 0x1u
595#define ALERT_HANDLER_ALERT_REGWEN_91_EN_91_BIT 0
598#define ALERT_HANDLER_ALERT_REGWEN_92_REG_OFFSET 0x188
599#define ALERT_HANDLER_ALERT_REGWEN_92_REG_RESVAL 0x1u
600#define ALERT_HANDLER_ALERT_REGWEN_92_EN_92_BIT 0
603#define ALERT_HANDLER_ALERT_REGWEN_93_REG_OFFSET 0x18c
604#define ALERT_HANDLER_ALERT_REGWEN_93_REG_RESVAL 0x1u
605#define ALERT_HANDLER_ALERT_REGWEN_93_EN_93_BIT 0
608#define ALERT_HANDLER_ALERT_REGWEN_94_REG_OFFSET 0x190
609#define ALERT_HANDLER_ALERT_REGWEN_94_REG_RESVAL 0x1u
610#define ALERT_HANDLER_ALERT_REGWEN_94_EN_94_BIT 0
613#define ALERT_HANDLER_ALERT_REGWEN_95_REG_OFFSET 0x194
614#define ALERT_HANDLER_ALERT_REGWEN_95_REG_RESVAL 0x1u
615#define ALERT_HANDLER_ALERT_REGWEN_95_EN_95_BIT 0
618#define ALERT_HANDLER_ALERT_REGWEN_96_REG_OFFSET 0x198
619#define ALERT_HANDLER_ALERT_REGWEN_96_REG_RESVAL 0x1u
620#define ALERT_HANDLER_ALERT_REGWEN_96_EN_96_BIT 0
623#define ALERT_HANDLER_ALERT_REGWEN_97_REG_OFFSET 0x19c
624#define ALERT_HANDLER_ALERT_REGWEN_97_REG_RESVAL 0x1u
625#define ALERT_HANDLER_ALERT_REGWEN_97_EN_97_BIT 0
628#define ALERT_HANDLER_ALERT_REGWEN_98_REG_OFFSET 0x1a0
629#define ALERT_HANDLER_ALERT_REGWEN_98_REG_RESVAL 0x1u
630#define ALERT_HANDLER_ALERT_REGWEN_98_EN_98_BIT 0
633#define ALERT_HANDLER_ALERT_REGWEN_99_REG_OFFSET 0x1a4
634#define ALERT_HANDLER_ALERT_REGWEN_99_REG_RESVAL 0x1u
635#define ALERT_HANDLER_ALERT_REGWEN_99_EN_99_BIT 0
638#define ALERT_HANDLER_ALERT_REGWEN_100_REG_OFFSET 0x1a8
639#define ALERT_HANDLER_ALERT_REGWEN_100_REG_RESVAL 0x1u
640#define ALERT_HANDLER_ALERT_REGWEN_100_EN_100_BIT 0
643#define ALERT_HANDLER_ALERT_REGWEN_101_REG_OFFSET 0x1ac
644#define ALERT_HANDLER_ALERT_REGWEN_101_REG_RESVAL 0x1u
645#define ALERT_HANDLER_ALERT_REGWEN_101_EN_101_BIT 0
648#define ALERT_HANDLER_ALERT_REGWEN_102_REG_OFFSET 0x1b0
649#define ALERT_HANDLER_ALERT_REGWEN_102_REG_RESVAL 0x1u
650#define ALERT_HANDLER_ALERT_REGWEN_102_EN_102_BIT 0
653#define ALERT_HANDLER_ALERT_REGWEN_103_REG_OFFSET 0x1b4
654#define ALERT_HANDLER_ALERT_REGWEN_103_REG_RESVAL 0x1u
655#define ALERT_HANDLER_ALERT_REGWEN_103_EN_103_BIT 0
658#define ALERT_HANDLER_ALERT_REGWEN_104_REG_OFFSET 0x1b8
659#define ALERT_HANDLER_ALERT_REGWEN_104_REG_RESVAL 0x1u
660#define ALERT_HANDLER_ALERT_REGWEN_104_EN_104_BIT 0
663#define ALERT_HANDLER_ALERT_EN_SHADOWED_EN_A_FIELD_WIDTH 1
664#define ALERT_HANDLER_ALERT_EN_SHADOWED_MULTIREG_COUNT 105
667#define ALERT_HANDLER_ALERT_EN_SHADOWED_0_REG_OFFSET 0x1bc
668#define ALERT_HANDLER_ALERT_EN_SHADOWED_0_REG_RESVAL 0x0u
669#define ALERT_HANDLER_ALERT_EN_SHADOWED_0_EN_A_0_BIT 0
672#define ALERT_HANDLER_ALERT_EN_SHADOWED_1_REG_OFFSET 0x1c0
673#define ALERT_HANDLER_ALERT_EN_SHADOWED_1_REG_RESVAL 0x0u
674#define ALERT_HANDLER_ALERT_EN_SHADOWED_1_EN_A_1_BIT 0
677#define ALERT_HANDLER_ALERT_EN_SHADOWED_2_REG_OFFSET 0x1c4
678#define ALERT_HANDLER_ALERT_EN_SHADOWED_2_REG_RESVAL 0x0u
679#define ALERT_HANDLER_ALERT_EN_SHADOWED_2_EN_A_2_BIT 0
682#define ALERT_HANDLER_ALERT_EN_SHADOWED_3_REG_OFFSET 0x1c8
683#define ALERT_HANDLER_ALERT_EN_SHADOWED_3_REG_RESVAL 0x0u
684#define ALERT_HANDLER_ALERT_EN_SHADOWED_3_EN_A_3_BIT 0
687#define ALERT_HANDLER_ALERT_EN_SHADOWED_4_REG_OFFSET 0x1cc
688#define ALERT_HANDLER_ALERT_EN_SHADOWED_4_REG_RESVAL 0x0u
689#define ALERT_HANDLER_ALERT_EN_SHADOWED_4_EN_A_4_BIT 0
692#define ALERT_HANDLER_ALERT_EN_SHADOWED_5_REG_OFFSET 0x1d0
693#define ALERT_HANDLER_ALERT_EN_SHADOWED_5_REG_RESVAL 0x0u
694#define ALERT_HANDLER_ALERT_EN_SHADOWED_5_EN_A_5_BIT 0
697#define ALERT_HANDLER_ALERT_EN_SHADOWED_6_REG_OFFSET 0x1d4
698#define ALERT_HANDLER_ALERT_EN_SHADOWED_6_REG_RESVAL 0x0u
699#define ALERT_HANDLER_ALERT_EN_SHADOWED_6_EN_A_6_BIT 0
702#define ALERT_HANDLER_ALERT_EN_SHADOWED_7_REG_OFFSET 0x1d8
703#define ALERT_HANDLER_ALERT_EN_SHADOWED_7_REG_RESVAL 0x0u
704#define ALERT_HANDLER_ALERT_EN_SHADOWED_7_EN_A_7_BIT 0
707#define ALERT_HANDLER_ALERT_EN_SHADOWED_8_REG_OFFSET 0x1dc
708#define ALERT_HANDLER_ALERT_EN_SHADOWED_8_REG_RESVAL 0x0u
709#define ALERT_HANDLER_ALERT_EN_SHADOWED_8_EN_A_8_BIT 0
712#define ALERT_HANDLER_ALERT_EN_SHADOWED_9_REG_OFFSET 0x1e0
713#define ALERT_HANDLER_ALERT_EN_SHADOWED_9_REG_RESVAL 0x0u
714#define ALERT_HANDLER_ALERT_EN_SHADOWED_9_EN_A_9_BIT 0
717#define ALERT_HANDLER_ALERT_EN_SHADOWED_10_REG_OFFSET 0x1e4
718#define ALERT_HANDLER_ALERT_EN_SHADOWED_10_REG_RESVAL 0x0u
719#define ALERT_HANDLER_ALERT_EN_SHADOWED_10_EN_A_10_BIT 0
722#define ALERT_HANDLER_ALERT_EN_SHADOWED_11_REG_OFFSET 0x1e8
723#define ALERT_HANDLER_ALERT_EN_SHADOWED_11_REG_RESVAL 0x0u
724#define ALERT_HANDLER_ALERT_EN_SHADOWED_11_EN_A_11_BIT 0
727#define ALERT_HANDLER_ALERT_EN_SHADOWED_12_REG_OFFSET 0x1ec
728#define ALERT_HANDLER_ALERT_EN_SHADOWED_12_REG_RESVAL 0x0u
729#define ALERT_HANDLER_ALERT_EN_SHADOWED_12_EN_A_12_BIT 0
732#define ALERT_HANDLER_ALERT_EN_SHADOWED_13_REG_OFFSET 0x1f0
733#define ALERT_HANDLER_ALERT_EN_SHADOWED_13_REG_RESVAL 0x0u
734#define ALERT_HANDLER_ALERT_EN_SHADOWED_13_EN_A_13_BIT 0
737#define ALERT_HANDLER_ALERT_EN_SHADOWED_14_REG_OFFSET 0x1f4
738#define ALERT_HANDLER_ALERT_EN_SHADOWED_14_REG_RESVAL 0x0u
739#define ALERT_HANDLER_ALERT_EN_SHADOWED_14_EN_A_14_BIT 0
742#define ALERT_HANDLER_ALERT_EN_SHADOWED_15_REG_OFFSET 0x1f8
743#define ALERT_HANDLER_ALERT_EN_SHADOWED_15_REG_RESVAL 0x0u
744#define ALERT_HANDLER_ALERT_EN_SHADOWED_15_EN_A_15_BIT 0
747#define ALERT_HANDLER_ALERT_EN_SHADOWED_16_REG_OFFSET 0x1fc
748#define ALERT_HANDLER_ALERT_EN_SHADOWED_16_REG_RESVAL 0x0u
749#define ALERT_HANDLER_ALERT_EN_SHADOWED_16_EN_A_16_BIT 0
752#define ALERT_HANDLER_ALERT_EN_SHADOWED_17_REG_OFFSET 0x200
753#define ALERT_HANDLER_ALERT_EN_SHADOWED_17_REG_RESVAL 0x0u
754#define ALERT_HANDLER_ALERT_EN_SHADOWED_17_EN_A_17_BIT 0
757#define ALERT_HANDLER_ALERT_EN_SHADOWED_18_REG_OFFSET 0x204
758#define ALERT_HANDLER_ALERT_EN_SHADOWED_18_REG_RESVAL 0x0u
759#define ALERT_HANDLER_ALERT_EN_SHADOWED_18_EN_A_18_BIT 0
762#define ALERT_HANDLER_ALERT_EN_SHADOWED_19_REG_OFFSET 0x208
763#define ALERT_HANDLER_ALERT_EN_SHADOWED_19_REG_RESVAL 0x0u
764#define ALERT_HANDLER_ALERT_EN_SHADOWED_19_EN_A_19_BIT 0
767#define ALERT_HANDLER_ALERT_EN_SHADOWED_20_REG_OFFSET 0x20c
768#define ALERT_HANDLER_ALERT_EN_SHADOWED_20_REG_RESVAL 0x0u
769#define ALERT_HANDLER_ALERT_EN_SHADOWED_20_EN_A_20_BIT 0
772#define ALERT_HANDLER_ALERT_EN_SHADOWED_21_REG_OFFSET 0x210
773#define ALERT_HANDLER_ALERT_EN_SHADOWED_21_REG_RESVAL 0x0u
774#define ALERT_HANDLER_ALERT_EN_SHADOWED_21_EN_A_21_BIT 0
777#define ALERT_HANDLER_ALERT_EN_SHADOWED_22_REG_OFFSET 0x214
778#define ALERT_HANDLER_ALERT_EN_SHADOWED_22_REG_RESVAL 0x0u
779#define ALERT_HANDLER_ALERT_EN_SHADOWED_22_EN_A_22_BIT 0
782#define ALERT_HANDLER_ALERT_EN_SHADOWED_23_REG_OFFSET 0x218
783#define ALERT_HANDLER_ALERT_EN_SHADOWED_23_REG_RESVAL 0x0u
784#define ALERT_HANDLER_ALERT_EN_SHADOWED_23_EN_A_23_BIT 0
787#define ALERT_HANDLER_ALERT_EN_SHADOWED_24_REG_OFFSET 0x21c
788#define ALERT_HANDLER_ALERT_EN_SHADOWED_24_REG_RESVAL 0x0u
789#define ALERT_HANDLER_ALERT_EN_SHADOWED_24_EN_A_24_BIT 0
792#define ALERT_HANDLER_ALERT_EN_SHADOWED_25_REG_OFFSET 0x220
793#define ALERT_HANDLER_ALERT_EN_SHADOWED_25_REG_RESVAL 0x0u
794#define ALERT_HANDLER_ALERT_EN_SHADOWED_25_EN_A_25_BIT 0
797#define ALERT_HANDLER_ALERT_EN_SHADOWED_26_REG_OFFSET 0x224
798#define ALERT_HANDLER_ALERT_EN_SHADOWED_26_REG_RESVAL 0x0u
799#define ALERT_HANDLER_ALERT_EN_SHADOWED_26_EN_A_26_BIT 0
802#define ALERT_HANDLER_ALERT_EN_SHADOWED_27_REG_OFFSET 0x228
803#define ALERT_HANDLER_ALERT_EN_SHADOWED_27_REG_RESVAL 0x0u
804#define ALERT_HANDLER_ALERT_EN_SHADOWED_27_EN_A_27_BIT 0
807#define ALERT_HANDLER_ALERT_EN_SHADOWED_28_REG_OFFSET 0x22c
808#define ALERT_HANDLER_ALERT_EN_SHADOWED_28_REG_RESVAL 0x0u
809#define ALERT_HANDLER_ALERT_EN_SHADOWED_28_EN_A_28_BIT 0
812#define ALERT_HANDLER_ALERT_EN_SHADOWED_29_REG_OFFSET 0x230
813#define ALERT_HANDLER_ALERT_EN_SHADOWED_29_REG_RESVAL 0x0u
814#define ALERT_HANDLER_ALERT_EN_SHADOWED_29_EN_A_29_BIT 0
817#define ALERT_HANDLER_ALERT_EN_SHADOWED_30_REG_OFFSET 0x234
818#define ALERT_HANDLER_ALERT_EN_SHADOWED_30_REG_RESVAL 0x0u
819#define ALERT_HANDLER_ALERT_EN_SHADOWED_30_EN_A_30_BIT 0
822#define ALERT_HANDLER_ALERT_EN_SHADOWED_31_REG_OFFSET 0x238
823#define ALERT_HANDLER_ALERT_EN_SHADOWED_31_REG_RESVAL 0x0u
824#define ALERT_HANDLER_ALERT_EN_SHADOWED_31_EN_A_31_BIT 0
827#define ALERT_HANDLER_ALERT_EN_SHADOWED_32_REG_OFFSET 0x23c
828#define ALERT_HANDLER_ALERT_EN_SHADOWED_32_REG_RESVAL 0x0u
829#define ALERT_HANDLER_ALERT_EN_SHADOWED_32_EN_A_32_BIT 0
832#define ALERT_HANDLER_ALERT_EN_SHADOWED_33_REG_OFFSET 0x240
833#define ALERT_HANDLER_ALERT_EN_SHADOWED_33_REG_RESVAL 0x0u
834#define ALERT_HANDLER_ALERT_EN_SHADOWED_33_EN_A_33_BIT 0
837#define ALERT_HANDLER_ALERT_EN_SHADOWED_34_REG_OFFSET 0x244
838#define ALERT_HANDLER_ALERT_EN_SHADOWED_34_REG_RESVAL 0x0u
839#define ALERT_HANDLER_ALERT_EN_SHADOWED_34_EN_A_34_BIT 0
842#define ALERT_HANDLER_ALERT_EN_SHADOWED_35_REG_OFFSET 0x248
843#define ALERT_HANDLER_ALERT_EN_SHADOWED_35_REG_RESVAL 0x0u
844#define ALERT_HANDLER_ALERT_EN_SHADOWED_35_EN_A_35_BIT 0
847#define ALERT_HANDLER_ALERT_EN_SHADOWED_36_REG_OFFSET 0x24c
848#define ALERT_HANDLER_ALERT_EN_SHADOWED_36_REG_RESVAL 0x0u
849#define ALERT_HANDLER_ALERT_EN_SHADOWED_36_EN_A_36_BIT 0
852#define ALERT_HANDLER_ALERT_EN_SHADOWED_37_REG_OFFSET 0x250
853#define ALERT_HANDLER_ALERT_EN_SHADOWED_37_REG_RESVAL 0x0u
854#define ALERT_HANDLER_ALERT_EN_SHADOWED_37_EN_A_37_BIT 0
857#define ALERT_HANDLER_ALERT_EN_SHADOWED_38_REG_OFFSET 0x254
858#define ALERT_HANDLER_ALERT_EN_SHADOWED_38_REG_RESVAL 0x0u
859#define ALERT_HANDLER_ALERT_EN_SHADOWED_38_EN_A_38_BIT 0
862#define ALERT_HANDLER_ALERT_EN_SHADOWED_39_REG_OFFSET 0x258
863#define ALERT_HANDLER_ALERT_EN_SHADOWED_39_REG_RESVAL 0x0u
864#define ALERT_HANDLER_ALERT_EN_SHADOWED_39_EN_A_39_BIT 0
867#define ALERT_HANDLER_ALERT_EN_SHADOWED_40_REG_OFFSET 0x25c
868#define ALERT_HANDLER_ALERT_EN_SHADOWED_40_REG_RESVAL 0x0u
869#define ALERT_HANDLER_ALERT_EN_SHADOWED_40_EN_A_40_BIT 0
872#define ALERT_HANDLER_ALERT_EN_SHADOWED_41_REG_OFFSET 0x260
873#define ALERT_HANDLER_ALERT_EN_SHADOWED_41_REG_RESVAL 0x0u
874#define ALERT_HANDLER_ALERT_EN_SHADOWED_41_EN_A_41_BIT 0
877#define ALERT_HANDLER_ALERT_EN_SHADOWED_42_REG_OFFSET 0x264
878#define ALERT_HANDLER_ALERT_EN_SHADOWED_42_REG_RESVAL 0x0u
879#define ALERT_HANDLER_ALERT_EN_SHADOWED_42_EN_A_42_BIT 0
882#define ALERT_HANDLER_ALERT_EN_SHADOWED_43_REG_OFFSET 0x268
883#define ALERT_HANDLER_ALERT_EN_SHADOWED_43_REG_RESVAL 0x0u
884#define ALERT_HANDLER_ALERT_EN_SHADOWED_43_EN_A_43_BIT 0
887#define ALERT_HANDLER_ALERT_EN_SHADOWED_44_REG_OFFSET 0x26c
888#define ALERT_HANDLER_ALERT_EN_SHADOWED_44_REG_RESVAL 0x0u
889#define ALERT_HANDLER_ALERT_EN_SHADOWED_44_EN_A_44_BIT 0
892#define ALERT_HANDLER_ALERT_EN_SHADOWED_45_REG_OFFSET 0x270
893#define ALERT_HANDLER_ALERT_EN_SHADOWED_45_REG_RESVAL 0x0u
894#define ALERT_HANDLER_ALERT_EN_SHADOWED_45_EN_A_45_BIT 0
897#define ALERT_HANDLER_ALERT_EN_SHADOWED_46_REG_OFFSET 0x274
898#define ALERT_HANDLER_ALERT_EN_SHADOWED_46_REG_RESVAL 0x0u
899#define ALERT_HANDLER_ALERT_EN_SHADOWED_46_EN_A_46_BIT 0
902#define ALERT_HANDLER_ALERT_EN_SHADOWED_47_REG_OFFSET 0x278
903#define ALERT_HANDLER_ALERT_EN_SHADOWED_47_REG_RESVAL 0x0u
904#define ALERT_HANDLER_ALERT_EN_SHADOWED_47_EN_A_47_BIT 0
907#define ALERT_HANDLER_ALERT_EN_SHADOWED_48_REG_OFFSET 0x27c
908#define ALERT_HANDLER_ALERT_EN_SHADOWED_48_REG_RESVAL 0x0u
909#define ALERT_HANDLER_ALERT_EN_SHADOWED_48_EN_A_48_BIT 0
912#define ALERT_HANDLER_ALERT_EN_SHADOWED_49_REG_OFFSET 0x280
913#define ALERT_HANDLER_ALERT_EN_SHADOWED_49_REG_RESVAL 0x0u
914#define ALERT_HANDLER_ALERT_EN_SHADOWED_49_EN_A_49_BIT 0
917#define ALERT_HANDLER_ALERT_EN_SHADOWED_50_REG_OFFSET 0x284
918#define ALERT_HANDLER_ALERT_EN_SHADOWED_50_REG_RESVAL 0x0u
919#define ALERT_HANDLER_ALERT_EN_SHADOWED_50_EN_A_50_BIT 0
922#define ALERT_HANDLER_ALERT_EN_SHADOWED_51_REG_OFFSET 0x288
923#define ALERT_HANDLER_ALERT_EN_SHADOWED_51_REG_RESVAL 0x0u
924#define ALERT_HANDLER_ALERT_EN_SHADOWED_51_EN_A_51_BIT 0
927#define ALERT_HANDLER_ALERT_EN_SHADOWED_52_REG_OFFSET 0x28c
928#define ALERT_HANDLER_ALERT_EN_SHADOWED_52_REG_RESVAL 0x0u
929#define ALERT_HANDLER_ALERT_EN_SHADOWED_52_EN_A_52_BIT 0
932#define ALERT_HANDLER_ALERT_EN_SHADOWED_53_REG_OFFSET 0x290
933#define ALERT_HANDLER_ALERT_EN_SHADOWED_53_REG_RESVAL 0x0u
934#define ALERT_HANDLER_ALERT_EN_SHADOWED_53_EN_A_53_BIT 0
937#define ALERT_HANDLER_ALERT_EN_SHADOWED_54_REG_OFFSET 0x294
938#define ALERT_HANDLER_ALERT_EN_SHADOWED_54_REG_RESVAL 0x0u
939#define ALERT_HANDLER_ALERT_EN_SHADOWED_54_EN_A_54_BIT 0
942#define ALERT_HANDLER_ALERT_EN_SHADOWED_55_REG_OFFSET 0x298
943#define ALERT_HANDLER_ALERT_EN_SHADOWED_55_REG_RESVAL 0x0u
944#define ALERT_HANDLER_ALERT_EN_SHADOWED_55_EN_A_55_BIT 0
947#define ALERT_HANDLER_ALERT_EN_SHADOWED_56_REG_OFFSET 0x29c
948#define ALERT_HANDLER_ALERT_EN_SHADOWED_56_REG_RESVAL 0x0u
949#define ALERT_HANDLER_ALERT_EN_SHADOWED_56_EN_A_56_BIT 0
952#define ALERT_HANDLER_ALERT_EN_SHADOWED_57_REG_OFFSET 0x2a0
953#define ALERT_HANDLER_ALERT_EN_SHADOWED_57_REG_RESVAL 0x0u
954#define ALERT_HANDLER_ALERT_EN_SHADOWED_57_EN_A_57_BIT 0
957#define ALERT_HANDLER_ALERT_EN_SHADOWED_58_REG_OFFSET 0x2a4
958#define ALERT_HANDLER_ALERT_EN_SHADOWED_58_REG_RESVAL 0x0u
959#define ALERT_HANDLER_ALERT_EN_SHADOWED_58_EN_A_58_BIT 0
962#define ALERT_HANDLER_ALERT_EN_SHADOWED_59_REG_OFFSET 0x2a8
963#define ALERT_HANDLER_ALERT_EN_SHADOWED_59_REG_RESVAL 0x0u
964#define ALERT_HANDLER_ALERT_EN_SHADOWED_59_EN_A_59_BIT 0
967#define ALERT_HANDLER_ALERT_EN_SHADOWED_60_REG_OFFSET 0x2ac
968#define ALERT_HANDLER_ALERT_EN_SHADOWED_60_REG_RESVAL 0x0u
969#define ALERT_HANDLER_ALERT_EN_SHADOWED_60_EN_A_60_BIT 0
972#define ALERT_HANDLER_ALERT_EN_SHADOWED_61_REG_OFFSET 0x2b0
973#define ALERT_HANDLER_ALERT_EN_SHADOWED_61_REG_RESVAL 0x0u
974#define ALERT_HANDLER_ALERT_EN_SHADOWED_61_EN_A_61_BIT 0
977#define ALERT_HANDLER_ALERT_EN_SHADOWED_62_REG_OFFSET 0x2b4
978#define ALERT_HANDLER_ALERT_EN_SHADOWED_62_REG_RESVAL 0x0u
979#define ALERT_HANDLER_ALERT_EN_SHADOWED_62_EN_A_62_BIT 0
982#define ALERT_HANDLER_ALERT_EN_SHADOWED_63_REG_OFFSET 0x2b8
983#define ALERT_HANDLER_ALERT_EN_SHADOWED_63_REG_RESVAL 0x0u
984#define ALERT_HANDLER_ALERT_EN_SHADOWED_63_EN_A_63_BIT 0
987#define ALERT_HANDLER_ALERT_EN_SHADOWED_64_REG_OFFSET 0x2bc
988#define ALERT_HANDLER_ALERT_EN_SHADOWED_64_REG_RESVAL 0x0u
989#define ALERT_HANDLER_ALERT_EN_SHADOWED_64_EN_A_64_BIT 0
992#define ALERT_HANDLER_ALERT_EN_SHADOWED_65_REG_OFFSET 0x2c0
993#define ALERT_HANDLER_ALERT_EN_SHADOWED_65_REG_RESVAL 0x0u
994#define ALERT_HANDLER_ALERT_EN_SHADOWED_65_EN_A_65_BIT 0
997#define ALERT_HANDLER_ALERT_EN_SHADOWED_66_REG_OFFSET 0x2c4
998#define ALERT_HANDLER_ALERT_EN_SHADOWED_66_REG_RESVAL 0x0u
999#define ALERT_HANDLER_ALERT_EN_SHADOWED_66_EN_A_66_BIT 0
1002#define ALERT_HANDLER_ALERT_EN_SHADOWED_67_REG_OFFSET 0x2c8
1003#define ALERT_HANDLER_ALERT_EN_SHADOWED_67_REG_RESVAL 0x0u
1004#define ALERT_HANDLER_ALERT_EN_SHADOWED_67_EN_A_67_BIT 0
1007#define ALERT_HANDLER_ALERT_EN_SHADOWED_68_REG_OFFSET 0x2cc
1008#define ALERT_HANDLER_ALERT_EN_SHADOWED_68_REG_RESVAL 0x0u
1009#define ALERT_HANDLER_ALERT_EN_SHADOWED_68_EN_A_68_BIT 0
1012#define ALERT_HANDLER_ALERT_EN_SHADOWED_69_REG_OFFSET 0x2d0
1013#define ALERT_HANDLER_ALERT_EN_SHADOWED_69_REG_RESVAL 0x0u
1014#define ALERT_HANDLER_ALERT_EN_SHADOWED_69_EN_A_69_BIT 0
1017#define ALERT_HANDLER_ALERT_EN_SHADOWED_70_REG_OFFSET 0x2d4
1018#define ALERT_HANDLER_ALERT_EN_SHADOWED_70_REG_RESVAL 0x0u
1019#define ALERT_HANDLER_ALERT_EN_SHADOWED_70_EN_A_70_BIT 0
1022#define ALERT_HANDLER_ALERT_EN_SHADOWED_71_REG_OFFSET 0x2d8
1023#define ALERT_HANDLER_ALERT_EN_SHADOWED_71_REG_RESVAL 0x0u
1024#define ALERT_HANDLER_ALERT_EN_SHADOWED_71_EN_A_71_BIT 0
1027#define ALERT_HANDLER_ALERT_EN_SHADOWED_72_REG_OFFSET 0x2dc
1028#define ALERT_HANDLER_ALERT_EN_SHADOWED_72_REG_RESVAL 0x0u
1029#define ALERT_HANDLER_ALERT_EN_SHADOWED_72_EN_A_72_BIT 0
1032#define ALERT_HANDLER_ALERT_EN_SHADOWED_73_REG_OFFSET 0x2e0
1033#define ALERT_HANDLER_ALERT_EN_SHADOWED_73_REG_RESVAL 0x0u
1034#define ALERT_HANDLER_ALERT_EN_SHADOWED_73_EN_A_73_BIT 0
1037#define ALERT_HANDLER_ALERT_EN_SHADOWED_74_REG_OFFSET 0x2e4
1038#define ALERT_HANDLER_ALERT_EN_SHADOWED_74_REG_RESVAL 0x0u
1039#define ALERT_HANDLER_ALERT_EN_SHADOWED_74_EN_A_74_BIT 0
1042#define ALERT_HANDLER_ALERT_EN_SHADOWED_75_REG_OFFSET 0x2e8
1043#define ALERT_HANDLER_ALERT_EN_SHADOWED_75_REG_RESVAL 0x0u
1044#define ALERT_HANDLER_ALERT_EN_SHADOWED_75_EN_A_75_BIT 0
1047#define ALERT_HANDLER_ALERT_EN_SHADOWED_76_REG_OFFSET 0x2ec
1048#define ALERT_HANDLER_ALERT_EN_SHADOWED_76_REG_RESVAL 0x0u
1049#define ALERT_HANDLER_ALERT_EN_SHADOWED_76_EN_A_76_BIT 0
1052#define ALERT_HANDLER_ALERT_EN_SHADOWED_77_REG_OFFSET 0x2f0
1053#define ALERT_HANDLER_ALERT_EN_SHADOWED_77_REG_RESVAL 0x0u
1054#define ALERT_HANDLER_ALERT_EN_SHADOWED_77_EN_A_77_BIT 0
1057#define ALERT_HANDLER_ALERT_EN_SHADOWED_78_REG_OFFSET 0x2f4
1058#define ALERT_HANDLER_ALERT_EN_SHADOWED_78_REG_RESVAL 0x0u
1059#define ALERT_HANDLER_ALERT_EN_SHADOWED_78_EN_A_78_BIT 0
1062#define ALERT_HANDLER_ALERT_EN_SHADOWED_79_REG_OFFSET 0x2f8
1063#define ALERT_HANDLER_ALERT_EN_SHADOWED_79_REG_RESVAL 0x0u
1064#define ALERT_HANDLER_ALERT_EN_SHADOWED_79_EN_A_79_BIT 0
1067#define ALERT_HANDLER_ALERT_EN_SHADOWED_80_REG_OFFSET 0x2fc
1068#define ALERT_HANDLER_ALERT_EN_SHADOWED_80_REG_RESVAL 0x0u
1069#define ALERT_HANDLER_ALERT_EN_SHADOWED_80_EN_A_80_BIT 0
1072#define ALERT_HANDLER_ALERT_EN_SHADOWED_81_REG_OFFSET 0x300
1073#define ALERT_HANDLER_ALERT_EN_SHADOWED_81_REG_RESVAL 0x0u
1074#define ALERT_HANDLER_ALERT_EN_SHADOWED_81_EN_A_81_BIT 0
1077#define ALERT_HANDLER_ALERT_EN_SHADOWED_82_REG_OFFSET 0x304
1078#define ALERT_HANDLER_ALERT_EN_SHADOWED_82_REG_RESVAL 0x0u
1079#define ALERT_HANDLER_ALERT_EN_SHADOWED_82_EN_A_82_BIT 0
1082#define ALERT_HANDLER_ALERT_EN_SHADOWED_83_REG_OFFSET 0x308
1083#define ALERT_HANDLER_ALERT_EN_SHADOWED_83_REG_RESVAL 0x0u
1084#define ALERT_HANDLER_ALERT_EN_SHADOWED_83_EN_A_83_BIT 0
1087#define ALERT_HANDLER_ALERT_EN_SHADOWED_84_REG_OFFSET 0x30c
1088#define ALERT_HANDLER_ALERT_EN_SHADOWED_84_REG_RESVAL 0x0u
1089#define ALERT_HANDLER_ALERT_EN_SHADOWED_84_EN_A_84_BIT 0
1092#define ALERT_HANDLER_ALERT_EN_SHADOWED_85_REG_OFFSET 0x310
1093#define ALERT_HANDLER_ALERT_EN_SHADOWED_85_REG_RESVAL 0x0u
1094#define ALERT_HANDLER_ALERT_EN_SHADOWED_85_EN_A_85_BIT 0
1097#define ALERT_HANDLER_ALERT_EN_SHADOWED_86_REG_OFFSET 0x314
1098#define ALERT_HANDLER_ALERT_EN_SHADOWED_86_REG_RESVAL 0x0u
1099#define ALERT_HANDLER_ALERT_EN_SHADOWED_86_EN_A_86_BIT 0
1102#define ALERT_HANDLER_ALERT_EN_SHADOWED_87_REG_OFFSET 0x318
1103#define ALERT_HANDLER_ALERT_EN_SHADOWED_87_REG_RESVAL 0x0u
1104#define ALERT_HANDLER_ALERT_EN_SHADOWED_87_EN_A_87_BIT 0
1107#define ALERT_HANDLER_ALERT_EN_SHADOWED_88_REG_OFFSET 0x31c
1108#define ALERT_HANDLER_ALERT_EN_SHADOWED_88_REG_RESVAL 0x0u
1109#define ALERT_HANDLER_ALERT_EN_SHADOWED_88_EN_A_88_BIT 0
1112#define ALERT_HANDLER_ALERT_EN_SHADOWED_89_REG_OFFSET 0x320
1113#define ALERT_HANDLER_ALERT_EN_SHADOWED_89_REG_RESVAL 0x0u
1114#define ALERT_HANDLER_ALERT_EN_SHADOWED_89_EN_A_89_BIT 0
1117#define ALERT_HANDLER_ALERT_EN_SHADOWED_90_REG_OFFSET 0x324
1118#define ALERT_HANDLER_ALERT_EN_SHADOWED_90_REG_RESVAL 0x0u
1119#define ALERT_HANDLER_ALERT_EN_SHADOWED_90_EN_A_90_BIT 0
1122#define ALERT_HANDLER_ALERT_EN_SHADOWED_91_REG_OFFSET 0x328
1123#define ALERT_HANDLER_ALERT_EN_SHADOWED_91_REG_RESVAL 0x0u
1124#define ALERT_HANDLER_ALERT_EN_SHADOWED_91_EN_A_91_BIT 0
1127#define ALERT_HANDLER_ALERT_EN_SHADOWED_92_REG_OFFSET 0x32c
1128#define ALERT_HANDLER_ALERT_EN_SHADOWED_92_REG_RESVAL 0x0u
1129#define ALERT_HANDLER_ALERT_EN_SHADOWED_92_EN_A_92_BIT 0
1132#define ALERT_HANDLER_ALERT_EN_SHADOWED_93_REG_OFFSET 0x330
1133#define ALERT_HANDLER_ALERT_EN_SHADOWED_93_REG_RESVAL 0x0u
1134#define ALERT_HANDLER_ALERT_EN_SHADOWED_93_EN_A_93_BIT 0
1137#define ALERT_HANDLER_ALERT_EN_SHADOWED_94_REG_OFFSET 0x334
1138#define ALERT_HANDLER_ALERT_EN_SHADOWED_94_REG_RESVAL 0x0u
1139#define ALERT_HANDLER_ALERT_EN_SHADOWED_94_EN_A_94_BIT 0
1142#define ALERT_HANDLER_ALERT_EN_SHADOWED_95_REG_OFFSET 0x338
1143#define ALERT_HANDLER_ALERT_EN_SHADOWED_95_REG_RESVAL 0x0u
1144#define ALERT_HANDLER_ALERT_EN_SHADOWED_95_EN_A_95_BIT 0
1147#define ALERT_HANDLER_ALERT_EN_SHADOWED_96_REG_OFFSET 0x33c
1148#define ALERT_HANDLER_ALERT_EN_SHADOWED_96_REG_RESVAL 0x0u
1149#define ALERT_HANDLER_ALERT_EN_SHADOWED_96_EN_A_96_BIT 0
1152#define ALERT_HANDLER_ALERT_EN_SHADOWED_97_REG_OFFSET 0x340
1153#define ALERT_HANDLER_ALERT_EN_SHADOWED_97_REG_RESVAL 0x0u
1154#define ALERT_HANDLER_ALERT_EN_SHADOWED_97_EN_A_97_BIT 0
1157#define ALERT_HANDLER_ALERT_EN_SHADOWED_98_REG_OFFSET 0x344
1158#define ALERT_HANDLER_ALERT_EN_SHADOWED_98_REG_RESVAL 0x0u
1159#define ALERT_HANDLER_ALERT_EN_SHADOWED_98_EN_A_98_BIT 0
1162#define ALERT_HANDLER_ALERT_EN_SHADOWED_99_REG_OFFSET 0x348
1163#define ALERT_HANDLER_ALERT_EN_SHADOWED_99_REG_RESVAL 0x0u
1164#define ALERT_HANDLER_ALERT_EN_SHADOWED_99_EN_A_99_BIT 0
1167#define ALERT_HANDLER_ALERT_EN_SHADOWED_100_REG_OFFSET 0x34c
1168#define ALERT_HANDLER_ALERT_EN_SHADOWED_100_REG_RESVAL 0x0u
1169#define ALERT_HANDLER_ALERT_EN_SHADOWED_100_EN_A_100_BIT 0
1172#define ALERT_HANDLER_ALERT_EN_SHADOWED_101_REG_OFFSET 0x350
1173#define ALERT_HANDLER_ALERT_EN_SHADOWED_101_REG_RESVAL 0x0u
1174#define ALERT_HANDLER_ALERT_EN_SHADOWED_101_EN_A_101_BIT 0
1177#define ALERT_HANDLER_ALERT_EN_SHADOWED_102_REG_OFFSET 0x354
1178#define ALERT_HANDLER_ALERT_EN_SHADOWED_102_REG_RESVAL 0x0u
1179#define ALERT_HANDLER_ALERT_EN_SHADOWED_102_EN_A_102_BIT 0
1182#define ALERT_HANDLER_ALERT_EN_SHADOWED_103_REG_OFFSET 0x358
1183#define ALERT_HANDLER_ALERT_EN_SHADOWED_103_REG_RESVAL 0x0u
1184#define ALERT_HANDLER_ALERT_EN_SHADOWED_103_EN_A_103_BIT 0
1187#define ALERT_HANDLER_ALERT_EN_SHADOWED_104_REG_OFFSET 0x35c
1188#define ALERT_HANDLER_ALERT_EN_SHADOWED_104_REG_RESVAL 0x0u
1189#define ALERT_HANDLER_ALERT_EN_SHADOWED_104_EN_A_104_BIT 0
1192#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_CLASS_A_FIELD_WIDTH 2
1193#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_MULTIREG_COUNT 105
1196#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_REG_OFFSET 0x360
1197#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_REG_RESVAL 0x0u
1198#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_MASK 0x3u
1199#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_OFFSET 0
1200#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_FIELD \
1201 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_OFFSET })
1202#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_VALUE_CLASSA 0x0
1203#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_VALUE_CLASSB 0x1
1204#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_VALUE_CLASSC 0x2
1205#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_VALUE_CLASSD 0x3
1208#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_REG_OFFSET 0x364
1209#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_REG_RESVAL 0x0u
1210#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_CLASS_A_1_MASK 0x3u
1211#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_CLASS_A_1_OFFSET 0
1212#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_CLASS_A_1_FIELD \
1213 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_CLASS_A_1_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_CLASS_A_1_OFFSET })
1216#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_REG_OFFSET 0x368
1217#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_REG_RESVAL 0x0u
1218#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_CLASS_A_2_MASK 0x3u
1219#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_CLASS_A_2_OFFSET 0
1220#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_CLASS_A_2_FIELD \
1221 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_CLASS_A_2_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_CLASS_A_2_OFFSET })
1224#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_REG_OFFSET 0x36c
1225#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_REG_RESVAL 0x0u
1226#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_CLASS_A_3_MASK 0x3u
1227#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_CLASS_A_3_OFFSET 0
1228#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_CLASS_A_3_FIELD \
1229 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_CLASS_A_3_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_CLASS_A_3_OFFSET })
1232#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_REG_OFFSET 0x370
1233#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_REG_RESVAL 0x0u
1234#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_CLASS_A_4_MASK 0x3u
1235#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_CLASS_A_4_OFFSET 0
1236#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_CLASS_A_4_FIELD \
1237 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_CLASS_A_4_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_CLASS_A_4_OFFSET })
1240#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_REG_OFFSET 0x374
1241#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_REG_RESVAL 0x0u
1242#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_CLASS_A_5_MASK 0x3u
1243#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_CLASS_A_5_OFFSET 0
1244#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_CLASS_A_5_FIELD \
1245 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_CLASS_A_5_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_CLASS_A_5_OFFSET })
1248#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_REG_OFFSET 0x378
1249#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_REG_RESVAL 0x0u
1250#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_CLASS_A_6_MASK 0x3u
1251#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_CLASS_A_6_OFFSET 0
1252#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_CLASS_A_6_FIELD \
1253 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_CLASS_A_6_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_CLASS_A_6_OFFSET })
1256#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_REG_OFFSET 0x37c
1257#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_REG_RESVAL 0x0u
1258#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_CLASS_A_7_MASK 0x3u
1259#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_CLASS_A_7_OFFSET 0
1260#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_CLASS_A_7_FIELD \
1261 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_CLASS_A_7_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_CLASS_A_7_OFFSET })
1264#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_REG_OFFSET 0x380
1265#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_REG_RESVAL 0x0u
1266#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_CLASS_A_8_MASK 0x3u
1267#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_CLASS_A_8_OFFSET 0
1268#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_CLASS_A_8_FIELD \
1269 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_CLASS_A_8_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_CLASS_A_8_OFFSET })
1272#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_REG_OFFSET 0x384
1273#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_REG_RESVAL 0x0u
1274#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_CLASS_A_9_MASK 0x3u
1275#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_CLASS_A_9_OFFSET 0
1276#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_CLASS_A_9_FIELD \
1277 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_CLASS_A_9_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_CLASS_A_9_OFFSET })
1280#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_REG_OFFSET 0x388
1281#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_REG_RESVAL 0x0u
1282#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_CLASS_A_10_MASK 0x3u
1283#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_CLASS_A_10_OFFSET 0
1284#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_CLASS_A_10_FIELD \
1285 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_CLASS_A_10_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_CLASS_A_10_OFFSET })
1288#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_REG_OFFSET 0x38c
1289#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_REG_RESVAL 0x0u
1290#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_CLASS_A_11_MASK 0x3u
1291#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_CLASS_A_11_OFFSET 0
1292#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_CLASS_A_11_FIELD \
1293 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_CLASS_A_11_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_CLASS_A_11_OFFSET })
1296#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_REG_OFFSET 0x390
1297#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_REG_RESVAL 0x0u
1298#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_CLASS_A_12_MASK 0x3u
1299#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_CLASS_A_12_OFFSET 0
1300#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_CLASS_A_12_FIELD \
1301 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_CLASS_A_12_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_CLASS_A_12_OFFSET })
1304#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_REG_OFFSET 0x394
1305#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_REG_RESVAL 0x0u
1306#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_CLASS_A_13_MASK 0x3u
1307#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_CLASS_A_13_OFFSET 0
1308#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_CLASS_A_13_FIELD \
1309 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_CLASS_A_13_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_CLASS_A_13_OFFSET })
1312#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_REG_OFFSET 0x398
1313#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_REG_RESVAL 0x0u
1314#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_CLASS_A_14_MASK 0x3u
1315#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_CLASS_A_14_OFFSET 0
1316#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_CLASS_A_14_FIELD \
1317 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_CLASS_A_14_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_CLASS_A_14_OFFSET })
1320#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_REG_OFFSET 0x39c
1321#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_REG_RESVAL 0x0u
1322#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_CLASS_A_15_MASK 0x3u
1323#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_CLASS_A_15_OFFSET 0
1324#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_CLASS_A_15_FIELD \
1325 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_CLASS_A_15_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_CLASS_A_15_OFFSET })
1328#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_REG_OFFSET 0x3a0
1329#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_REG_RESVAL 0x0u
1330#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_CLASS_A_16_MASK 0x3u
1331#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_CLASS_A_16_OFFSET 0
1332#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_CLASS_A_16_FIELD \
1333 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_CLASS_A_16_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_CLASS_A_16_OFFSET })
1336#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_REG_OFFSET 0x3a4
1337#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_REG_RESVAL 0x0u
1338#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_CLASS_A_17_MASK 0x3u
1339#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_CLASS_A_17_OFFSET 0
1340#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_CLASS_A_17_FIELD \
1341 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_CLASS_A_17_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_CLASS_A_17_OFFSET })
1344#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_REG_OFFSET 0x3a8
1345#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_REG_RESVAL 0x0u
1346#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_CLASS_A_18_MASK 0x3u
1347#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_CLASS_A_18_OFFSET 0
1348#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_CLASS_A_18_FIELD \
1349 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_CLASS_A_18_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_CLASS_A_18_OFFSET })
1352#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_REG_OFFSET 0x3ac
1353#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_REG_RESVAL 0x0u
1354#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_CLASS_A_19_MASK 0x3u
1355#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_CLASS_A_19_OFFSET 0
1356#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_CLASS_A_19_FIELD \
1357 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_CLASS_A_19_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_CLASS_A_19_OFFSET })
1360#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_REG_OFFSET 0x3b0
1361#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_REG_RESVAL 0x0u
1362#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_CLASS_A_20_MASK 0x3u
1363#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_CLASS_A_20_OFFSET 0
1364#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_CLASS_A_20_FIELD \
1365 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_CLASS_A_20_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_CLASS_A_20_OFFSET })
1368#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_REG_OFFSET 0x3b4
1369#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_REG_RESVAL 0x0u
1370#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_CLASS_A_21_MASK 0x3u
1371#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_CLASS_A_21_OFFSET 0
1372#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_CLASS_A_21_FIELD \
1373 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_CLASS_A_21_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_CLASS_A_21_OFFSET })
1376#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_REG_OFFSET 0x3b8
1377#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_REG_RESVAL 0x0u
1378#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_CLASS_A_22_MASK 0x3u
1379#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_CLASS_A_22_OFFSET 0
1380#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_CLASS_A_22_FIELD \
1381 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_CLASS_A_22_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_CLASS_A_22_OFFSET })
1384#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_REG_OFFSET 0x3bc
1385#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_REG_RESVAL 0x0u
1386#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_CLASS_A_23_MASK 0x3u
1387#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_CLASS_A_23_OFFSET 0
1388#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_CLASS_A_23_FIELD \
1389 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_CLASS_A_23_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_CLASS_A_23_OFFSET })
1392#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_REG_OFFSET 0x3c0
1393#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_REG_RESVAL 0x0u
1394#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_CLASS_A_24_MASK 0x3u
1395#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_CLASS_A_24_OFFSET 0
1396#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_CLASS_A_24_FIELD \
1397 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_CLASS_A_24_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_CLASS_A_24_OFFSET })
1400#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_REG_OFFSET 0x3c4
1401#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_REG_RESVAL 0x0u
1402#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_CLASS_A_25_MASK 0x3u
1403#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_CLASS_A_25_OFFSET 0
1404#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_CLASS_A_25_FIELD \
1405 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_CLASS_A_25_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_CLASS_A_25_OFFSET })
1408#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_REG_OFFSET 0x3c8
1409#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_REG_RESVAL 0x0u
1410#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_CLASS_A_26_MASK 0x3u
1411#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_CLASS_A_26_OFFSET 0
1412#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_CLASS_A_26_FIELD \
1413 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_CLASS_A_26_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_CLASS_A_26_OFFSET })
1416#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_REG_OFFSET 0x3cc
1417#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_REG_RESVAL 0x0u
1418#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_CLASS_A_27_MASK 0x3u
1419#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_CLASS_A_27_OFFSET 0
1420#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_CLASS_A_27_FIELD \
1421 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_CLASS_A_27_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_CLASS_A_27_OFFSET })
1424#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_REG_OFFSET 0x3d0
1425#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_REG_RESVAL 0x0u
1426#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_CLASS_A_28_MASK 0x3u
1427#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_CLASS_A_28_OFFSET 0
1428#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_CLASS_A_28_FIELD \
1429 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_CLASS_A_28_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_CLASS_A_28_OFFSET })
1432#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_REG_OFFSET 0x3d4
1433#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_REG_RESVAL 0x0u
1434#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_CLASS_A_29_MASK 0x3u
1435#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_CLASS_A_29_OFFSET 0
1436#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_CLASS_A_29_FIELD \
1437 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_CLASS_A_29_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_CLASS_A_29_OFFSET })
1440#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_REG_OFFSET 0x3d8
1441#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_REG_RESVAL 0x0u
1442#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_CLASS_A_30_MASK 0x3u
1443#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_CLASS_A_30_OFFSET 0
1444#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_CLASS_A_30_FIELD \
1445 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_CLASS_A_30_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_CLASS_A_30_OFFSET })
1448#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_REG_OFFSET 0x3dc
1449#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_REG_RESVAL 0x0u
1450#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_CLASS_A_31_MASK 0x3u
1451#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_CLASS_A_31_OFFSET 0
1452#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_CLASS_A_31_FIELD \
1453 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_CLASS_A_31_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_CLASS_A_31_OFFSET })
1456#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_REG_OFFSET 0x3e0
1457#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_REG_RESVAL 0x0u
1458#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_CLASS_A_32_MASK 0x3u
1459#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_CLASS_A_32_OFFSET 0
1460#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_CLASS_A_32_FIELD \
1461 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_CLASS_A_32_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_CLASS_A_32_OFFSET })
1464#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_REG_OFFSET 0x3e4
1465#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_REG_RESVAL 0x0u
1466#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_CLASS_A_33_MASK 0x3u
1467#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_CLASS_A_33_OFFSET 0
1468#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_CLASS_A_33_FIELD \
1469 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_CLASS_A_33_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_CLASS_A_33_OFFSET })
1472#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_REG_OFFSET 0x3e8
1473#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_REG_RESVAL 0x0u
1474#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_CLASS_A_34_MASK 0x3u
1475#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_CLASS_A_34_OFFSET 0
1476#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_CLASS_A_34_FIELD \
1477 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_CLASS_A_34_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_CLASS_A_34_OFFSET })
1480#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_REG_OFFSET 0x3ec
1481#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_REG_RESVAL 0x0u
1482#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_CLASS_A_35_MASK 0x3u
1483#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_CLASS_A_35_OFFSET 0
1484#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_CLASS_A_35_FIELD \
1485 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_CLASS_A_35_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_CLASS_A_35_OFFSET })
1488#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_REG_OFFSET 0x3f0
1489#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_REG_RESVAL 0x0u
1490#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_CLASS_A_36_MASK 0x3u
1491#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_CLASS_A_36_OFFSET 0
1492#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_CLASS_A_36_FIELD \
1493 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_CLASS_A_36_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_CLASS_A_36_OFFSET })
1496#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_REG_OFFSET 0x3f4
1497#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_REG_RESVAL 0x0u
1498#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_CLASS_A_37_MASK 0x3u
1499#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_CLASS_A_37_OFFSET 0
1500#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_CLASS_A_37_FIELD \
1501 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_CLASS_A_37_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_CLASS_A_37_OFFSET })
1504#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_REG_OFFSET 0x3f8
1505#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_REG_RESVAL 0x0u
1506#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_CLASS_A_38_MASK 0x3u
1507#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_CLASS_A_38_OFFSET 0
1508#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_CLASS_A_38_FIELD \
1509 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_CLASS_A_38_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_CLASS_A_38_OFFSET })
1512#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_REG_OFFSET 0x3fc
1513#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_REG_RESVAL 0x0u
1514#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_CLASS_A_39_MASK 0x3u
1515#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_CLASS_A_39_OFFSET 0
1516#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_CLASS_A_39_FIELD \
1517 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_CLASS_A_39_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_CLASS_A_39_OFFSET })
1520#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_REG_OFFSET 0x400
1521#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_REG_RESVAL 0x0u
1522#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_CLASS_A_40_MASK 0x3u
1523#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_CLASS_A_40_OFFSET 0
1524#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_CLASS_A_40_FIELD \
1525 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_CLASS_A_40_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_CLASS_A_40_OFFSET })
1528#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_REG_OFFSET 0x404
1529#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_REG_RESVAL 0x0u
1530#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_CLASS_A_41_MASK 0x3u
1531#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_CLASS_A_41_OFFSET 0
1532#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_CLASS_A_41_FIELD \
1533 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_CLASS_A_41_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_CLASS_A_41_OFFSET })
1536#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_REG_OFFSET 0x408
1537#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_REG_RESVAL 0x0u
1538#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_CLASS_A_42_MASK 0x3u
1539#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_CLASS_A_42_OFFSET 0
1540#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_CLASS_A_42_FIELD \
1541 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_CLASS_A_42_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_CLASS_A_42_OFFSET })
1544#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_REG_OFFSET 0x40c
1545#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_REG_RESVAL 0x0u
1546#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_CLASS_A_43_MASK 0x3u
1547#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_CLASS_A_43_OFFSET 0
1548#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_CLASS_A_43_FIELD \
1549 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_CLASS_A_43_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_CLASS_A_43_OFFSET })
1552#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_REG_OFFSET 0x410
1553#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_REG_RESVAL 0x0u
1554#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_CLASS_A_44_MASK 0x3u
1555#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_CLASS_A_44_OFFSET 0
1556#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_CLASS_A_44_FIELD \
1557 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_CLASS_A_44_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_CLASS_A_44_OFFSET })
1560#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_REG_OFFSET 0x414
1561#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_REG_RESVAL 0x0u
1562#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_CLASS_A_45_MASK 0x3u
1563#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_CLASS_A_45_OFFSET 0
1564#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_CLASS_A_45_FIELD \
1565 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_CLASS_A_45_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_CLASS_A_45_OFFSET })
1568#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_REG_OFFSET 0x418
1569#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_REG_RESVAL 0x0u
1570#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_CLASS_A_46_MASK 0x3u
1571#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_CLASS_A_46_OFFSET 0
1572#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_CLASS_A_46_FIELD \
1573 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_CLASS_A_46_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_CLASS_A_46_OFFSET })
1576#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_REG_OFFSET 0x41c
1577#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_REG_RESVAL 0x0u
1578#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_CLASS_A_47_MASK 0x3u
1579#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_CLASS_A_47_OFFSET 0
1580#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_CLASS_A_47_FIELD \
1581 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_CLASS_A_47_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_CLASS_A_47_OFFSET })
1584#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_REG_OFFSET 0x420
1585#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_REG_RESVAL 0x0u
1586#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_CLASS_A_48_MASK 0x3u
1587#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_CLASS_A_48_OFFSET 0
1588#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_CLASS_A_48_FIELD \
1589 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_CLASS_A_48_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_CLASS_A_48_OFFSET })
1592#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_REG_OFFSET 0x424
1593#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_REG_RESVAL 0x0u
1594#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_CLASS_A_49_MASK 0x3u
1595#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_CLASS_A_49_OFFSET 0
1596#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_CLASS_A_49_FIELD \
1597 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_CLASS_A_49_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_CLASS_A_49_OFFSET })
1600#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_REG_OFFSET 0x428
1601#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_REG_RESVAL 0x0u
1602#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_CLASS_A_50_MASK 0x3u
1603#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_CLASS_A_50_OFFSET 0
1604#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_CLASS_A_50_FIELD \
1605 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_CLASS_A_50_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_CLASS_A_50_OFFSET })
1608#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_REG_OFFSET 0x42c
1609#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_REG_RESVAL 0x0u
1610#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_CLASS_A_51_MASK 0x3u
1611#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_CLASS_A_51_OFFSET 0
1612#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_CLASS_A_51_FIELD \
1613 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_CLASS_A_51_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_CLASS_A_51_OFFSET })
1616#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_REG_OFFSET 0x430
1617#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_REG_RESVAL 0x0u
1618#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_CLASS_A_52_MASK 0x3u
1619#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_CLASS_A_52_OFFSET 0
1620#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_CLASS_A_52_FIELD \
1621 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_CLASS_A_52_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_CLASS_A_52_OFFSET })
1624#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_REG_OFFSET 0x434
1625#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_REG_RESVAL 0x0u
1626#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_CLASS_A_53_MASK 0x3u
1627#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_CLASS_A_53_OFFSET 0
1628#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_CLASS_A_53_FIELD \
1629 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_CLASS_A_53_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_CLASS_A_53_OFFSET })
1632#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_REG_OFFSET 0x438
1633#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_REG_RESVAL 0x0u
1634#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_CLASS_A_54_MASK 0x3u
1635#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_CLASS_A_54_OFFSET 0
1636#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_CLASS_A_54_FIELD \
1637 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_CLASS_A_54_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_CLASS_A_54_OFFSET })
1640#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_REG_OFFSET 0x43c
1641#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_REG_RESVAL 0x0u
1642#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_CLASS_A_55_MASK 0x3u
1643#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_CLASS_A_55_OFFSET 0
1644#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_CLASS_A_55_FIELD \
1645 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_CLASS_A_55_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_CLASS_A_55_OFFSET })
1648#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_REG_OFFSET 0x440
1649#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_REG_RESVAL 0x0u
1650#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_CLASS_A_56_MASK 0x3u
1651#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_CLASS_A_56_OFFSET 0
1652#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_CLASS_A_56_FIELD \
1653 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_CLASS_A_56_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_CLASS_A_56_OFFSET })
1656#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_REG_OFFSET 0x444
1657#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_REG_RESVAL 0x0u
1658#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_CLASS_A_57_MASK 0x3u
1659#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_CLASS_A_57_OFFSET 0
1660#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_CLASS_A_57_FIELD \
1661 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_CLASS_A_57_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_CLASS_A_57_OFFSET })
1664#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_REG_OFFSET 0x448
1665#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_REG_RESVAL 0x0u
1666#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_CLASS_A_58_MASK 0x3u
1667#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_CLASS_A_58_OFFSET 0
1668#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_CLASS_A_58_FIELD \
1669 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_CLASS_A_58_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_CLASS_A_58_OFFSET })
1672#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_REG_OFFSET 0x44c
1673#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_REG_RESVAL 0x0u
1674#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_CLASS_A_59_MASK 0x3u
1675#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_CLASS_A_59_OFFSET 0
1676#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_CLASS_A_59_FIELD \
1677 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_CLASS_A_59_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_CLASS_A_59_OFFSET })
1680#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_60_REG_OFFSET 0x450
1681#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_60_REG_RESVAL 0x0u
1682#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_60_CLASS_A_60_MASK 0x3u
1683#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_60_CLASS_A_60_OFFSET 0
1684#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_60_CLASS_A_60_FIELD \
1685 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_60_CLASS_A_60_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_60_CLASS_A_60_OFFSET })
1688#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_61_REG_OFFSET 0x454
1689#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_61_REG_RESVAL 0x0u
1690#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_61_CLASS_A_61_MASK 0x3u
1691#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_61_CLASS_A_61_OFFSET 0
1692#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_61_CLASS_A_61_FIELD \
1693 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_61_CLASS_A_61_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_61_CLASS_A_61_OFFSET })
1696#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_62_REG_OFFSET 0x458
1697#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_62_REG_RESVAL 0x0u
1698#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_62_CLASS_A_62_MASK 0x3u
1699#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_62_CLASS_A_62_OFFSET 0
1700#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_62_CLASS_A_62_FIELD \
1701 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_62_CLASS_A_62_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_62_CLASS_A_62_OFFSET })
1704#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_63_REG_OFFSET 0x45c
1705#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_63_REG_RESVAL 0x0u
1706#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_63_CLASS_A_63_MASK 0x3u
1707#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_63_CLASS_A_63_OFFSET 0
1708#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_63_CLASS_A_63_FIELD \
1709 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_63_CLASS_A_63_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_63_CLASS_A_63_OFFSET })
1712#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_64_REG_OFFSET 0x460
1713#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_64_REG_RESVAL 0x0u
1714#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_64_CLASS_A_64_MASK 0x3u
1715#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_64_CLASS_A_64_OFFSET 0
1716#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_64_CLASS_A_64_FIELD \
1717 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_64_CLASS_A_64_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_64_CLASS_A_64_OFFSET })
1720#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_65_REG_OFFSET 0x464
1721#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_65_REG_RESVAL 0x0u
1722#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_65_CLASS_A_65_MASK 0x3u
1723#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_65_CLASS_A_65_OFFSET 0
1724#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_65_CLASS_A_65_FIELD \
1725 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_65_CLASS_A_65_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_65_CLASS_A_65_OFFSET })
1728#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_66_REG_OFFSET 0x468
1729#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_66_REG_RESVAL 0x0u
1730#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_66_CLASS_A_66_MASK 0x3u
1731#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_66_CLASS_A_66_OFFSET 0
1732#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_66_CLASS_A_66_FIELD \
1733 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_66_CLASS_A_66_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_66_CLASS_A_66_OFFSET })
1736#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_67_REG_OFFSET 0x46c
1737#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_67_REG_RESVAL 0x0u
1738#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_67_CLASS_A_67_MASK 0x3u
1739#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_67_CLASS_A_67_OFFSET 0
1740#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_67_CLASS_A_67_FIELD \
1741 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_67_CLASS_A_67_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_67_CLASS_A_67_OFFSET })
1744#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_68_REG_OFFSET 0x470
1745#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_68_REG_RESVAL 0x0u
1746#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_68_CLASS_A_68_MASK 0x3u
1747#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_68_CLASS_A_68_OFFSET 0
1748#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_68_CLASS_A_68_FIELD \
1749 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_68_CLASS_A_68_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_68_CLASS_A_68_OFFSET })
1752#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_69_REG_OFFSET 0x474
1753#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_69_REG_RESVAL 0x0u
1754#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_69_CLASS_A_69_MASK 0x3u
1755#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_69_CLASS_A_69_OFFSET 0
1756#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_69_CLASS_A_69_FIELD \
1757 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_69_CLASS_A_69_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_69_CLASS_A_69_OFFSET })
1760#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_70_REG_OFFSET 0x478
1761#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_70_REG_RESVAL 0x0u
1762#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_70_CLASS_A_70_MASK 0x3u
1763#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_70_CLASS_A_70_OFFSET 0
1764#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_70_CLASS_A_70_FIELD \
1765 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_70_CLASS_A_70_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_70_CLASS_A_70_OFFSET })
1768#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_71_REG_OFFSET 0x47c
1769#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_71_REG_RESVAL 0x0u
1770#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_71_CLASS_A_71_MASK 0x3u
1771#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_71_CLASS_A_71_OFFSET 0
1772#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_71_CLASS_A_71_FIELD \
1773 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_71_CLASS_A_71_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_71_CLASS_A_71_OFFSET })
1776#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_72_REG_OFFSET 0x480
1777#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_72_REG_RESVAL 0x0u
1778#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_72_CLASS_A_72_MASK 0x3u
1779#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_72_CLASS_A_72_OFFSET 0
1780#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_72_CLASS_A_72_FIELD \
1781 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_72_CLASS_A_72_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_72_CLASS_A_72_OFFSET })
1784#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_73_REG_OFFSET 0x484
1785#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_73_REG_RESVAL 0x0u
1786#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_73_CLASS_A_73_MASK 0x3u
1787#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_73_CLASS_A_73_OFFSET 0
1788#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_73_CLASS_A_73_FIELD \
1789 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_73_CLASS_A_73_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_73_CLASS_A_73_OFFSET })
1792#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_74_REG_OFFSET 0x488
1793#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_74_REG_RESVAL 0x0u
1794#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_74_CLASS_A_74_MASK 0x3u
1795#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_74_CLASS_A_74_OFFSET 0
1796#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_74_CLASS_A_74_FIELD \
1797 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_74_CLASS_A_74_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_74_CLASS_A_74_OFFSET })
1800#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_75_REG_OFFSET 0x48c
1801#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_75_REG_RESVAL 0x0u
1802#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_75_CLASS_A_75_MASK 0x3u
1803#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_75_CLASS_A_75_OFFSET 0
1804#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_75_CLASS_A_75_FIELD \
1805 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_75_CLASS_A_75_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_75_CLASS_A_75_OFFSET })
1808#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_76_REG_OFFSET 0x490
1809#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_76_REG_RESVAL 0x0u
1810#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_76_CLASS_A_76_MASK 0x3u
1811#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_76_CLASS_A_76_OFFSET 0
1812#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_76_CLASS_A_76_FIELD \
1813 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_76_CLASS_A_76_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_76_CLASS_A_76_OFFSET })
1816#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_77_REG_OFFSET 0x494
1817#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_77_REG_RESVAL 0x0u
1818#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_77_CLASS_A_77_MASK 0x3u
1819#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_77_CLASS_A_77_OFFSET 0
1820#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_77_CLASS_A_77_FIELD \
1821 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_77_CLASS_A_77_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_77_CLASS_A_77_OFFSET })
1824#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_78_REG_OFFSET 0x498
1825#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_78_REG_RESVAL 0x0u
1826#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_78_CLASS_A_78_MASK 0x3u
1827#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_78_CLASS_A_78_OFFSET 0
1828#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_78_CLASS_A_78_FIELD \
1829 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_78_CLASS_A_78_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_78_CLASS_A_78_OFFSET })
1832#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_79_REG_OFFSET 0x49c
1833#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_79_REG_RESVAL 0x0u
1834#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_79_CLASS_A_79_MASK 0x3u
1835#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_79_CLASS_A_79_OFFSET 0
1836#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_79_CLASS_A_79_FIELD \
1837 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_79_CLASS_A_79_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_79_CLASS_A_79_OFFSET })
1840#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_80_REG_OFFSET 0x4a0
1841#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_80_REG_RESVAL 0x0u
1842#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_80_CLASS_A_80_MASK 0x3u
1843#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_80_CLASS_A_80_OFFSET 0
1844#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_80_CLASS_A_80_FIELD \
1845 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_80_CLASS_A_80_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_80_CLASS_A_80_OFFSET })
1848#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_81_REG_OFFSET 0x4a4
1849#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_81_REG_RESVAL 0x0u
1850#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_81_CLASS_A_81_MASK 0x3u
1851#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_81_CLASS_A_81_OFFSET 0
1852#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_81_CLASS_A_81_FIELD \
1853 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_81_CLASS_A_81_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_81_CLASS_A_81_OFFSET })
1856#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_82_REG_OFFSET 0x4a8
1857#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_82_REG_RESVAL 0x0u
1858#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_82_CLASS_A_82_MASK 0x3u
1859#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_82_CLASS_A_82_OFFSET 0
1860#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_82_CLASS_A_82_FIELD \
1861 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_82_CLASS_A_82_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_82_CLASS_A_82_OFFSET })
1864#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_83_REG_OFFSET 0x4ac
1865#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_83_REG_RESVAL 0x0u
1866#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_83_CLASS_A_83_MASK 0x3u
1867#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_83_CLASS_A_83_OFFSET 0
1868#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_83_CLASS_A_83_FIELD \
1869 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_83_CLASS_A_83_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_83_CLASS_A_83_OFFSET })
1872#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_84_REG_OFFSET 0x4b0
1873#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_84_REG_RESVAL 0x0u
1874#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_84_CLASS_A_84_MASK 0x3u
1875#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_84_CLASS_A_84_OFFSET 0
1876#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_84_CLASS_A_84_FIELD \
1877 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_84_CLASS_A_84_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_84_CLASS_A_84_OFFSET })
1880#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_85_REG_OFFSET 0x4b4
1881#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_85_REG_RESVAL 0x0u
1882#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_85_CLASS_A_85_MASK 0x3u
1883#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_85_CLASS_A_85_OFFSET 0
1884#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_85_CLASS_A_85_FIELD \
1885 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_85_CLASS_A_85_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_85_CLASS_A_85_OFFSET })
1888#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_86_REG_OFFSET 0x4b8
1889#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_86_REG_RESVAL 0x0u
1890#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_86_CLASS_A_86_MASK 0x3u
1891#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_86_CLASS_A_86_OFFSET 0
1892#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_86_CLASS_A_86_FIELD \
1893 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_86_CLASS_A_86_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_86_CLASS_A_86_OFFSET })
1896#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_87_REG_OFFSET 0x4bc
1897#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_87_REG_RESVAL 0x0u
1898#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_87_CLASS_A_87_MASK 0x3u
1899#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_87_CLASS_A_87_OFFSET 0
1900#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_87_CLASS_A_87_FIELD \
1901 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_87_CLASS_A_87_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_87_CLASS_A_87_OFFSET })
1904#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_88_REG_OFFSET 0x4c0
1905#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_88_REG_RESVAL 0x0u
1906#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_88_CLASS_A_88_MASK 0x3u
1907#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_88_CLASS_A_88_OFFSET 0
1908#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_88_CLASS_A_88_FIELD \
1909 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_88_CLASS_A_88_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_88_CLASS_A_88_OFFSET })
1912#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_89_REG_OFFSET 0x4c4
1913#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_89_REG_RESVAL 0x0u
1914#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_89_CLASS_A_89_MASK 0x3u
1915#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_89_CLASS_A_89_OFFSET 0
1916#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_89_CLASS_A_89_FIELD \
1917 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_89_CLASS_A_89_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_89_CLASS_A_89_OFFSET })
1920#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_90_REG_OFFSET 0x4c8
1921#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_90_REG_RESVAL 0x0u
1922#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_90_CLASS_A_90_MASK 0x3u
1923#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_90_CLASS_A_90_OFFSET 0
1924#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_90_CLASS_A_90_FIELD \
1925 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_90_CLASS_A_90_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_90_CLASS_A_90_OFFSET })
1928#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_91_REG_OFFSET 0x4cc
1929#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_91_REG_RESVAL 0x0u
1930#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_91_CLASS_A_91_MASK 0x3u
1931#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_91_CLASS_A_91_OFFSET 0
1932#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_91_CLASS_A_91_FIELD \
1933 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_91_CLASS_A_91_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_91_CLASS_A_91_OFFSET })
1936#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_92_REG_OFFSET 0x4d0
1937#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_92_REG_RESVAL 0x0u
1938#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_92_CLASS_A_92_MASK 0x3u
1939#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_92_CLASS_A_92_OFFSET 0
1940#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_92_CLASS_A_92_FIELD \
1941 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_92_CLASS_A_92_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_92_CLASS_A_92_OFFSET })
1944#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_93_REG_OFFSET 0x4d4
1945#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_93_REG_RESVAL 0x0u
1946#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_93_CLASS_A_93_MASK 0x3u
1947#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_93_CLASS_A_93_OFFSET 0
1948#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_93_CLASS_A_93_FIELD \
1949 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_93_CLASS_A_93_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_93_CLASS_A_93_OFFSET })
1952#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_94_REG_OFFSET 0x4d8
1953#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_94_REG_RESVAL 0x0u
1954#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_94_CLASS_A_94_MASK 0x3u
1955#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_94_CLASS_A_94_OFFSET 0
1956#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_94_CLASS_A_94_FIELD \
1957 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_94_CLASS_A_94_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_94_CLASS_A_94_OFFSET })
1960#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_95_REG_OFFSET 0x4dc
1961#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_95_REG_RESVAL 0x0u
1962#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_95_CLASS_A_95_MASK 0x3u
1963#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_95_CLASS_A_95_OFFSET 0
1964#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_95_CLASS_A_95_FIELD \
1965 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_95_CLASS_A_95_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_95_CLASS_A_95_OFFSET })
1968#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_96_REG_OFFSET 0x4e0
1969#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_96_REG_RESVAL 0x0u
1970#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_96_CLASS_A_96_MASK 0x3u
1971#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_96_CLASS_A_96_OFFSET 0
1972#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_96_CLASS_A_96_FIELD \
1973 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_96_CLASS_A_96_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_96_CLASS_A_96_OFFSET })
1976#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_97_REG_OFFSET 0x4e4
1977#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_97_REG_RESVAL 0x0u
1978#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_97_CLASS_A_97_MASK 0x3u
1979#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_97_CLASS_A_97_OFFSET 0
1980#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_97_CLASS_A_97_FIELD \
1981 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_97_CLASS_A_97_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_97_CLASS_A_97_OFFSET })
1984#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_98_REG_OFFSET 0x4e8
1985#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_98_REG_RESVAL 0x0u
1986#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_98_CLASS_A_98_MASK 0x3u
1987#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_98_CLASS_A_98_OFFSET 0
1988#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_98_CLASS_A_98_FIELD \
1989 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_98_CLASS_A_98_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_98_CLASS_A_98_OFFSET })
1992#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_99_REG_OFFSET 0x4ec
1993#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_99_REG_RESVAL 0x0u
1994#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_99_CLASS_A_99_MASK 0x3u
1995#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_99_CLASS_A_99_OFFSET 0
1996#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_99_CLASS_A_99_FIELD \
1997 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_99_CLASS_A_99_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_99_CLASS_A_99_OFFSET })
2000#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_100_REG_OFFSET 0x4f0
2001#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_100_REG_RESVAL 0x0u
2002#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_100_CLASS_A_100_MASK 0x3u
2003#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_100_CLASS_A_100_OFFSET 0
2004#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_100_CLASS_A_100_FIELD \
2005 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_100_CLASS_A_100_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_100_CLASS_A_100_OFFSET })
2008#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_101_REG_OFFSET 0x4f4
2009#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_101_REG_RESVAL 0x0u
2010#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_101_CLASS_A_101_MASK 0x3u
2011#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_101_CLASS_A_101_OFFSET 0
2012#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_101_CLASS_A_101_FIELD \
2013 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_101_CLASS_A_101_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_101_CLASS_A_101_OFFSET })
2016#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_102_REG_OFFSET 0x4f8
2017#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_102_REG_RESVAL 0x0u
2018#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_102_CLASS_A_102_MASK 0x3u
2019#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_102_CLASS_A_102_OFFSET 0
2020#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_102_CLASS_A_102_FIELD \
2021 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_102_CLASS_A_102_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_102_CLASS_A_102_OFFSET })
2024#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_103_REG_OFFSET 0x4fc
2025#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_103_REG_RESVAL 0x0u
2026#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_103_CLASS_A_103_MASK 0x3u
2027#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_103_CLASS_A_103_OFFSET 0
2028#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_103_CLASS_A_103_FIELD \
2029 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_103_CLASS_A_103_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_103_CLASS_A_103_OFFSET })
2032#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_104_REG_OFFSET 0x500
2033#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_104_REG_RESVAL 0x0u
2034#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_104_CLASS_A_104_MASK 0x3u
2035#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_104_CLASS_A_104_OFFSET 0
2036#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_104_CLASS_A_104_FIELD \
2037 ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_104_CLASS_A_104_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_104_CLASS_A_104_OFFSET })
2040#define ALERT_HANDLER_ALERT_CAUSE_A_FIELD_WIDTH 1
2041#define ALERT_HANDLER_ALERT_CAUSE_MULTIREG_COUNT 105
2044#define ALERT_HANDLER_ALERT_CAUSE_0_REG_OFFSET 0x504
2045#define ALERT_HANDLER_ALERT_CAUSE_0_REG_RESVAL 0x0u
2046#define ALERT_HANDLER_ALERT_CAUSE_0_A_0_BIT 0
2049#define ALERT_HANDLER_ALERT_CAUSE_1_REG_OFFSET 0x508
2050#define ALERT_HANDLER_ALERT_CAUSE_1_REG_RESVAL 0x0u
2051#define ALERT_HANDLER_ALERT_CAUSE_1_A_1_BIT 0
2054#define ALERT_HANDLER_ALERT_CAUSE_2_REG_OFFSET 0x50c
2055#define ALERT_HANDLER_ALERT_CAUSE_2_REG_RESVAL 0x0u
2056#define ALERT_HANDLER_ALERT_CAUSE_2_A_2_BIT 0
2059#define ALERT_HANDLER_ALERT_CAUSE_3_REG_OFFSET 0x510
2060#define ALERT_HANDLER_ALERT_CAUSE_3_REG_RESVAL 0x0u
2061#define ALERT_HANDLER_ALERT_CAUSE_3_A_3_BIT 0
2064#define ALERT_HANDLER_ALERT_CAUSE_4_REG_OFFSET 0x514
2065#define ALERT_HANDLER_ALERT_CAUSE_4_REG_RESVAL 0x0u
2066#define ALERT_HANDLER_ALERT_CAUSE_4_A_4_BIT 0
2069#define ALERT_HANDLER_ALERT_CAUSE_5_REG_OFFSET 0x518
2070#define ALERT_HANDLER_ALERT_CAUSE_5_REG_RESVAL 0x0u
2071#define ALERT_HANDLER_ALERT_CAUSE_5_A_5_BIT 0
2074#define ALERT_HANDLER_ALERT_CAUSE_6_REG_OFFSET 0x51c
2075#define ALERT_HANDLER_ALERT_CAUSE_6_REG_RESVAL 0x0u
2076#define ALERT_HANDLER_ALERT_CAUSE_6_A_6_BIT 0
2079#define ALERT_HANDLER_ALERT_CAUSE_7_REG_OFFSET 0x520
2080#define ALERT_HANDLER_ALERT_CAUSE_7_REG_RESVAL 0x0u
2081#define ALERT_HANDLER_ALERT_CAUSE_7_A_7_BIT 0
2084#define ALERT_HANDLER_ALERT_CAUSE_8_REG_OFFSET 0x524
2085#define ALERT_HANDLER_ALERT_CAUSE_8_REG_RESVAL 0x0u
2086#define ALERT_HANDLER_ALERT_CAUSE_8_A_8_BIT 0
2089#define ALERT_HANDLER_ALERT_CAUSE_9_REG_OFFSET 0x528
2090#define ALERT_HANDLER_ALERT_CAUSE_9_REG_RESVAL 0x0u
2091#define ALERT_HANDLER_ALERT_CAUSE_9_A_9_BIT 0
2094#define ALERT_HANDLER_ALERT_CAUSE_10_REG_OFFSET 0x52c
2095#define ALERT_HANDLER_ALERT_CAUSE_10_REG_RESVAL 0x0u
2096#define ALERT_HANDLER_ALERT_CAUSE_10_A_10_BIT 0
2099#define ALERT_HANDLER_ALERT_CAUSE_11_REG_OFFSET 0x530
2100#define ALERT_HANDLER_ALERT_CAUSE_11_REG_RESVAL 0x0u
2101#define ALERT_HANDLER_ALERT_CAUSE_11_A_11_BIT 0
2104#define ALERT_HANDLER_ALERT_CAUSE_12_REG_OFFSET 0x534
2105#define ALERT_HANDLER_ALERT_CAUSE_12_REG_RESVAL 0x0u
2106#define ALERT_HANDLER_ALERT_CAUSE_12_A_12_BIT 0
2109#define ALERT_HANDLER_ALERT_CAUSE_13_REG_OFFSET 0x538
2110#define ALERT_HANDLER_ALERT_CAUSE_13_REG_RESVAL 0x0u
2111#define ALERT_HANDLER_ALERT_CAUSE_13_A_13_BIT 0
2114#define ALERT_HANDLER_ALERT_CAUSE_14_REG_OFFSET 0x53c
2115#define ALERT_HANDLER_ALERT_CAUSE_14_REG_RESVAL 0x0u
2116#define ALERT_HANDLER_ALERT_CAUSE_14_A_14_BIT 0
2119#define ALERT_HANDLER_ALERT_CAUSE_15_REG_OFFSET 0x540
2120#define ALERT_HANDLER_ALERT_CAUSE_15_REG_RESVAL 0x0u
2121#define ALERT_HANDLER_ALERT_CAUSE_15_A_15_BIT 0
2124#define ALERT_HANDLER_ALERT_CAUSE_16_REG_OFFSET 0x544
2125#define ALERT_HANDLER_ALERT_CAUSE_16_REG_RESVAL 0x0u
2126#define ALERT_HANDLER_ALERT_CAUSE_16_A_16_BIT 0
2129#define ALERT_HANDLER_ALERT_CAUSE_17_REG_OFFSET 0x548
2130#define ALERT_HANDLER_ALERT_CAUSE_17_REG_RESVAL 0x0u
2131#define ALERT_HANDLER_ALERT_CAUSE_17_A_17_BIT 0
2134#define ALERT_HANDLER_ALERT_CAUSE_18_REG_OFFSET 0x54c
2135#define ALERT_HANDLER_ALERT_CAUSE_18_REG_RESVAL 0x0u
2136#define ALERT_HANDLER_ALERT_CAUSE_18_A_18_BIT 0
2139#define ALERT_HANDLER_ALERT_CAUSE_19_REG_OFFSET 0x550
2140#define ALERT_HANDLER_ALERT_CAUSE_19_REG_RESVAL 0x0u
2141#define ALERT_HANDLER_ALERT_CAUSE_19_A_19_BIT 0
2144#define ALERT_HANDLER_ALERT_CAUSE_20_REG_OFFSET 0x554
2145#define ALERT_HANDLER_ALERT_CAUSE_20_REG_RESVAL 0x0u
2146#define ALERT_HANDLER_ALERT_CAUSE_20_A_20_BIT 0
2149#define ALERT_HANDLER_ALERT_CAUSE_21_REG_OFFSET 0x558
2150#define ALERT_HANDLER_ALERT_CAUSE_21_REG_RESVAL 0x0u
2151#define ALERT_HANDLER_ALERT_CAUSE_21_A_21_BIT 0
2154#define ALERT_HANDLER_ALERT_CAUSE_22_REG_OFFSET 0x55c
2155#define ALERT_HANDLER_ALERT_CAUSE_22_REG_RESVAL 0x0u
2156#define ALERT_HANDLER_ALERT_CAUSE_22_A_22_BIT 0
2159#define ALERT_HANDLER_ALERT_CAUSE_23_REG_OFFSET 0x560
2160#define ALERT_HANDLER_ALERT_CAUSE_23_REG_RESVAL 0x0u
2161#define ALERT_HANDLER_ALERT_CAUSE_23_A_23_BIT 0
2164#define ALERT_HANDLER_ALERT_CAUSE_24_REG_OFFSET 0x564
2165#define ALERT_HANDLER_ALERT_CAUSE_24_REG_RESVAL 0x0u
2166#define ALERT_HANDLER_ALERT_CAUSE_24_A_24_BIT 0
2169#define ALERT_HANDLER_ALERT_CAUSE_25_REG_OFFSET 0x568
2170#define ALERT_HANDLER_ALERT_CAUSE_25_REG_RESVAL 0x0u
2171#define ALERT_HANDLER_ALERT_CAUSE_25_A_25_BIT 0
2174#define ALERT_HANDLER_ALERT_CAUSE_26_REG_OFFSET 0x56c
2175#define ALERT_HANDLER_ALERT_CAUSE_26_REG_RESVAL 0x0u
2176#define ALERT_HANDLER_ALERT_CAUSE_26_A_26_BIT 0
2179#define ALERT_HANDLER_ALERT_CAUSE_27_REG_OFFSET 0x570
2180#define ALERT_HANDLER_ALERT_CAUSE_27_REG_RESVAL 0x0u
2181#define ALERT_HANDLER_ALERT_CAUSE_27_A_27_BIT 0
2184#define ALERT_HANDLER_ALERT_CAUSE_28_REG_OFFSET 0x574
2185#define ALERT_HANDLER_ALERT_CAUSE_28_REG_RESVAL 0x0u
2186#define ALERT_HANDLER_ALERT_CAUSE_28_A_28_BIT 0
2189#define ALERT_HANDLER_ALERT_CAUSE_29_REG_OFFSET 0x578
2190#define ALERT_HANDLER_ALERT_CAUSE_29_REG_RESVAL 0x0u
2191#define ALERT_HANDLER_ALERT_CAUSE_29_A_29_BIT 0
2194#define ALERT_HANDLER_ALERT_CAUSE_30_REG_OFFSET 0x57c
2195#define ALERT_HANDLER_ALERT_CAUSE_30_REG_RESVAL 0x0u
2196#define ALERT_HANDLER_ALERT_CAUSE_30_A_30_BIT 0
2199#define ALERT_HANDLER_ALERT_CAUSE_31_REG_OFFSET 0x580
2200#define ALERT_HANDLER_ALERT_CAUSE_31_REG_RESVAL 0x0u
2201#define ALERT_HANDLER_ALERT_CAUSE_31_A_31_BIT 0
2204#define ALERT_HANDLER_ALERT_CAUSE_32_REG_OFFSET 0x584
2205#define ALERT_HANDLER_ALERT_CAUSE_32_REG_RESVAL 0x0u
2206#define ALERT_HANDLER_ALERT_CAUSE_32_A_32_BIT 0
2209#define ALERT_HANDLER_ALERT_CAUSE_33_REG_OFFSET 0x588
2210#define ALERT_HANDLER_ALERT_CAUSE_33_REG_RESVAL 0x0u
2211#define ALERT_HANDLER_ALERT_CAUSE_33_A_33_BIT 0
2214#define ALERT_HANDLER_ALERT_CAUSE_34_REG_OFFSET 0x58c
2215#define ALERT_HANDLER_ALERT_CAUSE_34_REG_RESVAL 0x0u
2216#define ALERT_HANDLER_ALERT_CAUSE_34_A_34_BIT 0
2219#define ALERT_HANDLER_ALERT_CAUSE_35_REG_OFFSET 0x590
2220#define ALERT_HANDLER_ALERT_CAUSE_35_REG_RESVAL 0x0u
2221#define ALERT_HANDLER_ALERT_CAUSE_35_A_35_BIT 0
2224#define ALERT_HANDLER_ALERT_CAUSE_36_REG_OFFSET 0x594
2225#define ALERT_HANDLER_ALERT_CAUSE_36_REG_RESVAL 0x0u
2226#define ALERT_HANDLER_ALERT_CAUSE_36_A_36_BIT 0
2229#define ALERT_HANDLER_ALERT_CAUSE_37_REG_OFFSET 0x598
2230#define ALERT_HANDLER_ALERT_CAUSE_37_REG_RESVAL 0x0u
2231#define ALERT_HANDLER_ALERT_CAUSE_37_A_37_BIT 0
2234#define ALERT_HANDLER_ALERT_CAUSE_38_REG_OFFSET 0x59c
2235#define ALERT_HANDLER_ALERT_CAUSE_38_REG_RESVAL 0x0u
2236#define ALERT_HANDLER_ALERT_CAUSE_38_A_38_BIT 0
2239#define ALERT_HANDLER_ALERT_CAUSE_39_REG_OFFSET 0x5a0
2240#define ALERT_HANDLER_ALERT_CAUSE_39_REG_RESVAL 0x0u
2241#define ALERT_HANDLER_ALERT_CAUSE_39_A_39_BIT 0
2244#define ALERT_HANDLER_ALERT_CAUSE_40_REG_OFFSET 0x5a4
2245#define ALERT_HANDLER_ALERT_CAUSE_40_REG_RESVAL 0x0u
2246#define ALERT_HANDLER_ALERT_CAUSE_40_A_40_BIT 0
2249#define ALERT_HANDLER_ALERT_CAUSE_41_REG_OFFSET 0x5a8
2250#define ALERT_HANDLER_ALERT_CAUSE_41_REG_RESVAL 0x0u
2251#define ALERT_HANDLER_ALERT_CAUSE_41_A_41_BIT 0
2254#define ALERT_HANDLER_ALERT_CAUSE_42_REG_OFFSET 0x5ac
2255#define ALERT_HANDLER_ALERT_CAUSE_42_REG_RESVAL 0x0u
2256#define ALERT_HANDLER_ALERT_CAUSE_42_A_42_BIT 0
2259#define ALERT_HANDLER_ALERT_CAUSE_43_REG_OFFSET 0x5b0
2260#define ALERT_HANDLER_ALERT_CAUSE_43_REG_RESVAL 0x0u
2261#define ALERT_HANDLER_ALERT_CAUSE_43_A_43_BIT 0
2264#define ALERT_HANDLER_ALERT_CAUSE_44_REG_OFFSET 0x5b4
2265#define ALERT_HANDLER_ALERT_CAUSE_44_REG_RESVAL 0x0u
2266#define ALERT_HANDLER_ALERT_CAUSE_44_A_44_BIT 0
2269#define ALERT_HANDLER_ALERT_CAUSE_45_REG_OFFSET 0x5b8
2270#define ALERT_HANDLER_ALERT_CAUSE_45_REG_RESVAL 0x0u
2271#define ALERT_HANDLER_ALERT_CAUSE_45_A_45_BIT 0
2274#define ALERT_HANDLER_ALERT_CAUSE_46_REG_OFFSET 0x5bc
2275#define ALERT_HANDLER_ALERT_CAUSE_46_REG_RESVAL 0x0u
2276#define ALERT_HANDLER_ALERT_CAUSE_46_A_46_BIT 0
2279#define ALERT_HANDLER_ALERT_CAUSE_47_REG_OFFSET 0x5c0
2280#define ALERT_HANDLER_ALERT_CAUSE_47_REG_RESVAL 0x0u
2281#define ALERT_HANDLER_ALERT_CAUSE_47_A_47_BIT 0
2284#define ALERT_HANDLER_ALERT_CAUSE_48_REG_OFFSET 0x5c4
2285#define ALERT_HANDLER_ALERT_CAUSE_48_REG_RESVAL 0x0u
2286#define ALERT_HANDLER_ALERT_CAUSE_48_A_48_BIT 0
2289#define ALERT_HANDLER_ALERT_CAUSE_49_REG_OFFSET 0x5c8
2290#define ALERT_HANDLER_ALERT_CAUSE_49_REG_RESVAL 0x0u
2291#define ALERT_HANDLER_ALERT_CAUSE_49_A_49_BIT 0
2294#define ALERT_HANDLER_ALERT_CAUSE_50_REG_OFFSET 0x5cc
2295#define ALERT_HANDLER_ALERT_CAUSE_50_REG_RESVAL 0x0u
2296#define ALERT_HANDLER_ALERT_CAUSE_50_A_50_BIT 0
2299#define ALERT_HANDLER_ALERT_CAUSE_51_REG_OFFSET 0x5d0
2300#define ALERT_HANDLER_ALERT_CAUSE_51_REG_RESVAL 0x0u
2301#define ALERT_HANDLER_ALERT_CAUSE_51_A_51_BIT 0
2304#define ALERT_HANDLER_ALERT_CAUSE_52_REG_OFFSET 0x5d4
2305#define ALERT_HANDLER_ALERT_CAUSE_52_REG_RESVAL 0x0u
2306#define ALERT_HANDLER_ALERT_CAUSE_52_A_52_BIT 0
2309#define ALERT_HANDLER_ALERT_CAUSE_53_REG_OFFSET 0x5d8
2310#define ALERT_HANDLER_ALERT_CAUSE_53_REG_RESVAL 0x0u
2311#define ALERT_HANDLER_ALERT_CAUSE_53_A_53_BIT 0
2314#define ALERT_HANDLER_ALERT_CAUSE_54_REG_OFFSET 0x5dc
2315#define ALERT_HANDLER_ALERT_CAUSE_54_REG_RESVAL 0x0u
2316#define ALERT_HANDLER_ALERT_CAUSE_54_A_54_BIT 0
2319#define ALERT_HANDLER_ALERT_CAUSE_55_REG_OFFSET 0x5e0
2320#define ALERT_HANDLER_ALERT_CAUSE_55_REG_RESVAL 0x0u
2321#define ALERT_HANDLER_ALERT_CAUSE_55_A_55_BIT 0
2324#define ALERT_HANDLER_ALERT_CAUSE_56_REG_OFFSET 0x5e4
2325#define ALERT_HANDLER_ALERT_CAUSE_56_REG_RESVAL 0x0u
2326#define ALERT_HANDLER_ALERT_CAUSE_56_A_56_BIT 0
2329#define ALERT_HANDLER_ALERT_CAUSE_57_REG_OFFSET 0x5e8
2330#define ALERT_HANDLER_ALERT_CAUSE_57_REG_RESVAL 0x0u
2331#define ALERT_HANDLER_ALERT_CAUSE_57_A_57_BIT 0
2334#define ALERT_HANDLER_ALERT_CAUSE_58_REG_OFFSET 0x5ec
2335#define ALERT_HANDLER_ALERT_CAUSE_58_REG_RESVAL 0x0u
2336#define ALERT_HANDLER_ALERT_CAUSE_58_A_58_BIT 0
2339#define ALERT_HANDLER_ALERT_CAUSE_59_REG_OFFSET 0x5f0
2340#define ALERT_HANDLER_ALERT_CAUSE_59_REG_RESVAL 0x0u
2341#define ALERT_HANDLER_ALERT_CAUSE_59_A_59_BIT 0
2344#define ALERT_HANDLER_ALERT_CAUSE_60_REG_OFFSET 0x5f4
2345#define ALERT_HANDLER_ALERT_CAUSE_60_REG_RESVAL 0x0u
2346#define ALERT_HANDLER_ALERT_CAUSE_60_A_60_BIT 0
2349#define ALERT_HANDLER_ALERT_CAUSE_61_REG_OFFSET 0x5f8
2350#define ALERT_HANDLER_ALERT_CAUSE_61_REG_RESVAL 0x0u
2351#define ALERT_HANDLER_ALERT_CAUSE_61_A_61_BIT 0
2354#define ALERT_HANDLER_ALERT_CAUSE_62_REG_OFFSET 0x5fc
2355#define ALERT_HANDLER_ALERT_CAUSE_62_REG_RESVAL 0x0u
2356#define ALERT_HANDLER_ALERT_CAUSE_62_A_62_BIT 0
2359#define ALERT_HANDLER_ALERT_CAUSE_63_REG_OFFSET 0x600
2360#define ALERT_HANDLER_ALERT_CAUSE_63_REG_RESVAL 0x0u
2361#define ALERT_HANDLER_ALERT_CAUSE_63_A_63_BIT 0
2364#define ALERT_HANDLER_ALERT_CAUSE_64_REG_OFFSET 0x604
2365#define ALERT_HANDLER_ALERT_CAUSE_64_REG_RESVAL 0x0u
2366#define ALERT_HANDLER_ALERT_CAUSE_64_A_64_BIT 0
2369#define ALERT_HANDLER_ALERT_CAUSE_65_REG_OFFSET 0x608
2370#define ALERT_HANDLER_ALERT_CAUSE_65_REG_RESVAL 0x0u
2371#define ALERT_HANDLER_ALERT_CAUSE_65_A_65_BIT 0
2374#define ALERT_HANDLER_ALERT_CAUSE_66_REG_OFFSET 0x60c
2375#define ALERT_HANDLER_ALERT_CAUSE_66_REG_RESVAL 0x0u
2376#define ALERT_HANDLER_ALERT_CAUSE_66_A_66_BIT 0
2379#define ALERT_HANDLER_ALERT_CAUSE_67_REG_OFFSET 0x610
2380#define ALERT_HANDLER_ALERT_CAUSE_67_REG_RESVAL 0x0u
2381#define ALERT_HANDLER_ALERT_CAUSE_67_A_67_BIT 0
2384#define ALERT_HANDLER_ALERT_CAUSE_68_REG_OFFSET 0x614
2385#define ALERT_HANDLER_ALERT_CAUSE_68_REG_RESVAL 0x0u
2386#define ALERT_HANDLER_ALERT_CAUSE_68_A_68_BIT 0
2389#define ALERT_HANDLER_ALERT_CAUSE_69_REG_OFFSET 0x618
2390#define ALERT_HANDLER_ALERT_CAUSE_69_REG_RESVAL 0x0u
2391#define ALERT_HANDLER_ALERT_CAUSE_69_A_69_BIT 0
2394#define ALERT_HANDLER_ALERT_CAUSE_70_REG_OFFSET 0x61c
2395#define ALERT_HANDLER_ALERT_CAUSE_70_REG_RESVAL 0x0u
2396#define ALERT_HANDLER_ALERT_CAUSE_70_A_70_BIT 0
2399#define ALERT_HANDLER_ALERT_CAUSE_71_REG_OFFSET 0x620
2400#define ALERT_HANDLER_ALERT_CAUSE_71_REG_RESVAL 0x0u
2401#define ALERT_HANDLER_ALERT_CAUSE_71_A_71_BIT 0
2404#define ALERT_HANDLER_ALERT_CAUSE_72_REG_OFFSET 0x624
2405#define ALERT_HANDLER_ALERT_CAUSE_72_REG_RESVAL 0x0u
2406#define ALERT_HANDLER_ALERT_CAUSE_72_A_72_BIT 0
2409#define ALERT_HANDLER_ALERT_CAUSE_73_REG_OFFSET 0x628
2410#define ALERT_HANDLER_ALERT_CAUSE_73_REG_RESVAL 0x0u
2411#define ALERT_HANDLER_ALERT_CAUSE_73_A_73_BIT 0
2414#define ALERT_HANDLER_ALERT_CAUSE_74_REG_OFFSET 0x62c
2415#define ALERT_HANDLER_ALERT_CAUSE_74_REG_RESVAL 0x0u
2416#define ALERT_HANDLER_ALERT_CAUSE_74_A_74_BIT 0
2419#define ALERT_HANDLER_ALERT_CAUSE_75_REG_OFFSET 0x630
2420#define ALERT_HANDLER_ALERT_CAUSE_75_REG_RESVAL 0x0u
2421#define ALERT_HANDLER_ALERT_CAUSE_75_A_75_BIT 0
2424#define ALERT_HANDLER_ALERT_CAUSE_76_REG_OFFSET 0x634
2425#define ALERT_HANDLER_ALERT_CAUSE_76_REG_RESVAL 0x0u
2426#define ALERT_HANDLER_ALERT_CAUSE_76_A_76_BIT 0
2429#define ALERT_HANDLER_ALERT_CAUSE_77_REG_OFFSET 0x638
2430#define ALERT_HANDLER_ALERT_CAUSE_77_REG_RESVAL 0x0u
2431#define ALERT_HANDLER_ALERT_CAUSE_77_A_77_BIT 0
2434#define ALERT_HANDLER_ALERT_CAUSE_78_REG_OFFSET 0x63c
2435#define ALERT_HANDLER_ALERT_CAUSE_78_REG_RESVAL 0x0u
2436#define ALERT_HANDLER_ALERT_CAUSE_78_A_78_BIT 0
2439#define ALERT_HANDLER_ALERT_CAUSE_79_REG_OFFSET 0x640
2440#define ALERT_HANDLER_ALERT_CAUSE_79_REG_RESVAL 0x0u
2441#define ALERT_HANDLER_ALERT_CAUSE_79_A_79_BIT 0
2444#define ALERT_HANDLER_ALERT_CAUSE_80_REG_OFFSET 0x644
2445#define ALERT_HANDLER_ALERT_CAUSE_80_REG_RESVAL 0x0u
2446#define ALERT_HANDLER_ALERT_CAUSE_80_A_80_BIT 0
2449#define ALERT_HANDLER_ALERT_CAUSE_81_REG_OFFSET 0x648
2450#define ALERT_HANDLER_ALERT_CAUSE_81_REG_RESVAL 0x0u
2451#define ALERT_HANDLER_ALERT_CAUSE_81_A_81_BIT 0
2454#define ALERT_HANDLER_ALERT_CAUSE_82_REG_OFFSET 0x64c
2455#define ALERT_HANDLER_ALERT_CAUSE_82_REG_RESVAL 0x0u
2456#define ALERT_HANDLER_ALERT_CAUSE_82_A_82_BIT 0
2459#define ALERT_HANDLER_ALERT_CAUSE_83_REG_OFFSET 0x650
2460#define ALERT_HANDLER_ALERT_CAUSE_83_REG_RESVAL 0x0u
2461#define ALERT_HANDLER_ALERT_CAUSE_83_A_83_BIT 0
2464#define ALERT_HANDLER_ALERT_CAUSE_84_REG_OFFSET 0x654
2465#define ALERT_HANDLER_ALERT_CAUSE_84_REG_RESVAL 0x0u
2466#define ALERT_HANDLER_ALERT_CAUSE_84_A_84_BIT 0
2469#define ALERT_HANDLER_ALERT_CAUSE_85_REG_OFFSET 0x658
2470#define ALERT_HANDLER_ALERT_CAUSE_85_REG_RESVAL 0x0u
2471#define ALERT_HANDLER_ALERT_CAUSE_85_A_85_BIT 0
2474#define ALERT_HANDLER_ALERT_CAUSE_86_REG_OFFSET 0x65c
2475#define ALERT_HANDLER_ALERT_CAUSE_86_REG_RESVAL 0x0u
2476#define ALERT_HANDLER_ALERT_CAUSE_86_A_86_BIT 0
2479#define ALERT_HANDLER_ALERT_CAUSE_87_REG_OFFSET 0x660
2480#define ALERT_HANDLER_ALERT_CAUSE_87_REG_RESVAL 0x0u
2481#define ALERT_HANDLER_ALERT_CAUSE_87_A_87_BIT 0
2484#define ALERT_HANDLER_ALERT_CAUSE_88_REG_OFFSET 0x664
2485#define ALERT_HANDLER_ALERT_CAUSE_88_REG_RESVAL 0x0u
2486#define ALERT_HANDLER_ALERT_CAUSE_88_A_88_BIT 0
2489#define ALERT_HANDLER_ALERT_CAUSE_89_REG_OFFSET 0x668
2490#define ALERT_HANDLER_ALERT_CAUSE_89_REG_RESVAL 0x0u
2491#define ALERT_HANDLER_ALERT_CAUSE_89_A_89_BIT 0
2494#define ALERT_HANDLER_ALERT_CAUSE_90_REG_OFFSET 0x66c
2495#define ALERT_HANDLER_ALERT_CAUSE_90_REG_RESVAL 0x0u
2496#define ALERT_HANDLER_ALERT_CAUSE_90_A_90_BIT 0
2499#define ALERT_HANDLER_ALERT_CAUSE_91_REG_OFFSET 0x670
2500#define ALERT_HANDLER_ALERT_CAUSE_91_REG_RESVAL 0x0u
2501#define ALERT_HANDLER_ALERT_CAUSE_91_A_91_BIT 0
2504#define ALERT_HANDLER_ALERT_CAUSE_92_REG_OFFSET 0x674
2505#define ALERT_HANDLER_ALERT_CAUSE_92_REG_RESVAL 0x0u
2506#define ALERT_HANDLER_ALERT_CAUSE_92_A_92_BIT 0
2509#define ALERT_HANDLER_ALERT_CAUSE_93_REG_OFFSET 0x678
2510#define ALERT_HANDLER_ALERT_CAUSE_93_REG_RESVAL 0x0u
2511#define ALERT_HANDLER_ALERT_CAUSE_93_A_93_BIT 0
2514#define ALERT_HANDLER_ALERT_CAUSE_94_REG_OFFSET 0x67c
2515#define ALERT_HANDLER_ALERT_CAUSE_94_REG_RESVAL 0x0u
2516#define ALERT_HANDLER_ALERT_CAUSE_94_A_94_BIT 0
2519#define ALERT_HANDLER_ALERT_CAUSE_95_REG_OFFSET 0x680
2520#define ALERT_HANDLER_ALERT_CAUSE_95_REG_RESVAL 0x0u
2521#define ALERT_HANDLER_ALERT_CAUSE_95_A_95_BIT 0
2524#define ALERT_HANDLER_ALERT_CAUSE_96_REG_OFFSET 0x684
2525#define ALERT_HANDLER_ALERT_CAUSE_96_REG_RESVAL 0x0u
2526#define ALERT_HANDLER_ALERT_CAUSE_96_A_96_BIT 0
2529#define ALERT_HANDLER_ALERT_CAUSE_97_REG_OFFSET 0x688
2530#define ALERT_HANDLER_ALERT_CAUSE_97_REG_RESVAL 0x0u
2531#define ALERT_HANDLER_ALERT_CAUSE_97_A_97_BIT 0
2534#define ALERT_HANDLER_ALERT_CAUSE_98_REG_OFFSET 0x68c
2535#define ALERT_HANDLER_ALERT_CAUSE_98_REG_RESVAL 0x0u
2536#define ALERT_HANDLER_ALERT_CAUSE_98_A_98_BIT 0
2539#define ALERT_HANDLER_ALERT_CAUSE_99_REG_OFFSET 0x690
2540#define ALERT_HANDLER_ALERT_CAUSE_99_REG_RESVAL 0x0u
2541#define ALERT_HANDLER_ALERT_CAUSE_99_A_99_BIT 0
2544#define ALERT_HANDLER_ALERT_CAUSE_100_REG_OFFSET 0x694
2545#define ALERT_HANDLER_ALERT_CAUSE_100_REG_RESVAL 0x0u
2546#define ALERT_HANDLER_ALERT_CAUSE_100_A_100_BIT 0
2549#define ALERT_HANDLER_ALERT_CAUSE_101_REG_OFFSET 0x698
2550#define ALERT_HANDLER_ALERT_CAUSE_101_REG_RESVAL 0x0u
2551#define ALERT_HANDLER_ALERT_CAUSE_101_A_101_BIT 0
2554#define ALERT_HANDLER_ALERT_CAUSE_102_REG_OFFSET 0x69c
2555#define ALERT_HANDLER_ALERT_CAUSE_102_REG_RESVAL 0x0u
2556#define ALERT_HANDLER_ALERT_CAUSE_102_A_102_BIT 0
2559#define ALERT_HANDLER_ALERT_CAUSE_103_REG_OFFSET 0x6a0
2560#define ALERT_HANDLER_ALERT_CAUSE_103_REG_RESVAL 0x0u
2561#define ALERT_HANDLER_ALERT_CAUSE_103_A_103_BIT 0
2564#define ALERT_HANDLER_ALERT_CAUSE_104_REG_OFFSET 0x6a4
2565#define ALERT_HANDLER_ALERT_CAUSE_104_REG_RESVAL 0x0u
2566#define ALERT_HANDLER_ALERT_CAUSE_104_A_104_BIT 0
2569#define ALERT_HANDLER_LOC_ALERT_REGWEN_EN_FIELD_WIDTH 1
2570#define ALERT_HANDLER_LOC_ALERT_REGWEN_MULTIREG_COUNT 7
2573#define ALERT_HANDLER_LOC_ALERT_REGWEN_0_REG_OFFSET 0x6a8
2574#define ALERT_HANDLER_LOC_ALERT_REGWEN_0_REG_RESVAL 0x1u
2575#define ALERT_HANDLER_LOC_ALERT_REGWEN_0_EN_0_BIT 0
2578#define ALERT_HANDLER_LOC_ALERT_REGWEN_1_REG_OFFSET 0x6ac
2579#define ALERT_HANDLER_LOC_ALERT_REGWEN_1_REG_RESVAL 0x1u
2580#define ALERT_HANDLER_LOC_ALERT_REGWEN_1_EN_1_BIT 0
2583#define ALERT_HANDLER_LOC_ALERT_REGWEN_2_REG_OFFSET 0x6b0
2584#define ALERT_HANDLER_LOC_ALERT_REGWEN_2_REG_RESVAL 0x1u
2585#define ALERT_HANDLER_LOC_ALERT_REGWEN_2_EN_2_BIT 0
2588#define ALERT_HANDLER_LOC_ALERT_REGWEN_3_REG_OFFSET 0x6b4
2589#define ALERT_HANDLER_LOC_ALERT_REGWEN_3_REG_RESVAL 0x1u
2590#define ALERT_HANDLER_LOC_ALERT_REGWEN_3_EN_3_BIT 0
2593#define ALERT_HANDLER_LOC_ALERT_REGWEN_4_REG_OFFSET 0x6b8
2594#define ALERT_HANDLER_LOC_ALERT_REGWEN_4_REG_RESVAL 0x1u
2595#define ALERT_HANDLER_LOC_ALERT_REGWEN_4_EN_4_BIT 0
2598#define ALERT_HANDLER_LOC_ALERT_REGWEN_5_REG_OFFSET 0x6bc
2599#define ALERT_HANDLER_LOC_ALERT_REGWEN_5_REG_RESVAL 0x1u
2600#define ALERT_HANDLER_LOC_ALERT_REGWEN_5_EN_5_BIT 0
2603#define ALERT_HANDLER_LOC_ALERT_REGWEN_6_REG_OFFSET 0x6c0
2604#define ALERT_HANDLER_LOC_ALERT_REGWEN_6_REG_RESVAL 0x1u
2605#define ALERT_HANDLER_LOC_ALERT_REGWEN_6_EN_6_BIT 0
2608#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_EN_LA_FIELD_WIDTH 1
2609#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_MULTIREG_COUNT 7
2612#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0_REG_OFFSET 0x6c4
2613#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0_REG_RESVAL 0x0u
2614#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0_EN_LA_0_BIT 0
2617#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1_REG_OFFSET 0x6c8
2618#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1_REG_RESVAL 0x0u
2619#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1_EN_LA_1_BIT 0
2622#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2_REG_OFFSET 0x6cc
2623#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2_REG_RESVAL 0x0u
2624#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2_EN_LA_2_BIT 0
2627#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3_REG_OFFSET 0x6d0
2628#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3_REG_RESVAL 0x0u
2629#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3_EN_LA_3_BIT 0
2632#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4_REG_OFFSET 0x6d4
2633#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4_REG_RESVAL 0x0u
2634#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4_EN_LA_4_BIT 0
2637#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5_REG_OFFSET 0x6d8
2638#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5_REG_RESVAL 0x0u
2639#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5_EN_LA_5_BIT 0
2642#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6_REG_OFFSET 0x6dc
2643#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6_REG_RESVAL 0x0u
2644#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6_EN_LA_6_BIT 0
2647#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_CLASS_LA_FIELD_WIDTH 2
2648#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_MULTIREG_COUNT 7
2651#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_REG_OFFSET 0x6e0
2652#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_REG_RESVAL 0x0u
2653#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_MASK 0x3u
2654#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_OFFSET 0
2655#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_FIELD \
2656 ((bitfield_field32_t) { .mask = ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_MASK, .index = ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_OFFSET })
2657#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_VALUE_CLASSA 0x0
2658#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_VALUE_CLASSB 0x1
2659#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_VALUE_CLASSC 0x2
2660#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_VALUE_CLASSD 0x3
2663#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_REG_OFFSET 0x6e4
2664#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_REG_RESVAL 0x0u
2665#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_CLASS_LA_1_MASK 0x3u
2666#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_CLASS_LA_1_OFFSET 0
2667#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_CLASS_LA_1_FIELD \
2668 ((bitfield_field32_t) { .mask = ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_CLASS_LA_1_MASK, .index = ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_CLASS_LA_1_OFFSET })
2671#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_REG_OFFSET 0x6e8
2672#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_REG_RESVAL 0x0u
2673#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_CLASS_LA_2_MASK 0x3u
2674#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_CLASS_LA_2_OFFSET 0
2675#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_CLASS_LA_2_FIELD \
2676 ((bitfield_field32_t) { .mask = ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_CLASS_LA_2_MASK, .index = ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_CLASS_LA_2_OFFSET })
2679#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_REG_OFFSET 0x6ec
2680#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_REG_RESVAL 0x0u
2681#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_CLASS_LA_3_MASK 0x3u
2682#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_CLASS_LA_3_OFFSET 0
2683#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_CLASS_LA_3_FIELD \
2684 ((bitfield_field32_t) { .mask = ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_CLASS_LA_3_MASK, .index = ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_CLASS_LA_3_OFFSET })
2687#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_REG_OFFSET 0x6f0
2688#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_REG_RESVAL 0x0u
2689#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_CLASS_LA_4_MASK 0x3u
2690#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_CLASS_LA_4_OFFSET 0
2691#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_CLASS_LA_4_FIELD \
2692 ((bitfield_field32_t) { .mask = ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_CLASS_LA_4_MASK, .index = ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_CLASS_LA_4_OFFSET })
2695#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_REG_OFFSET 0x6f4
2696#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_REG_RESVAL 0x0u
2697#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_CLASS_LA_5_MASK 0x3u
2698#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_CLASS_LA_5_OFFSET 0
2699#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_CLASS_LA_5_FIELD \
2700 ((bitfield_field32_t) { .mask = ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_CLASS_LA_5_MASK, .index = ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_CLASS_LA_5_OFFSET })
2703#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_REG_OFFSET 0x6f8
2704#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_REG_RESVAL 0x0u
2705#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_CLASS_LA_6_MASK 0x3u
2706#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_CLASS_LA_6_OFFSET 0
2707#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_CLASS_LA_6_FIELD \
2708 ((bitfield_field32_t) { .mask = ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_CLASS_LA_6_MASK, .index = ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_CLASS_LA_6_OFFSET })
2711#define ALERT_HANDLER_LOC_ALERT_CAUSE_LA_FIELD_WIDTH 1
2712#define ALERT_HANDLER_LOC_ALERT_CAUSE_MULTIREG_COUNT 7
2715#define ALERT_HANDLER_LOC_ALERT_CAUSE_0_REG_OFFSET 0x6fc
2716#define ALERT_HANDLER_LOC_ALERT_CAUSE_0_REG_RESVAL 0x0u
2717#define ALERT_HANDLER_LOC_ALERT_CAUSE_0_LA_0_BIT 0
2720#define ALERT_HANDLER_LOC_ALERT_CAUSE_1_REG_OFFSET 0x700
2721#define ALERT_HANDLER_LOC_ALERT_CAUSE_1_REG_RESVAL 0x0u
2722#define ALERT_HANDLER_LOC_ALERT_CAUSE_1_LA_1_BIT 0
2725#define ALERT_HANDLER_LOC_ALERT_CAUSE_2_REG_OFFSET 0x704
2726#define ALERT_HANDLER_LOC_ALERT_CAUSE_2_REG_RESVAL 0x0u
2727#define ALERT_HANDLER_LOC_ALERT_CAUSE_2_LA_2_BIT 0
2730#define ALERT_HANDLER_LOC_ALERT_CAUSE_3_REG_OFFSET 0x708
2731#define ALERT_HANDLER_LOC_ALERT_CAUSE_3_REG_RESVAL 0x0u
2732#define ALERT_HANDLER_LOC_ALERT_CAUSE_3_LA_3_BIT 0
2735#define ALERT_HANDLER_LOC_ALERT_CAUSE_4_REG_OFFSET 0x70c
2736#define ALERT_HANDLER_LOC_ALERT_CAUSE_4_REG_RESVAL 0x0u
2737#define ALERT_HANDLER_LOC_ALERT_CAUSE_4_LA_4_BIT 0
2740#define ALERT_HANDLER_LOC_ALERT_CAUSE_5_REG_OFFSET 0x710
2741#define ALERT_HANDLER_LOC_ALERT_CAUSE_5_REG_RESVAL 0x0u
2742#define ALERT_HANDLER_LOC_ALERT_CAUSE_5_LA_5_BIT 0
2745#define ALERT_HANDLER_LOC_ALERT_CAUSE_6_REG_OFFSET 0x714
2746#define ALERT_HANDLER_LOC_ALERT_CAUSE_6_REG_RESVAL 0x0u
2747#define ALERT_HANDLER_LOC_ALERT_CAUSE_6_LA_6_BIT 0
2750#define ALERT_HANDLER_CLASSA_REGWEN_REG_OFFSET 0x718
2751#define ALERT_HANDLER_CLASSA_REGWEN_REG_RESVAL 0x1u
2752#define ALERT_HANDLER_CLASSA_REGWEN_CLASSA_REGWEN_BIT 0
2756#define ALERT_HANDLER_CLASSA_CTRL_SHADOWED_REG_OFFSET 0x71c
2757#define ALERT_HANDLER_CLASSA_CTRL_SHADOWED_REG_RESVAL 0x393cu
2758#define ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_BIT 0
2759#define ALERT_HANDLER_CLASSA_CTRL_SHADOWED_LOCK_BIT 1
2760#define ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_E0_BIT 2
2761#define ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_E1_BIT 3
2762#define ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_E2_BIT 4
2763#define ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_E3_BIT 5
2764#define ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E0_MASK 0x3u
2765#define ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E0_OFFSET 6
2766#define ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E0_FIELD \
2767 ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E0_MASK, .index = ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E0_OFFSET })
2768#define ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E1_MASK 0x3u
2769#define ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E1_OFFSET 8
2770#define ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E1_FIELD \
2771 ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E1_MASK, .index = ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E1_OFFSET })
2772#define ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E2_MASK 0x3u
2773#define ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E2_OFFSET 10
2774#define ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E2_FIELD \
2775 ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E2_MASK, .index = ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E2_OFFSET })
2776#define ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E3_MASK 0x3u
2777#define ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E3_OFFSET 12
2778#define ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E3_FIELD \
2779 ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E3_MASK, .index = ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E3_OFFSET })
2782#define ALERT_HANDLER_CLASSA_CLR_REGWEN_REG_OFFSET 0x720
2783#define ALERT_HANDLER_CLASSA_CLR_REGWEN_REG_RESVAL 0x1u
2784#define ALERT_HANDLER_CLASSA_CLR_REGWEN_CLASSA_CLR_REGWEN_BIT 0
2787#define ALERT_HANDLER_CLASSA_CLR_SHADOWED_REG_OFFSET 0x724
2788#define ALERT_HANDLER_CLASSA_CLR_SHADOWED_REG_RESVAL 0x0u
2789#define ALERT_HANDLER_CLASSA_CLR_SHADOWED_CLASSA_CLR_SHADOWED_BIT 0
2793#define ALERT_HANDLER_CLASSA_ACCUM_CNT_REG_OFFSET 0x728
2794#define ALERT_HANDLER_CLASSA_ACCUM_CNT_REG_RESVAL 0x0u
2795#define ALERT_HANDLER_CLASSA_ACCUM_CNT_CLASSA_ACCUM_CNT_MASK 0xffffu
2796#define ALERT_HANDLER_CLASSA_ACCUM_CNT_CLASSA_ACCUM_CNT_OFFSET 0
2797#define ALERT_HANDLER_CLASSA_ACCUM_CNT_CLASSA_ACCUM_CNT_FIELD \
2798 ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSA_ACCUM_CNT_CLASSA_ACCUM_CNT_MASK, .index = ALERT_HANDLER_CLASSA_ACCUM_CNT_CLASSA_ACCUM_CNT_OFFSET })
2801#define ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_REG_OFFSET 0x72c
2802#define ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_REG_RESVAL 0x0u
2803#define ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_CLASSA_ACCUM_THRESH_SHADOWED_MASK \
2805#define ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_CLASSA_ACCUM_THRESH_SHADOWED_OFFSET \
2807#define ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_CLASSA_ACCUM_THRESH_SHADOWED_FIELD \
2808 ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_CLASSA_ACCUM_THRESH_SHADOWED_MASK, .index = ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_CLASSA_ACCUM_THRESH_SHADOWED_OFFSET })
2811#define ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED_REG_OFFSET 0x730
2812#define ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED_REG_RESVAL 0x0u
2815#define ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_REG_OFFSET 0x734
2816#define ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_REG_RESVAL 0x0u
2817#define ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_MASK \
2819#define ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_OFFSET \
2821#define ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_FIELD \
2822 ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_MASK, .index = ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_OFFSET })
2825#define ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED_REG_OFFSET 0x738
2826#define ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED_REG_RESVAL 0x0u
2829#define ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED_REG_OFFSET 0x73c
2830#define ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED_REG_RESVAL 0x0u
2833#define ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED_REG_OFFSET 0x740
2834#define ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED_REG_RESVAL 0x0u
2837#define ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED_REG_OFFSET 0x744
2838#define ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED_REG_RESVAL 0x0u
2841#define ALERT_HANDLER_CLASSA_ESC_CNT_REG_OFFSET 0x748
2842#define ALERT_HANDLER_CLASSA_ESC_CNT_REG_RESVAL 0x0u
2845#define ALERT_HANDLER_CLASSA_STATE_REG_OFFSET 0x74c
2846#define ALERT_HANDLER_CLASSA_STATE_REG_RESVAL 0x0u
2847#define ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_MASK 0x7u
2848#define ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_OFFSET 0
2849#define ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_FIELD \
2850 ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_MASK, .index = ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_OFFSET })
2851#define ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_VALUE_IDLE 0x0
2852#define ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_VALUE_TIMEOUT 0x1
2853#define ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_VALUE_FSMERROR 0x2
2854#define ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_VALUE_TERMINAL 0x3
2855#define ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_VALUE_PHASE0 0x4
2856#define ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_VALUE_PHASE1 0x5
2857#define ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_VALUE_PHASE2 0x6
2858#define ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_VALUE_PHASE3 0x7
2861#define ALERT_HANDLER_CLASSB_REGWEN_REG_OFFSET 0x750
2862#define ALERT_HANDLER_CLASSB_REGWEN_REG_RESVAL 0x1u
2863#define ALERT_HANDLER_CLASSB_REGWEN_CLASSB_REGWEN_BIT 0
2867#define ALERT_HANDLER_CLASSB_CTRL_SHADOWED_REG_OFFSET 0x754
2868#define ALERT_HANDLER_CLASSB_CTRL_SHADOWED_REG_RESVAL 0x393cu
2869#define ALERT_HANDLER_CLASSB_CTRL_SHADOWED_EN_BIT 0
2870#define ALERT_HANDLER_CLASSB_CTRL_SHADOWED_LOCK_BIT 1
2871#define ALERT_HANDLER_CLASSB_CTRL_SHADOWED_EN_E0_BIT 2
2872#define ALERT_HANDLER_CLASSB_CTRL_SHADOWED_EN_E1_BIT 3
2873#define ALERT_HANDLER_CLASSB_CTRL_SHADOWED_EN_E2_BIT 4
2874#define ALERT_HANDLER_CLASSB_CTRL_SHADOWED_EN_E3_BIT 5
2875#define ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E0_MASK 0x3u
2876#define ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E0_OFFSET 6
2877#define ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E0_FIELD \
2878 ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E0_MASK, .index = ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E0_OFFSET })
2879#define ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E1_MASK 0x3u
2880#define ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E1_OFFSET 8
2881#define ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E1_FIELD \
2882 ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E1_MASK, .index = ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E1_OFFSET })
2883#define ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E2_MASK 0x3u
2884#define ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E2_OFFSET 10
2885#define ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E2_FIELD \
2886 ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E2_MASK, .index = ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E2_OFFSET })
2887#define ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E3_MASK 0x3u
2888#define ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E3_OFFSET 12
2889#define ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E3_FIELD \
2890 ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E3_MASK, .index = ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E3_OFFSET })
2893#define ALERT_HANDLER_CLASSB_CLR_REGWEN_REG_OFFSET 0x758
2894#define ALERT_HANDLER_CLASSB_CLR_REGWEN_REG_RESVAL 0x1u
2895#define ALERT_HANDLER_CLASSB_CLR_REGWEN_CLASSB_CLR_REGWEN_BIT 0
2898#define ALERT_HANDLER_CLASSB_CLR_SHADOWED_REG_OFFSET 0x75c
2899#define ALERT_HANDLER_CLASSB_CLR_SHADOWED_REG_RESVAL 0x0u
2900#define ALERT_HANDLER_CLASSB_CLR_SHADOWED_CLASSB_CLR_SHADOWED_BIT 0
2904#define ALERT_HANDLER_CLASSB_ACCUM_CNT_REG_OFFSET 0x760
2905#define ALERT_HANDLER_CLASSB_ACCUM_CNT_REG_RESVAL 0x0u
2906#define ALERT_HANDLER_CLASSB_ACCUM_CNT_CLASSB_ACCUM_CNT_MASK 0xffffu
2907#define ALERT_HANDLER_CLASSB_ACCUM_CNT_CLASSB_ACCUM_CNT_OFFSET 0
2908#define ALERT_HANDLER_CLASSB_ACCUM_CNT_CLASSB_ACCUM_CNT_FIELD \
2909 ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSB_ACCUM_CNT_CLASSB_ACCUM_CNT_MASK, .index = ALERT_HANDLER_CLASSB_ACCUM_CNT_CLASSB_ACCUM_CNT_OFFSET })
2912#define ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_REG_OFFSET 0x764
2913#define ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_REG_RESVAL 0x0u
2914#define ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_CLASSB_ACCUM_THRESH_SHADOWED_MASK \
2916#define ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_CLASSB_ACCUM_THRESH_SHADOWED_OFFSET \
2918#define ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_CLASSB_ACCUM_THRESH_SHADOWED_FIELD \
2919 ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_CLASSB_ACCUM_THRESH_SHADOWED_MASK, .index = ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_CLASSB_ACCUM_THRESH_SHADOWED_OFFSET })
2922#define ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED_REG_OFFSET 0x768
2923#define ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED_REG_RESVAL 0x0u
2926#define ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_REG_OFFSET 0x76c
2927#define ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_REG_RESVAL 0x0u
2928#define ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_MASK \
2930#define ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_OFFSET \
2932#define ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_FIELD \
2933 ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_MASK, .index = ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_OFFSET })
2936#define ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED_REG_OFFSET 0x770
2937#define ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED_REG_RESVAL 0x0u
2940#define ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED_REG_OFFSET 0x774
2941#define ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED_REG_RESVAL 0x0u
2944#define ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED_REG_OFFSET 0x778
2945#define ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED_REG_RESVAL 0x0u
2948#define ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED_REG_OFFSET 0x77c
2949#define ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED_REG_RESVAL 0x0u
2952#define ALERT_HANDLER_CLASSB_ESC_CNT_REG_OFFSET 0x780
2953#define ALERT_HANDLER_CLASSB_ESC_CNT_REG_RESVAL 0x0u
2956#define ALERT_HANDLER_CLASSB_STATE_REG_OFFSET 0x784
2957#define ALERT_HANDLER_CLASSB_STATE_REG_RESVAL 0x0u
2958#define ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_MASK 0x7u
2959#define ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_OFFSET 0
2960#define ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_FIELD \
2961 ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_MASK, .index = ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_OFFSET })
2962#define ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_VALUE_IDLE 0x0
2963#define ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_VALUE_TIMEOUT 0x1
2964#define ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_VALUE_FSMERROR 0x2
2965#define ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_VALUE_TERMINAL 0x3
2966#define ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_VALUE_PHASE0 0x4
2967#define ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_VALUE_PHASE1 0x5
2968#define ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_VALUE_PHASE2 0x6
2969#define ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_VALUE_PHASE3 0x7
2972#define ALERT_HANDLER_CLASSC_REGWEN_REG_OFFSET 0x788
2973#define ALERT_HANDLER_CLASSC_REGWEN_REG_RESVAL 0x1u
2974#define ALERT_HANDLER_CLASSC_REGWEN_CLASSC_REGWEN_BIT 0
2978#define ALERT_HANDLER_CLASSC_CTRL_SHADOWED_REG_OFFSET 0x78c
2979#define ALERT_HANDLER_CLASSC_CTRL_SHADOWED_REG_RESVAL 0x393cu
2980#define ALERT_HANDLER_CLASSC_CTRL_SHADOWED_EN_BIT 0
2981#define ALERT_HANDLER_CLASSC_CTRL_SHADOWED_LOCK_BIT 1
2982#define ALERT_HANDLER_CLASSC_CTRL_SHADOWED_EN_E0_BIT 2
2983#define ALERT_HANDLER_CLASSC_CTRL_SHADOWED_EN_E1_BIT 3
2984#define ALERT_HANDLER_CLASSC_CTRL_SHADOWED_EN_E2_BIT 4
2985#define ALERT_HANDLER_CLASSC_CTRL_SHADOWED_EN_E3_BIT 5
2986#define ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E0_MASK 0x3u
2987#define ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E0_OFFSET 6
2988#define ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E0_FIELD \
2989 ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E0_MASK, .index = ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E0_OFFSET })
2990#define ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E1_MASK 0x3u
2991#define ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E1_OFFSET 8
2992#define ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E1_FIELD \
2993 ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E1_MASK, .index = ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E1_OFFSET })
2994#define ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E2_MASK 0x3u
2995#define ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E2_OFFSET 10
2996#define ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E2_FIELD \
2997 ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E2_MASK, .index = ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E2_OFFSET })
2998#define ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E3_MASK 0x3u
2999#define ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E3_OFFSET 12
3000#define ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E3_FIELD \
3001 ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E3_MASK, .index = ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E3_OFFSET })
3004#define ALERT_HANDLER_CLASSC_CLR_REGWEN_REG_OFFSET 0x790
3005#define ALERT_HANDLER_CLASSC_CLR_REGWEN_REG_RESVAL 0x1u
3006#define ALERT_HANDLER_CLASSC_CLR_REGWEN_CLASSC_CLR_REGWEN_BIT 0
3009#define ALERT_HANDLER_CLASSC_CLR_SHADOWED_REG_OFFSET 0x794
3010#define ALERT_HANDLER_CLASSC_CLR_SHADOWED_REG_RESVAL 0x0u
3011#define ALERT_HANDLER_CLASSC_CLR_SHADOWED_CLASSC_CLR_SHADOWED_BIT 0
3015#define ALERT_HANDLER_CLASSC_ACCUM_CNT_REG_OFFSET 0x798
3016#define ALERT_HANDLER_CLASSC_ACCUM_CNT_REG_RESVAL 0x0u
3017#define ALERT_HANDLER_CLASSC_ACCUM_CNT_CLASSC_ACCUM_CNT_MASK 0xffffu
3018#define ALERT_HANDLER_CLASSC_ACCUM_CNT_CLASSC_ACCUM_CNT_OFFSET 0
3019#define ALERT_HANDLER_CLASSC_ACCUM_CNT_CLASSC_ACCUM_CNT_FIELD \
3020 ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSC_ACCUM_CNT_CLASSC_ACCUM_CNT_MASK, .index = ALERT_HANDLER_CLASSC_ACCUM_CNT_CLASSC_ACCUM_CNT_OFFSET })
3023#define ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_REG_OFFSET 0x79c
3024#define ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_REG_RESVAL 0x0u
3025#define ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_CLASSC_ACCUM_THRESH_SHADOWED_MASK \
3027#define ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_CLASSC_ACCUM_THRESH_SHADOWED_OFFSET \
3029#define ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_CLASSC_ACCUM_THRESH_SHADOWED_FIELD \
3030 ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_CLASSC_ACCUM_THRESH_SHADOWED_MASK, .index = ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_CLASSC_ACCUM_THRESH_SHADOWED_OFFSET })
3033#define ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED_REG_OFFSET 0x7a0
3034#define ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED_REG_RESVAL 0x0u
3037#define ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_REG_OFFSET 0x7a4
3038#define ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_REG_RESVAL 0x0u
3039#define ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_MASK \
3041#define ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_OFFSET \
3043#define ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_FIELD \
3044 ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_MASK, .index = ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_OFFSET })
3047#define ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED_REG_OFFSET 0x7a8
3048#define ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED_REG_RESVAL 0x0u
3051#define ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED_REG_OFFSET 0x7ac
3052#define ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED_REG_RESVAL 0x0u
3055#define ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED_REG_OFFSET 0x7b0
3056#define ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED_REG_RESVAL 0x0u
3059#define ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED_REG_OFFSET 0x7b4
3060#define ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED_REG_RESVAL 0x0u
3063#define ALERT_HANDLER_CLASSC_ESC_CNT_REG_OFFSET 0x7b8
3064#define ALERT_HANDLER_CLASSC_ESC_CNT_REG_RESVAL 0x0u
3067#define ALERT_HANDLER_CLASSC_STATE_REG_OFFSET 0x7bc
3068#define ALERT_HANDLER_CLASSC_STATE_REG_RESVAL 0x0u
3069#define ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_MASK 0x7u
3070#define ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_OFFSET 0
3071#define ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_FIELD \
3072 ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_MASK, .index = ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_OFFSET })
3073#define ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_VALUE_IDLE 0x0
3074#define ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_VALUE_TIMEOUT 0x1
3075#define ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_VALUE_FSMERROR 0x2
3076#define ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_VALUE_TERMINAL 0x3
3077#define ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_VALUE_PHASE0 0x4
3078#define ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_VALUE_PHASE1 0x5
3079#define ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_VALUE_PHASE2 0x6
3080#define ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_VALUE_PHASE3 0x7
3083#define ALERT_HANDLER_CLASSD_REGWEN_REG_OFFSET 0x7c0
3084#define ALERT_HANDLER_CLASSD_REGWEN_REG_RESVAL 0x1u
3085#define ALERT_HANDLER_CLASSD_REGWEN_CLASSD_REGWEN_BIT 0
3089#define ALERT_HANDLER_CLASSD_CTRL_SHADOWED_REG_OFFSET 0x7c4
3090#define ALERT_HANDLER_CLASSD_CTRL_SHADOWED_REG_RESVAL 0x393cu
3091#define ALERT_HANDLER_CLASSD_CTRL_SHADOWED_EN_BIT 0
3092#define ALERT_HANDLER_CLASSD_CTRL_SHADOWED_LOCK_BIT 1
3093#define ALERT_HANDLER_CLASSD_CTRL_SHADOWED_EN_E0_BIT 2
3094#define ALERT_HANDLER_CLASSD_CTRL_SHADOWED_EN_E1_BIT 3
3095#define ALERT_HANDLER_CLASSD_CTRL_SHADOWED_EN_E2_BIT 4
3096#define ALERT_HANDLER_CLASSD_CTRL_SHADOWED_EN_E3_BIT 5
3097#define ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E0_MASK 0x3u
3098#define ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E0_OFFSET 6
3099#define ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E0_FIELD \
3100 ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E0_MASK, .index = ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E0_OFFSET })
3101#define ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E1_MASK 0x3u
3102#define ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E1_OFFSET 8
3103#define ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E1_FIELD \
3104 ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E1_MASK, .index = ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E1_OFFSET })
3105#define ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E2_MASK 0x3u
3106#define ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E2_OFFSET 10
3107#define ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E2_FIELD \
3108 ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E2_MASK, .index = ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E2_OFFSET })
3109#define ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E3_MASK 0x3u
3110#define ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E3_OFFSET 12
3111#define ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E3_FIELD \
3112 ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E3_MASK, .index = ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E3_OFFSET })
3115#define ALERT_HANDLER_CLASSD_CLR_REGWEN_REG_OFFSET 0x7c8
3116#define ALERT_HANDLER_CLASSD_CLR_REGWEN_REG_RESVAL 0x1u
3117#define ALERT_HANDLER_CLASSD_CLR_REGWEN_CLASSD_CLR_REGWEN_BIT 0
3120#define ALERT_HANDLER_CLASSD_CLR_SHADOWED_REG_OFFSET 0x7cc
3121#define ALERT_HANDLER_CLASSD_CLR_SHADOWED_REG_RESVAL 0x0u
3122#define ALERT_HANDLER_CLASSD_CLR_SHADOWED_CLASSD_CLR_SHADOWED_BIT 0
3126#define ALERT_HANDLER_CLASSD_ACCUM_CNT_REG_OFFSET 0x7d0
3127#define ALERT_HANDLER_CLASSD_ACCUM_CNT_REG_RESVAL 0x0u
3128#define ALERT_HANDLER_CLASSD_ACCUM_CNT_CLASSD_ACCUM_CNT_MASK 0xffffu
3129#define ALERT_HANDLER_CLASSD_ACCUM_CNT_CLASSD_ACCUM_CNT_OFFSET 0
3130#define ALERT_HANDLER_CLASSD_ACCUM_CNT_CLASSD_ACCUM_CNT_FIELD \
3131 ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSD_ACCUM_CNT_CLASSD_ACCUM_CNT_MASK, .index = ALERT_HANDLER_CLASSD_ACCUM_CNT_CLASSD_ACCUM_CNT_OFFSET })
3134#define ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_REG_OFFSET 0x7d4
3135#define ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_REG_RESVAL 0x0u
3136#define ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_CLASSD_ACCUM_THRESH_SHADOWED_MASK \
3138#define ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_CLASSD_ACCUM_THRESH_SHADOWED_OFFSET \
3140#define ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_CLASSD_ACCUM_THRESH_SHADOWED_FIELD \
3141 ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_CLASSD_ACCUM_THRESH_SHADOWED_MASK, .index = ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_CLASSD_ACCUM_THRESH_SHADOWED_OFFSET })
3144#define ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED_REG_OFFSET 0x7d8
3145#define ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED_REG_RESVAL 0x0u
3148#define ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_REG_OFFSET 0x7dc
3149#define ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_REG_RESVAL 0x0u
3150#define ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_MASK \
3152#define ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_OFFSET \
3154#define ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_FIELD \
3155 ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_MASK, .index = ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_OFFSET })
3158#define ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED_REG_OFFSET 0x7e0
3159#define ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED_REG_RESVAL 0x0u
3162#define ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED_REG_OFFSET 0x7e4
3163#define ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED_REG_RESVAL 0x0u
3166#define ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED_REG_OFFSET 0x7e8
3167#define ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED_REG_RESVAL 0x0u
3170#define ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED_REG_OFFSET 0x7ec
3171#define ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED_REG_RESVAL 0x0u
3174#define ALERT_HANDLER_CLASSD_ESC_CNT_REG_OFFSET 0x7f0
3175#define ALERT_HANDLER_CLASSD_ESC_CNT_REG_RESVAL 0x0u
3178#define ALERT_HANDLER_CLASSD_STATE_REG_OFFSET 0x7f4
3179#define ALERT_HANDLER_CLASSD_STATE_REG_RESVAL 0x0u
3180#define ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_MASK 0x7u
3181#define ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_OFFSET 0
3182#define ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_FIELD \
3183 ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_MASK, .index = ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_OFFSET })
3184#define ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_VALUE_IDLE 0x0
3185#define ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_VALUE_TIMEOUT 0x1
3186#define ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_VALUE_FSMERROR 0x2
3187#define ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_VALUE_TERMINAL 0x3
3188#define ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_VALUE_PHASE0 0x4
3189#define ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_VALUE_PHASE1 0x5
3190#define ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_VALUE_PHASE2 0x6
3191#define ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_VALUE_PHASE3 0x7